/__w/smoldot/smoldot/repo/target/debug/build/cranelift-codegen-1a9fb3f4e6daaa71/out/isle_x64.rs
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1 | | // GENERATED BY ISLE. DO NOT EDIT! |
2 | | // |
3 | | // Generated automatically from the instruction-selection DSL code in: |
4 | | // - src/prelude.isle |
5 | | // - src/prelude_lower.isle |
6 | | // - src/isa/x64/inst.isle |
7 | | // - src/isa/x64/lower.isle |
8 | | // - /__w/smoldot/smoldot/repo/target/debug/build/cranelift-codegen-1a9fb3f4e6daaa71/out/clif_lower.isle |
9 | | |
10 | | use super::*; // Pulls in all external types. |
11 | | use std::marker::PhantomData; |
12 | | |
13 | | /// Context during lowering: an implementation of this trait |
14 | | /// must be provided with all external constructors and extractors. |
15 | | /// A mutable borrow is passed along through all lowering logic. |
16 | | pub trait Context { |
17 | | fn unit(&mut self, ) -> Unit; |
18 | | fn value_type(&mut self, arg0: Value) -> Type; |
19 | | fn u32_nonnegative(&mut self, arg0: u32) -> Option<u32>; |
20 | | fn offset32(&mut self, arg0: Offset32) -> u32; |
21 | | fn u32_lteq(&mut self, arg0: u32, arg1: u32) -> Option<Unit>; |
22 | | fn u8_lteq(&mut self, arg0: u8, arg1: u8) -> Option<Unit>; |
23 | | fn u8_lt(&mut self, arg0: u8, arg1: u8) -> Option<Unit>; |
24 | | fn simm32(&mut self, arg0: Imm64) -> Option<u32>; |
25 | | fn uimm8(&mut self, arg0: Imm64) -> Option<u8>; |
26 | | fn u8_as_u32(&mut self, arg0: u8) -> u32; |
27 | | fn u8_as_u64(&mut self, arg0: u8) -> u64; |
28 | | fn u16_as_u64(&mut self, arg0: u16) -> u64; |
29 | | fn u32_as_u64(&mut self, arg0: u32) -> u64; |
30 | | fn i64_as_u64(&mut self, arg0: i64) -> u64; |
31 | | fn i64_neg(&mut self, arg0: i64) -> i64; |
32 | | fn u128_as_u64(&mut self, arg0: u128) -> Option<u64>; |
33 | | fn u64_as_u32(&mut self, arg0: u64) -> Option<u32>; |
34 | | fn u64_as_i32(&mut self, arg0: u64) -> i32; |
35 | | fn u8_and(&mut self, arg0: u8, arg1: u8) -> u8; |
36 | | fn u32_add(&mut self, arg0: u32, arg1: u32) -> u32; |
37 | | fn s32_add_fallible(&mut self, arg0: u32, arg1: u32) -> Option<u32>; |
38 | | fn u64_add(&mut self, arg0: u64, arg1: u64) -> u64; |
39 | | fn u64_sub(&mut self, arg0: u64, arg1: u64) -> u64; |
40 | | fn u64_mul(&mut self, arg0: u64, arg1: u64) -> u64; |
41 | | fn u64_sdiv(&mut self, arg0: u64, arg1: u64) -> Option<u64>; |
42 | | fn u64_udiv(&mut self, arg0: u64, arg1: u64) -> Option<u64>; |
43 | | fn u64_and(&mut self, arg0: u64, arg1: u64) -> u64; |
44 | | fn u64_or(&mut self, arg0: u64, arg1: u64) -> u64; |
45 | | fn u64_xor(&mut self, arg0: u64, arg1: u64) -> u64; |
46 | | fn u64_shl(&mut self, arg0: u64, arg1: u64) -> u64; |
47 | | fn imm64_shl(&mut self, arg0: Type, arg1: Imm64, arg2: Imm64) -> Imm64; |
48 | | fn imm64_ushr(&mut self, arg0: Type, arg1: Imm64, arg2: Imm64) -> Imm64; |
49 | | fn imm64_sshr(&mut self, arg0: Type, arg1: Imm64, arg2: Imm64) -> Imm64; |
50 | | fn u64_not(&mut self, arg0: u64) -> u64; |
51 | | fn u64_eq(&mut self, arg0: u64, arg1: u64) -> bool; |
52 | | fn u64_le(&mut self, arg0: u64, arg1: u64) -> bool; |
53 | | fn u64_lt(&mut self, arg0: u64, arg1: u64) -> bool; |
54 | | fn i64_sextend_imm64(&mut self, arg0: Type, arg1: Imm64) -> i64; |
55 | | fn u64_uextend_imm64(&mut self, arg0: Type, arg1: Imm64) -> u64; |
56 | | fn imm64_icmp(&mut self, arg0: Type, arg1: &IntCC, arg2: Imm64, arg3: Imm64) -> Imm64; |
57 | | fn u64_is_zero(&mut self, arg0: u64) -> bool; |
58 | | fn u64_is_odd(&mut self, arg0: u64) -> bool; |
59 | | fn ty_umin(&mut self, arg0: Type) -> u64; |
60 | | fn ty_umax(&mut self, arg0: Type) -> u64; |
61 | | fn ty_smin(&mut self, arg0: Type) -> u64; |
62 | | fn ty_smax(&mut self, arg0: Type) -> u64; |
63 | | fn ty_bits(&mut self, arg0: Type) -> u8; |
64 | | fn ty_bits_u16(&mut self, arg0: Type) -> u16; |
65 | | fn ty_bits_u64(&mut self, arg0: Type) -> u64; |
66 | | fn ty_mask(&mut self, arg0: Type) -> u64; |
67 | | fn ty_bytes(&mut self, arg0: Type) -> u16; |
68 | | fn lane_type(&mut self, arg0: Type) -> Type; |
69 | | fn mem_flags_trusted(&mut self, ) -> MemFlags; |
70 | | fn intcc_reverse(&mut self, arg0: &IntCC) -> IntCC; |
71 | | fn intcc_inverse(&mut self, arg0: &IntCC) -> IntCC; |
72 | | fn floatcc_reverse(&mut self, arg0: &FloatCC) -> FloatCC; |
73 | | fn floatcc_inverse(&mut self, arg0: &FloatCC) -> FloatCC; |
74 | | fn floatcc_unordered(&mut self, arg0: &FloatCC) -> bool; |
75 | | fn fits_in_16(&mut self, arg0: Type) -> Option<Type>; |
76 | | fn fits_in_32(&mut self, arg0: Type) -> Option<Type>; |
77 | | fn lane_fits_in_32(&mut self, arg0: Type) -> Option<Type>; |
78 | | fn fits_in_64(&mut self, arg0: Type) -> Option<Type>; |
79 | | fn ty_32(&mut self, arg0: Type) -> Option<Type>; |
80 | | fn ty_64(&mut self, arg0: Type) -> Option<Type>; |
81 | | fn ty_int_ref_scalar_64(&mut self, arg0: Type) -> Option<Type>; |
82 | | fn ty_32_or_64(&mut self, arg0: Type) -> Option<Type>; |
83 | | fn ty_8_or_16(&mut self, arg0: Type) -> Option<Type>; |
84 | | fn int_fits_in_32(&mut self, arg0: Type) -> Option<Type>; |
85 | | fn ty_int_ref_64(&mut self, arg0: Type) -> Option<Type>; |
86 | | fn ty_int(&mut self, arg0: Type) -> Option<Type>; |
87 | | fn ty_scalar_float(&mut self, arg0: Type) -> Option<Type>; |
88 | | fn ty_float_or_vec(&mut self, arg0: Type) -> Option<Type>; |
89 | | fn ty_vector_float(&mut self, arg0: Type) -> Option<Type>; |
90 | | fn ty_vector_not_float(&mut self, arg0: Type) -> Option<Type>; |
91 | | fn ty_vec64(&mut self, arg0: Type) -> Option<Type>; |
92 | | fn ty_vec64_ctor(&mut self, arg0: Type) -> Option<Type>; |
93 | | fn ty_vec128(&mut self, arg0: Type) -> Option<Type>; |
94 | | fn ty_dyn_vec64(&mut self, arg0: Type) -> Option<Type>; |
95 | | fn ty_dyn_vec128(&mut self, arg0: Type) -> Option<Type>; |
96 | | fn ty_vec64_int(&mut self, arg0: Type) -> Option<Type>; |
97 | | fn ty_vec128_int(&mut self, arg0: Type) -> Option<Type>; |
98 | | fn ty_addr64(&mut self, arg0: Type) -> Option<Type>; |
99 | | fn not_vec32x2(&mut self, arg0: Type) -> Option<Type>; |
100 | | fn not_i64x2(&mut self, arg0: Type) -> Option<()>; |
101 | | fn u8_from_uimm8(&mut self, arg0: Uimm8) -> u8; |
102 | | fn u64_from_bool(&mut self, arg0: bool) -> u64; |
103 | | fn u64_from_imm64(&mut self, arg0: Imm64) -> u64; |
104 | | fn nonzero_u64_from_imm64(&mut self, arg0: Imm64) -> Option<u64>; |
105 | | fn imm64_power_of_two(&mut self, arg0: Imm64) -> Option<u64>; |
106 | | fn imm64(&mut self, arg0: u64) -> Imm64; |
107 | | fn imm64_masked(&mut self, arg0: Type, arg1: u64) -> Imm64; |
108 | | fn u32_from_ieee32(&mut self, arg0: Ieee32) -> u32; |
109 | | fn u64_from_ieee64(&mut self, arg0: Ieee64) -> u64; |
110 | | fn multi_lane(&mut self, arg0: Type) -> Option<(u32, u32)>; |
111 | | fn dynamic_lane(&mut self, arg0: Type) -> Option<(u32, u32)>; |
112 | | fn dynamic_int_lane(&mut self, arg0: Type) -> Option<u32>; |
113 | | fn dynamic_fp_lane(&mut self, arg0: Type) -> Option<u32>; |
114 | | fn ty_dyn64_int(&mut self, arg0: Type) -> Option<Type>; |
115 | | fn ty_dyn128_int(&mut self, arg0: Type) -> Option<Type>; |
116 | | fn offset32_to_u32(&mut self, arg0: Offset32) -> u32; |
117 | | fn u32_to_offset32(&mut self, arg0: u32) -> Offset32; |
118 | | fn intcc_unsigned(&mut self, arg0: &IntCC) -> IntCC; |
119 | | fn signed_cond_code(&mut self, arg0: &IntCC) -> Option<IntCC>; |
120 | | fn trap_code_division_by_zero(&mut self, ) -> TrapCode; |
121 | | fn trap_code_integer_overflow(&mut self, ) -> TrapCode; |
122 | | fn trap_code_bad_conversion_to_integer(&mut self, ) -> TrapCode; |
123 | | fn range(&mut self, arg0: usize, arg1: usize) -> Range; |
124 | | fn range_view(&mut self, arg0: Range) -> RangeView; |
125 | | fn value_reg(&mut self, arg0: Reg) -> ValueRegs; |
126 | | fn value_regs(&mut self, arg0: Reg, arg1: Reg) -> ValueRegs; |
127 | | fn value_regs_invalid(&mut self, ) -> ValueRegs; |
128 | | fn output_none(&mut self, ) -> InstOutput; |
129 | | fn output(&mut self, arg0: ValueRegs) -> InstOutput; |
130 | | fn output_pair(&mut self, arg0: ValueRegs, arg1: ValueRegs) -> InstOutput; |
131 | | fn output_builder_new(&mut self, ) -> InstOutputBuilder; |
132 | | fn output_builder_push(&mut self, arg0: &InstOutputBuilder, arg1: ValueRegs) -> Unit; |
133 | | fn output_builder_finish(&mut self, arg0: &InstOutputBuilder) -> InstOutput; |
134 | | fn temp_writable_reg(&mut self, arg0: Type) -> WritableReg; |
135 | | fn is_valid_reg(&mut self, arg0: Reg) -> bool; |
136 | | fn invalid_reg(&mut self, ) -> Reg; |
137 | | fn mark_value_used(&mut self, arg0: Value) -> Unit; |
138 | | fn put_in_reg(&mut self, arg0: Value) -> Reg; |
139 | | fn put_in_regs(&mut self, arg0: Value) -> ValueRegs; |
140 | | fn ensure_in_vreg(&mut self, arg0: Reg, arg1: Type) -> Reg; |
141 | | fn value_regs_get(&mut self, arg0: ValueRegs, arg1: usize) -> Reg; |
142 | | fn value_regs_len(&mut self, arg0: ValueRegs) -> usize; |
143 | | fn preg_to_reg(&mut self, arg0: PReg) -> Reg; |
144 | | fn value_list_slice(&mut self, arg0: ValueList) -> ValueSlice; |
145 | | fn value_slice_empty(&mut self, arg0: ValueSlice) -> Option<()>; |
146 | | fn value_slice_unwrap(&mut self, arg0: ValueSlice) -> Option<(Value, ValueSlice)>; |
147 | | fn value_slice_len(&mut self, arg0: ValueSlice) -> usize; |
148 | | fn value_slice_get(&mut self, arg0: ValueSlice, arg1: usize) -> Value; |
149 | | fn writable_reg_to_reg(&mut self, arg0: WritableReg) -> Reg; |
150 | | fn inst_results(&mut self, arg0: Inst) -> ValueSlice; |
151 | | fn first_result(&mut self, arg0: Inst) -> Option<Value>; |
152 | | fn inst_data(&mut self, arg0: Inst) -> InstructionData; |
153 | | fn def_inst(&mut self, arg0: Value) -> Option<Inst>; |
154 | | fn zero_value(&mut self, arg0: Value) -> Option<Value>; |
155 | | fn is_sinkable_inst(&mut self, arg0: Value) -> Option<Inst>; |
156 | | fn maybe_uextend(&mut self, arg0: Value) -> Option<Value>; |
157 | | fn emit(&mut self, arg0: &MInst) -> Unit; |
158 | | fn sink_inst(&mut self, arg0: Inst) -> Unit; |
159 | | fn emit_u64_le_const(&mut self, arg0: u64) -> VCodeConstant; |
160 | | fn emit_u128_le_const(&mut self, arg0: u128) -> VCodeConstant; |
161 | | fn const_to_vconst(&mut self, arg0: Constant) -> VCodeConstant; |
162 | | fn tls_model(&mut self, arg0: Type) -> TlsModel; |
163 | | fn tls_model_is_elf_gd(&mut self, ) -> Option<Unit>; |
164 | | fn tls_model_is_macho(&mut self, ) -> Option<Unit>; |
165 | | fn tls_model_is_coff(&mut self, ) -> Option<Unit>; |
166 | | fn preserve_frame_pointers(&mut self, ) -> Option<Unit>; |
167 | | fn box_external_name(&mut self, arg0: ExternalName) -> BoxExternalName; |
168 | | fn func_ref_data(&mut self, arg0: FuncRef) -> (SigRef, ExternalName, RelocDistance); |
169 | | fn symbol_value_data(&mut self, arg0: GlobalValue) -> Option<(ExternalName, RelocDistance, i64)>; |
170 | | fn reloc_distance_near(&mut self, arg0: RelocDistance) -> Option<()>; |
171 | | fn vec_mask_from_immediate(&mut self, arg0: Immediate) -> Option<VecMask>; |
172 | | fn u128_from_immediate(&mut self, arg0: Immediate) -> Option<u128>; |
173 | | fn u128_from_constant(&mut self, arg0: Constant) -> Option<u128>; |
174 | | fn u64_from_constant(&mut self, arg0: Constant) -> Option<u64>; |
175 | | fn shuffle64_from_imm(&mut self, arg0: Immediate) -> Option<(u8, u8)>; |
176 | | fn shuffle32_from_imm(&mut self, arg0: Immediate) -> Option<(u8, u8, u8, u8)>; |
177 | | fn shuffle16_from_imm(&mut self, arg0: Immediate) -> Option<(u8, u8, u8, u8, u8, u8, u8, u8)>; |
178 | | fn only_writable_reg(&mut self, arg0: WritableValueRegs) -> Option<WritableReg>; |
179 | | fn writable_regs_get(&mut self, arg0: WritableValueRegs, arg1: usize) -> WritableReg; |
180 | | fn abi_num_args(&mut self, arg0: Sig) -> usize; |
181 | | fn abi_get_arg(&mut self, arg0: Sig, arg1: usize) -> ABIArg; |
182 | | fn abi_num_rets(&mut self, arg0: Sig) -> usize; |
183 | | fn abi_get_ret(&mut self, arg0: Sig, arg1: usize) -> ABIArg; |
184 | | fn abi_ret_arg(&mut self, arg0: Sig) -> Option<ABIArg>; |
185 | | fn abi_no_ret_arg(&mut self, arg0: Sig) -> Option<()>; |
186 | | fn abi_sized_stack_arg_space(&mut self, arg0: Sig) -> i64; |
187 | | fn abi_sized_stack_ret_space(&mut self, arg0: Sig) -> i64; |
188 | | fn abi_stackslot_addr(&mut self, arg0: WritableReg, arg1: StackSlot, arg2: Offset32) -> MInst; |
189 | | fn abi_dynamic_stackslot_addr(&mut self, arg0: WritableReg, arg1: DynamicStackSlot) -> MInst; |
190 | | fn abi_arg_only_slot(&mut self, arg0: &ABIArg) -> Option<ABIArgSlot>; |
191 | | fn abi_arg_struct_pointer(&mut self, arg0: &ABIArg) -> Option<(ABIArgSlot, i64, u64)>; |
192 | | fn abi_arg_implicit_pointer(&mut self, arg0: &ABIArg) -> Option<(ABIArgSlot, i64, Type)>; |
193 | | fn real_reg_to_reg(&mut self, arg0: RealReg) -> Reg; |
194 | | fn real_reg_to_writable_reg(&mut self, arg0: RealReg) -> WritableReg; |
195 | | fn gen_move(&mut self, arg0: Type, arg1: WritableReg, arg2: Reg) -> MInst; |
196 | | fn gen_return(&mut self, arg0: ValueSlice) -> Unit; |
197 | | fn safe_divisor_from_imm64(&mut self, arg0: Type, arg1: Imm64) -> Option<u64>; |
198 | | fn jump_table_size(&mut self, arg0: &BoxVecMachLabel) -> u32; |
199 | | fn single_target(&mut self, arg0: &MachLabelSlice) -> Option<MachLabel>; |
200 | | fn two_targets(&mut self, arg0: &MachLabelSlice) -> Option<(MachLabel, MachLabel)>; |
201 | | fn jump_table_targets(&mut self, arg0: &MachLabelSlice) -> Option<(MachLabel, BoxVecMachLabel)>; |
202 | | fn operand_size_of_type_32_64(&mut self, arg0: Type) -> OperandSize; |
203 | | fn raw_operand_size_of_type(&mut self, arg0: Type) -> OperandSize; |
204 | | fn put_in_reg_mem_imm(&mut self, arg0: Value) -> RegMemImm; |
205 | | fn put_in_reg_mem(&mut self, arg0: Value) -> RegMem; |
206 | | fn synthetic_amode_to_reg_mem(&mut self, arg0: &SyntheticAmode) -> RegMem; |
207 | | fn amode_to_synthetic_amode(&mut self, arg0: &Amode) -> SyntheticAmode; |
208 | | fn sum_extend_fits_in_32_bits(&mut self, arg0: Type, arg1: Imm64, arg2: Offset32) -> Option<u32>; |
209 | | fn amode_offset(&mut self, arg0: &Amode, arg1: u32) -> Amode; |
210 | | fn zero_offset(&mut self, ) -> Offset32; |
211 | | fn intcc_to_cc(&mut self, arg0: &IntCC) -> CC; |
212 | | fn cc_invert(&mut self, arg0: &CC) -> CC; |
213 | | fn cc_nz_or_z(&mut self, arg0: &CC) -> Option<CC>; |
214 | | fn encode_fcmp_imm(&mut self, arg0: &FcmpImm) -> u8; |
215 | | fn encode_round_imm(&mut self, arg0: &RoundImm) -> u8; |
216 | | fn imm8_reg_to_imm8_gpr(&mut self, arg0: &Imm8Reg) -> Imm8Gpr; |
217 | | fn writable_gpr_to_reg(&mut self, arg0: WritableGpr) -> WritableReg; |
218 | | fn writable_xmm_to_reg(&mut self, arg0: WritableXmm) -> WritableReg; |
219 | | fn writable_reg_to_xmm(&mut self, arg0: WritableReg) -> WritableXmm; |
220 | | fn writable_xmm_to_xmm(&mut self, arg0: WritableXmm) -> Xmm; |
221 | | fn writable_gpr_to_gpr(&mut self, arg0: WritableGpr) -> Gpr; |
222 | | fn gpr_to_reg(&mut self, arg0: Gpr) -> Reg; |
223 | | fn gpr_to_gpr_mem(&mut self, arg0: Gpr) -> GprMem; |
224 | | fn gpr_to_gpr_mem_imm(&mut self, arg0: Gpr) -> GprMemImm; |
225 | | fn xmm_to_reg(&mut self, arg0: Xmm) -> Reg; |
226 | | fn xmm_to_xmm_mem_imm(&mut self, arg0: Xmm) -> XmmMemImm; |
227 | | fn xmm_mem_to_xmm_mem_imm(&mut self, arg0: &XmmMem) -> XmmMemImm; |
228 | | fn xmm_mem_to_xmm_mem_aligned(&mut self, arg0: &XmmMem) -> XmmMemAligned; |
229 | | fn xmm_mem_imm_to_xmm_mem_aligned_imm(&mut self, arg0: &XmmMemImm) -> XmmMemAlignedImm; |
230 | | fn temp_writable_gpr(&mut self, ) -> WritableGpr; |
231 | | fn temp_writable_xmm(&mut self, ) -> WritableXmm; |
232 | | fn reg_mem_to_xmm_mem(&mut self, arg0: &RegMem) -> XmmMem; |
233 | | fn reg_to_reg_mem_imm(&mut self, arg0: Reg) -> RegMemImm; |
234 | | fn gpr_mem_imm_new(&mut self, arg0: &RegMemImm) -> GprMemImm; |
235 | | fn xmm_mem_imm_new(&mut self, arg0: &RegMemImm) -> XmmMemImm; |
236 | | fn xmm_to_xmm_mem(&mut self, arg0: Xmm) -> XmmMem; |
237 | | fn xmm_mem_to_reg_mem(&mut self, arg0: &XmmMem) -> RegMem; |
238 | | fn gpr_mem_to_reg_mem(&mut self, arg0: &GprMem) -> RegMem; |
239 | | fn xmm_new(&mut self, arg0: Reg) -> Xmm; |
240 | | fn gpr_new(&mut self, arg0: Reg) -> Gpr; |
241 | | fn reg_mem_to_gpr_mem(&mut self, arg0: &RegMem) -> GprMem; |
242 | | fn reg_to_gpr_mem(&mut self, arg0: Reg) -> GprMem; |
243 | | fn put_in_xmm_mem(&mut self, arg0: Value) -> XmmMem; |
244 | | fn put_in_xmm_mem_imm(&mut self, arg0: Value) -> XmmMemImm; |
245 | | fn gpr_to_imm8_gpr(&mut self, arg0: Gpr) -> Imm8Gpr; |
246 | | fn imm8_to_imm8_gpr(&mut self, arg0: u8) -> Imm8Gpr; |
247 | | fn xmi_imm(&mut self, arg0: u32) -> XmmMemImm; |
248 | | fn intcc_without_eq(&mut self, arg0: &IntCC) -> IntCC; |
249 | | fn type_register_class(&mut self, arg0: Type) -> Option<RegisterClass>; |
250 | | fn avx512vl_enabled(&mut self, arg0: Type) -> bool; |
251 | | fn avx512dq_enabled(&mut self, arg0: Type) -> bool; |
252 | | fn avx512f_enabled(&mut self, arg0: Type) -> bool; |
253 | | fn avx512bitalg_enabled(&mut self, arg0: Type) -> bool; |
254 | | fn avx512vbmi_enabled(&mut self, arg0: Type) -> bool; |
255 | | fn use_lzcnt(&mut self, arg0: Type) -> bool; |
256 | | fn use_bmi1(&mut self, arg0: Type) -> bool; |
257 | | fn use_popcnt(&mut self, arg0: Type) -> bool; |
258 | | fn use_fma(&mut self, ) -> bool; |
259 | | fn use_sse41(&mut self, arg0: Type) -> bool; |
260 | | fn use_avx_simd(&mut self, ) -> bool; |
261 | | fn use_avx2_simd(&mut self, ) -> bool; |
262 | | fn imm8_from_value(&mut self, arg0: Value) -> Option<Imm8Reg>; |
263 | | fn const_to_type_masked_imm8(&mut self, arg0: u64, arg1: Type) -> Imm8Gpr; |
264 | | fn shift_mask(&mut self, arg0: Type) -> u32; |
265 | | fn shift_amount_masked(&mut self, arg0: Type, arg1: Imm64) -> u32; |
266 | | fn simm32_from_value(&mut self, arg0: Value) -> Option<GprMemImm>; |
267 | | fn simm32_from_imm64(&mut self, arg0: Imm64) -> Option<GprMemImm>; |
268 | | fn sinkable_load(&mut self, arg0: Value) -> Option<SinkableLoad>; |
269 | | fn sinkable_load_exact(&mut self, arg0: Value) -> Option<SinkableLoad>; |
270 | | fn sink_load(&mut self, arg0: &SinkableLoad) -> SyntheticAmode; |
271 | | fn ext_mode(&mut self, arg0: u16, arg1: u16) -> ExtMode; |
272 | | fn gen_call(&mut self, arg0: SigRef, arg1: ExternalName, arg2: RelocDistance, arg3: ValueSlice) -> InstOutput; |
273 | | fn gen_call_indirect(&mut self, arg0: SigRef, arg1: Value, arg2: ValueSlice) -> InstOutput; |
274 | | fn nonzero_u64_fits_in_u32(&mut self, arg0: u64) -> Option<u64>; |
275 | | fn fcvt_uint_mask_const(&mut self, ) -> VCodeConstant; |
276 | | fn fcvt_uint_mask_high_const(&mut self, ) -> VCodeConstant; |
277 | | fn iadd_pairwise_mul_const_16(&mut self, ) -> VCodeConstant; |
278 | | fn iadd_pairwise_mul_const_32(&mut self, ) -> VCodeConstant; |
279 | | fn iadd_pairwise_xor_const_32(&mut self, ) -> VCodeConstant; |
280 | | fn iadd_pairwise_addd_const_32(&mut self, ) -> VCodeConstant; |
281 | | fn snarrow_umax_mask(&mut self, ) -> VCodeConstant; |
282 | | fn ty_int_bool_or_ref(&mut self, arg0: Type) -> Option<()>; |
283 | | fn atomic_rmw_op_to_mach_atomic_rmw_op(&mut self, arg0: &AtomicRmwOp) -> MachAtomicRmwOp; |
284 | | fn shuffle_0_31_mask(&mut self, arg0: &VecMask) -> VCodeConstant; |
285 | | fn shuffle_0_15_mask(&mut self, arg0: &VecMask) -> VCodeConstant; |
286 | | fn shuffle_16_31_mask(&mut self, arg0: &VecMask) -> VCodeConstant; |
287 | | fn perm_from_mask(&mut self, arg0: &VecMask) -> VCodeConstant; |
288 | | fn perm_from_mask_with_zeros(&mut self, arg0: &VecMask) -> Option<(VCodeConstant, VCodeConstant)>; |
289 | | fn swizzle_zero_mask(&mut self, ) -> VCodeConstant; |
290 | | fn sqmul_round_sat_mask(&mut self, ) -> VCodeConstant; |
291 | | fn uunarrow_umax_mask(&mut self, ) -> VCodeConstant; |
292 | | fn uunarrow_uint_mask(&mut self, ) -> VCodeConstant; |
293 | | fn const_to_synthetic_amode(&mut self, arg0: VCodeConstant) -> SyntheticAmode; |
294 | | fn preg_rbp(&mut self, ) -> PReg; |
295 | | fn preg_rsp(&mut self, ) -> PReg; |
296 | | fn preg_pinned(&mut self, ) -> PReg; |
297 | | fn libcall_1(&mut self, arg0: &LibCall, arg1: Reg) -> Reg; |
298 | | fn libcall_3(&mut self, arg0: &LibCall, arg1: Reg, arg2: Reg, arg3: Reg) -> Reg; |
299 | | fn ishl_i8x16_mask_for_const(&mut self, arg0: u32) -> SyntheticAmode; |
300 | | fn ishl_i8x16_mask_table(&mut self, ) -> SyntheticAmode; |
301 | | fn ushr_i8x16_mask_for_const(&mut self, arg0: u32) -> SyntheticAmode; |
302 | | fn ushr_i8x16_mask_table(&mut self, ) -> SyntheticAmode; |
303 | | fn vconst_all_ones_or_all_zeros(&mut self, arg0: Constant) -> Option<()>; |
304 | | fn sse_insertps_lane_imm(&mut self, arg0: u8) -> u8; |
305 | | fn popcount_4bit_table(&mut self, ) -> VCodeConstant; |
306 | | fn popcount_low_mask(&mut self, ) -> VCodeConstant; |
307 | | fn pblendw_imm(&mut self, arg0: Immediate) -> Option<u8>; |
308 | | fn palignr_imm_from_immediate(&mut self, arg0: Immediate) -> Option<u8>; |
309 | | fn pshuflw_lhs_imm(&mut self, arg0: Immediate) -> Option<u8>; |
310 | | fn pshuflw_rhs_imm(&mut self, arg0: Immediate) -> Option<u8>; |
311 | | fn pshufhw_lhs_imm(&mut self, arg0: Immediate) -> Option<u8>; |
312 | | fn pshufhw_rhs_imm(&mut self, arg0: Immediate) -> Option<u8>; |
313 | | fn pshufd_lhs_imm(&mut self, arg0: Immediate) -> Option<u8>; |
314 | | fn pshufd_rhs_imm(&mut self, arg0: Immediate) -> Option<u8>; |
315 | | fn shufps_imm(&mut self, arg0: Immediate) -> Option<u8>; |
316 | | fn shufps_rev_imm(&mut self, arg0: Immediate) -> Option<u8>; |
317 | | fn unpack_value_array_2(&mut self, arg0: &ValueArray2) -> (Value, Value); |
318 | | fn pack_value_array_2(&mut self, arg0: Value, arg1: Value) -> ValueArray2; |
319 | | fn unpack_value_array_3(&mut self, arg0: &ValueArray3) -> (Value, Value, Value); |
320 | | fn pack_value_array_3(&mut self, arg0: Value, arg1: Value, arg2: Value) -> ValueArray3; |
321 | | fn unpack_block_array_2(&mut self, arg0: &BlockArray2) -> (BlockCall, BlockCall); |
322 | | fn pack_block_array_2(&mut self, arg0: BlockCall, arg1: BlockCall) -> BlockArray2; |
323 | | } |
324 | | |
325 | | pub trait ContextIter { |
326 | | type Context; |
327 | | type Output; |
328 | | fn next(&mut self, ctx: &mut Self::Context) -> Option<Self::Output>; |
329 | | } |
330 | | |
331 | | pub struct ContextIterWrapper<Item, I: Iterator < Item = Item>, C: Context> { |
332 | | iter: I, |
333 | | _ctx: PhantomData<C>, |
334 | | } |
335 | | impl<Item, I: Iterator<Item = Item>, C: Context> From<I> for ContextIterWrapper<Item, I, C> { |
336 | 0 | fn from(iter: I) -> Self { |
337 | 0 | Self { iter, _ctx: PhantomData } |
338 | 0 | } |
339 | | } |
340 | | impl<Item, I: Iterator<Item = Item>, C: Context> ContextIter for ContextIterWrapper<Item, I, C> { |
341 | | type Context = C; |
342 | | type Output = Item; |
343 | 0 | fn next(&mut self, _ctx: &mut Self::Context) -> Option<Self::Output> { |
344 | 0 | self.iter.next() |
345 | 0 | } |
346 | | } |
347 | | |
348 | | |
349 | | /// Internal type SideEffectNoResult: defined at src/prelude_lower.isle line 282. |
350 | 164k | #[derive(Clone, D0 ebug0 )] |
351 | | pub enum SideEffectNoResult { |
352 | | Inst { |
353 | | inst: MInst, |
354 | | }, |
355 | | Inst2 { |
356 | | inst1: MInst, |
357 | | inst2: MInst, |
358 | | }, |
359 | | Inst3 { |
360 | | inst1: MInst, |
361 | | inst2: MInst, |
362 | | inst3: MInst, |
363 | | }, |
364 | | } |
365 | | |
366 | | /// Internal type ProducesFlags: defined at src/prelude_lower.isle line 324. |
367 | 748k | #[derive(Clone, D0 ebug0 )] |
368 | | pub enum ProducesFlags { |
369 | | AlreadyExistingFlags, |
370 | | ProducesFlagsSideEffect { |
371 | | inst: MInst, |
372 | | }, |
373 | | ProducesFlagsTwiceSideEffect { |
374 | | inst1: MInst, |
375 | | inst2: MInst, |
376 | | }, |
377 | | ProducesFlagsReturnsReg { |
378 | | inst: MInst, |
379 | | result: Reg, |
380 | | }, |
381 | | ProducesFlagsReturnsResultWithConsumer { |
382 | | inst: MInst, |
383 | | result: Reg, |
384 | | }, |
385 | | } |
386 | | |
387 | | /// Internal type ConsumesFlags: defined at src/prelude_lower.isle line 346. |
388 | 9.18k | #[derive(Clone, D0 ebug0 )] |
389 | | pub enum ConsumesFlags { |
390 | | ConsumesFlagsSideEffect { |
391 | | inst: MInst, |
392 | | }, |
393 | | ConsumesFlagsSideEffect2 { |
394 | | inst1: MInst, |
395 | | inst2: MInst, |
396 | | }, |
397 | | ConsumesFlagsReturnsResultWithProducer { |
398 | | inst: MInst, |
399 | | result: Reg, |
400 | | }, |
401 | | ConsumesFlagsReturnsReg { |
402 | | inst: MInst, |
403 | | result: Reg, |
404 | | }, |
405 | | ConsumesFlagsTwiceReturnsValueRegs { |
406 | | inst1: MInst, |
407 | | inst2: MInst, |
408 | | result: ValueRegs, |
409 | | }, |
410 | | ConsumesFlagsFourTimesReturnsValueRegs { |
411 | | inst1: MInst, |
412 | | inst2: MInst, |
413 | | inst3: MInst, |
414 | | inst4: MInst, |
415 | | result: ValueRegs, |
416 | | }, |
417 | | } |
418 | | |
419 | | /// Internal type MInst: defined at src/isa/x64/inst.isle line 8. |
420 | 4.48M | #[derive(Clone)] |
421 | | pub enum MInst { |
422 | | Nop { |
423 | | len: u8, |
424 | | }, |
425 | | AluRmiR { |
426 | | size: OperandSize, |
427 | | op: AluRmiROpcode, |
428 | | src1: Gpr, |
429 | | src2: GprMemImm, |
430 | | dst: WritableGpr, |
431 | | }, |
432 | | AluRM { |
433 | | size: OperandSize, |
434 | | op: AluRmiROpcode, |
435 | | src1_dst: SyntheticAmode, |
436 | | src2: Gpr, |
437 | | }, |
438 | | AluRmRVex { |
439 | | size: OperandSize, |
440 | | op: AluRmROpcode, |
441 | | src1: Gpr, |
442 | | src2: Gpr, |
443 | | dst: WritableGpr, |
444 | | }, |
445 | | AluConstOp { |
446 | | op: AluRmiROpcode, |
447 | | size: OperandSize, |
448 | | dst: WritableGpr, |
449 | | }, |
450 | | UnaryRmR { |
451 | | size: OperandSize, |
452 | | op: UnaryRmROpcode, |
453 | | src: GprMem, |
454 | | dst: WritableGpr, |
455 | | }, |
456 | | Not { |
457 | | size: OperandSize, |
458 | | src: Gpr, |
459 | | dst: WritableGpr, |
460 | | }, |
461 | | Neg { |
462 | | size: OperandSize, |
463 | | src: Gpr, |
464 | | dst: WritableGpr, |
465 | | }, |
466 | | Div { |
467 | | size: OperandSize, |
468 | | sign: DivSignedness, |
469 | | trap: TrapCode, |
470 | | divisor: GprMem, |
471 | | dividend_lo: Gpr, |
472 | | dividend_hi: Gpr, |
473 | | dst_quotient: WritableGpr, |
474 | | dst_remainder: WritableGpr, |
475 | | }, |
476 | | Div8 { |
477 | | sign: DivSignedness, |
478 | | trap: TrapCode, |
479 | | divisor: GprMem, |
480 | | dividend: Gpr, |
481 | | dst: WritableGpr, |
482 | | }, |
483 | | MulHi { |
484 | | size: OperandSize, |
485 | | signed: bool, |
486 | | src1: Gpr, |
487 | | src2: GprMem, |
488 | | dst_lo: WritableGpr, |
489 | | dst_hi: WritableGpr, |
490 | | }, |
491 | | CheckedSRemSeq { |
492 | | size: OperandSize, |
493 | | dividend_lo: Gpr, |
494 | | dividend_hi: Gpr, |
495 | | divisor: Gpr, |
496 | | dst_quotient: WritableGpr, |
497 | | dst_remainder: WritableGpr, |
498 | | }, |
499 | | CheckedSRemSeq8 { |
500 | | dividend: Gpr, |
501 | | divisor: Gpr, |
502 | | dst: WritableGpr, |
503 | | }, |
504 | | SignExtendData { |
505 | | size: OperandSize, |
506 | | src: Gpr, |
507 | | dst: WritableGpr, |
508 | | }, |
509 | | Imm { |
510 | | dst_size: OperandSize, |
511 | | simm64: u64, |
512 | | dst: WritableGpr, |
513 | | }, |
514 | | MovRR { |
515 | | size: OperandSize, |
516 | | src: Gpr, |
517 | | dst: WritableGpr, |
518 | | }, |
519 | | MovFromPReg { |
520 | | src: PReg, |
521 | | dst: WritableGpr, |
522 | | }, |
523 | | MovToPReg { |
524 | | src: Gpr, |
525 | | dst: PReg, |
526 | | }, |
527 | | MovzxRmR { |
528 | | ext_mode: ExtMode, |
529 | | src: GprMem, |
530 | | dst: WritableGpr, |
531 | | }, |
532 | | Mov64MR { |
533 | | src: SyntheticAmode, |
534 | | dst: WritableGpr, |
535 | | }, |
536 | | LoadEffectiveAddress { |
537 | | addr: SyntheticAmode, |
538 | | dst: WritableGpr, |
539 | | size: OperandSize, |
540 | | }, |
541 | | MovsxRmR { |
542 | | ext_mode: ExtMode, |
543 | | src: GprMem, |
544 | | dst: WritableGpr, |
545 | | }, |
546 | | MovImmM { |
547 | | size: OperandSize, |
548 | | simm64: u64, |
549 | | dst: SyntheticAmode, |
550 | | }, |
551 | | MovRM { |
552 | | size: OperandSize, |
553 | | src: Gpr, |
554 | | dst: SyntheticAmode, |
555 | | }, |
556 | | ShiftR { |
557 | | size: OperandSize, |
558 | | kind: ShiftKind, |
559 | | src: Gpr, |
560 | | num_bits: Imm8Gpr, |
561 | | dst: WritableGpr, |
562 | | }, |
563 | | XmmRmiReg { |
564 | | opcode: SseOpcode, |
565 | | src1: Xmm, |
566 | | src2: XmmMemAlignedImm, |
567 | | dst: WritableXmm, |
568 | | }, |
569 | | CmpRmiR { |
570 | | size: OperandSize, |
571 | | opcode: CmpOpcode, |
572 | | src: GprMemImm, |
573 | | dst: Gpr, |
574 | | }, |
575 | | Setcc { |
576 | | cc: CC, |
577 | | dst: WritableGpr, |
578 | | }, |
579 | | Bswap { |
580 | | size: OperandSize, |
581 | | src: Gpr, |
582 | | dst: WritableGpr, |
583 | | }, |
584 | | Cmove { |
585 | | size: OperandSize, |
586 | | cc: CC, |
587 | | consequent: GprMem, |
588 | | alternative: Gpr, |
589 | | dst: WritableGpr, |
590 | | }, |
591 | | XmmCmove { |
592 | | ty: Type, |
593 | | cc: CC, |
594 | | consequent: XmmMemAligned, |
595 | | alternative: Xmm, |
596 | | dst: WritableXmm, |
597 | | }, |
598 | | Push64 { |
599 | | src: GprMemImm, |
600 | | }, |
601 | | Pop64 { |
602 | | dst: WritableGpr, |
603 | | }, |
604 | | StackProbeLoop { |
605 | | tmp: WritableReg, |
606 | | frame_size: u32, |
607 | | guard_size: u32, |
608 | | }, |
609 | | XmmRmR { |
610 | | op: SseOpcode, |
611 | | src1: Xmm, |
612 | | src2: XmmMemAligned, |
613 | | dst: WritableXmm, |
614 | | }, |
615 | | XmmRmRUnaligned { |
616 | | op: SseOpcode, |
617 | | src1: Xmm, |
618 | | src2: XmmMem, |
619 | | dst: WritableXmm, |
620 | | }, |
621 | | XmmRmRBlend { |
622 | | op: SseOpcode, |
623 | | src1: Xmm, |
624 | | src2: XmmMemAligned, |
625 | | mask: Xmm, |
626 | | dst: WritableXmm, |
627 | | }, |
628 | | XmmRmiRVex { |
629 | | op: AvxOpcode, |
630 | | src1: Xmm, |
631 | | src2: XmmMemImm, |
632 | | dst: WritableXmm, |
633 | | }, |
634 | | XmmRmRImmVex { |
635 | | op: AvxOpcode, |
636 | | src1: Xmm, |
637 | | src2: XmmMem, |
638 | | dst: WritableXmm, |
639 | | imm: u8, |
640 | | }, |
641 | | XmmVexPinsr { |
642 | | op: AvxOpcode, |
643 | | src1: Xmm, |
644 | | src2: GprMem, |
645 | | dst: WritableXmm, |
646 | | imm: u8, |
647 | | }, |
648 | | XmmRmRVex3 { |
649 | | op: AvxOpcode, |
650 | | src1: Xmm, |
651 | | src2: Xmm, |
652 | | src3: XmmMem, |
653 | | dst: WritableXmm, |
654 | | }, |
655 | | XmmRmRBlendVex { |
656 | | op: AvxOpcode, |
657 | | src1: Xmm, |
658 | | src2: XmmMem, |
659 | | mask: Xmm, |
660 | | dst: WritableXmm, |
661 | | }, |
662 | | XmmUnaryRmRVex { |
663 | | op: AvxOpcode, |
664 | | src: XmmMem, |
665 | | dst: WritableXmm, |
666 | | }, |
667 | | XmmUnaryRmRImmVex { |
668 | | op: AvxOpcode, |
669 | | src: XmmMem, |
670 | | dst: WritableXmm, |
671 | | imm: u8, |
672 | | }, |
673 | | XmmMovRMVex { |
674 | | op: AvxOpcode, |
675 | | src: Xmm, |
676 | | dst: SyntheticAmode, |
677 | | }, |
678 | | XmmMovRMImmVex { |
679 | | op: AvxOpcode, |
680 | | src: Xmm, |
681 | | dst: SyntheticAmode, |
682 | | imm: u8, |
683 | | }, |
684 | | XmmToGprImmVex { |
685 | | op: AvxOpcode, |
686 | | src: Xmm, |
687 | | dst: WritableGpr, |
688 | | imm: u8, |
689 | | }, |
690 | | GprToXmmVex { |
691 | | op: AvxOpcode, |
692 | | src: GprMem, |
693 | | dst: WritableXmm, |
694 | | src_size: OperandSize, |
695 | | }, |
696 | | XmmToGprVex { |
697 | | op: AvxOpcode, |
698 | | src: Xmm, |
699 | | dst: WritableGpr, |
700 | | dst_size: OperandSize, |
701 | | }, |
702 | | XmmRmREvex { |
703 | | op: Avx512Opcode, |
704 | | src1: XmmMem, |
705 | | src2: Xmm, |
706 | | dst: WritableXmm, |
707 | | }, |
708 | | XmmRmREvex3 { |
709 | | op: Avx512Opcode, |
710 | | src1: XmmMem, |
711 | | src2: Xmm, |
712 | | src3: Xmm, |
713 | | dst: WritableXmm, |
714 | | }, |
715 | | XmmUnaryRmR { |
716 | | op: SseOpcode, |
717 | | src: XmmMemAligned, |
718 | | dst: WritableXmm, |
719 | | }, |
720 | | XmmUnaryRmRUnaligned { |
721 | | op: SseOpcode, |
722 | | src: XmmMem, |
723 | | dst: WritableXmm, |
724 | | }, |
725 | | XmmUnaryRmRImm { |
726 | | op: SseOpcode, |
727 | | src: XmmMemAligned, |
728 | | imm: u8, |
729 | | dst: WritableXmm, |
730 | | }, |
731 | | XmmUnaryRmREvex { |
732 | | op: Avx512Opcode, |
733 | | src: XmmMem, |
734 | | dst: WritableXmm, |
735 | | }, |
736 | | XmmMovRM { |
737 | | op: SseOpcode, |
738 | | src: Xmm, |
739 | | dst: SyntheticAmode, |
740 | | }, |
741 | | XmmMovRMImm { |
742 | | op: SseOpcode, |
743 | | src: Xmm, |
744 | | dst: SyntheticAmode, |
745 | | imm: u8, |
746 | | }, |
747 | | XmmToGpr { |
748 | | op: SseOpcode, |
749 | | src: Xmm, |
750 | | dst: WritableGpr, |
751 | | dst_size: OperandSize, |
752 | | }, |
753 | | XmmToGprImm { |
754 | | op: SseOpcode, |
755 | | src: Xmm, |
756 | | dst: WritableGpr, |
757 | | imm: u8, |
758 | | }, |
759 | | GprToXmm { |
760 | | op: SseOpcode, |
761 | | src: GprMem, |
762 | | dst: WritableXmm, |
763 | | src_size: OperandSize, |
764 | | }, |
765 | | CvtUint64ToFloatSeq { |
766 | | dst_size: OperandSize, |
767 | | src: Gpr, |
768 | | dst: WritableXmm, |
769 | | tmp_gpr1: WritableGpr, |
770 | | tmp_gpr2: WritableGpr, |
771 | | }, |
772 | | CvtFloatToSintSeq { |
773 | | dst_size: OperandSize, |
774 | | src_size: OperandSize, |
775 | | is_saturating: bool, |
776 | | src: Xmm, |
777 | | dst: WritableGpr, |
778 | | tmp_gpr: WritableGpr, |
779 | | tmp_xmm: WritableXmm, |
780 | | }, |
781 | | CvtFloatToUintSeq { |
782 | | dst_size: OperandSize, |
783 | | src_size: OperandSize, |
784 | | is_saturating: bool, |
785 | | src: Xmm, |
786 | | dst: WritableGpr, |
787 | | tmp_gpr: WritableGpr, |
788 | | tmp_xmm: WritableXmm, |
789 | | tmp_xmm2: WritableXmm, |
790 | | }, |
791 | | XmmMinMaxSeq { |
792 | | size: OperandSize, |
793 | | is_min: bool, |
794 | | lhs: Xmm, |
795 | | rhs: Xmm, |
796 | | dst: WritableXmm, |
797 | | }, |
798 | | XmmCmpRmR { |
799 | | op: SseOpcode, |
800 | | src: XmmMemAligned, |
801 | | dst: Xmm, |
802 | | }, |
803 | | XmmRmRImm { |
804 | | op: SseOpcode, |
805 | | src1: Reg, |
806 | | src2: RegMem, |
807 | | dst: WritableReg, |
808 | | imm: u8, |
809 | | size: OperandSize, |
810 | | }, |
811 | | CallKnown { |
812 | | dest: ExternalName, |
813 | | info: BoxCallInfo, |
814 | | }, |
815 | | CallUnknown { |
816 | | dest: RegMem, |
817 | | info: BoxCallInfo, |
818 | | }, |
819 | | Args { |
820 | | args: VecArgPair, |
821 | | }, |
822 | | Ret { |
823 | | rets: VecRetPair, |
824 | | }, |
825 | | JmpKnown { |
826 | | dst: MachLabel, |
827 | | }, |
828 | | JmpIf { |
829 | | cc: CC, |
830 | | taken: MachLabel, |
831 | | }, |
832 | | JmpCond { |
833 | | cc: CC, |
834 | | taken: MachLabel, |
835 | | not_taken: MachLabel, |
836 | | }, |
837 | | JmpTableSeq { |
838 | | idx: Reg, |
839 | | tmp1: WritableReg, |
840 | | tmp2: WritableReg, |
841 | | default_target: MachLabel, |
842 | | targets: BoxVecMachLabel, |
843 | | }, |
844 | | JmpUnknown { |
845 | | target: RegMem, |
846 | | }, |
847 | | TrapIf { |
848 | | cc: CC, |
849 | | trap_code: TrapCode, |
850 | | }, |
851 | | TrapIfAnd { |
852 | | cc1: CC, |
853 | | cc2: CC, |
854 | | trap_code: TrapCode, |
855 | | }, |
856 | | TrapIfOr { |
857 | | cc1: CC, |
858 | | cc2: CC, |
859 | | trap_code: TrapCode, |
860 | | }, |
861 | | Hlt, |
862 | | Ud2 { |
863 | | trap_code: TrapCode, |
864 | | }, |
865 | | LoadExtName { |
866 | | dst: WritableReg, |
867 | | name: BoxExternalName, |
868 | | offset: i64, |
869 | | }, |
870 | | LockCmpxchg { |
871 | | ty: Type, |
872 | | replacement: Reg, |
873 | | expected: Reg, |
874 | | mem: SyntheticAmode, |
875 | | dst_old: WritableReg, |
876 | | }, |
877 | | AtomicRmwSeq { |
878 | | ty: Type, |
879 | | op: MachAtomicRmwOp, |
880 | | mem: SyntheticAmode, |
881 | | operand: Reg, |
882 | | temp: WritableReg, |
883 | | dst_old: WritableReg, |
884 | | }, |
885 | | Fence { |
886 | | kind: FenceKind, |
887 | | }, |
888 | | VirtualSPOffsetAdj { |
889 | | offset: i64, |
890 | | }, |
891 | | XmmUninitializedValue { |
892 | | dst: WritableXmm, |
893 | | }, |
894 | | ElfTlsGetAddr { |
895 | | symbol: ExternalName, |
896 | | dst: WritableGpr, |
897 | | }, |
898 | | MachOTlsGetAddr { |
899 | | symbol: ExternalName, |
900 | | dst: WritableGpr, |
901 | | }, |
902 | | CoffTlsGetAddr { |
903 | | symbol: ExternalName, |
904 | | dst: WritableGpr, |
905 | | tmp: WritableGpr, |
906 | | }, |
907 | | Unwind { |
908 | | inst: UnwindInst, |
909 | | }, |
910 | | DummyUse { |
911 | | reg: Reg, |
912 | | }, |
913 | | } |
914 | | |
915 | | /// Internal type DivSignedness: defined at src/isa/x64/inst.isle line 663. |
916 | 2.88k | #[derive(Copy, Clone, PartialEq0 , Eq, D0 ebug0 )] |
917 | | pub enum DivSignedness { |
918 | | Signed, |
919 | | Unsigned, |
920 | | } |
921 | | |
922 | | /// Internal type Amode: defined at src/isa/x64/inst.isle line 971. |
923 | 9.36M | #[derive(Clone, D0 ebug0 )] |
924 | | pub enum Amode { |
925 | | ImmReg { |
926 | | simm32: u32, |
927 | | base: Reg, |
928 | | flags: MemFlags, |
929 | | }, |
930 | | ImmRegRegShift { |
931 | | simm32: u32, |
932 | | base: Gpr, |
933 | | index: Gpr, |
934 | | shift: u8, |
935 | | flags: MemFlags, |
936 | | }, |
937 | | RipRelative { |
938 | | target: MachLabel, |
939 | | }, |
940 | | } |
941 | | |
942 | | /// Internal type AvxOpcode: defined at src/isa/x64/inst.isle line 1120. |
943 | 0 | #[derive(Copy, Clone, PartialEq, Eq, Debug)] |
944 | | pub enum AvxOpcode { |
945 | | Vfmadd213ss, |
946 | | Vfmadd213sd, |
947 | | Vfmadd213ps, |
948 | | Vfmadd213pd, |
949 | | Vfmadd132ss, |
950 | | Vfmadd132sd, |
951 | | Vfmadd132ps, |
952 | | Vfmadd132pd, |
953 | | Vfnmadd213ss, |
954 | | Vfnmadd213sd, |
955 | | Vfnmadd213ps, |
956 | | Vfnmadd213pd, |
957 | | Vfnmadd132ss, |
958 | | Vfnmadd132sd, |
959 | | Vfnmadd132ps, |
960 | | Vfnmadd132pd, |
961 | | Vcmpps, |
962 | | Vcmppd, |
963 | | Vpsrlw, |
964 | | Vpsrld, |
965 | | Vpsrlq, |
966 | | Vpaddb, |
967 | | Vpaddw, |
968 | | Vpaddd, |
969 | | Vpaddq, |
970 | | Vpaddsb, |
971 | | Vpaddsw, |
972 | | Vpaddusb, |
973 | | Vpaddusw, |
974 | | Vpsubb, |
975 | | Vpsubw, |
976 | | Vpsubd, |
977 | | Vpsubq, |
978 | | Vpsubsb, |
979 | | Vpsubsw, |
980 | | Vpsubusb, |
981 | | Vpsubusw, |
982 | | Vpavgb, |
983 | | Vpavgw, |
984 | | Vpand, |
985 | | Vandps, |
986 | | Vandpd, |
987 | | Vpor, |
988 | | Vorps, |
989 | | Vorpd, |
990 | | Vpxor, |
991 | | Vxorps, |
992 | | Vxorpd, |
993 | | Vpmullw, |
994 | | Vpmulld, |
995 | | Vpmulhw, |
996 | | Vpmulhd, |
997 | | Vpmulhrsw, |
998 | | Vpmulhuw, |
999 | | Vpmuldq, |
1000 | | Vpmuludq, |
1001 | | Vpunpckhwd, |
1002 | | Vpunpcklwd, |
1003 | | Vunpcklps, |
1004 | | Vandnps, |
1005 | | Vandnpd, |
1006 | | Vpandn, |
1007 | | Vaddps, |
1008 | | Vaddpd, |
1009 | | Vsubps, |
1010 | | Vsubpd, |
1011 | | Vmulps, |
1012 | | Vmulpd, |
1013 | | Vdivps, |
1014 | | Vdivpd, |
1015 | | Vpcmpeqb, |
1016 | | Vpcmpeqw, |
1017 | | Vpcmpeqd, |
1018 | | Vpcmpeqq, |
1019 | | Vpcmpgtb, |
1020 | | Vpcmpgtw, |
1021 | | Vpcmpgtd, |
1022 | | Vpcmpgtq, |
1023 | | Vminps, |
1024 | | Vminpd, |
1025 | | Vmaxps, |
1026 | | Vmaxpd, |
1027 | | Vblendvpd, |
1028 | | Vblendvps, |
1029 | | Vpblendvb, |
1030 | | Vmovlhps, |
1031 | | Vpmaxsb, |
1032 | | Vpmaxsw, |
1033 | | Vpmaxsd, |
1034 | | Vpminsb, |
1035 | | Vpminsw, |
1036 | | Vpminsd, |
1037 | | Vpmaxub, |
1038 | | Vpmaxuw, |
1039 | | Vpmaxud, |
1040 | | Vpminub, |
1041 | | Vpminuw, |
1042 | | Vpminud, |
1043 | | Vpunpcklbw, |
1044 | | Vpunpckhbw, |
1045 | | Vpacksswb, |
1046 | | Vpackssdw, |
1047 | | Vpackuswb, |
1048 | | Vpackusdw, |
1049 | | Vpalignr, |
1050 | | Vpinsrb, |
1051 | | Vpinsrw, |
1052 | | Vpinsrd, |
1053 | | Vpinsrq, |
1054 | | Vpmaddwd, |
1055 | | Vpmaddubsw, |
1056 | | Vinsertps, |
1057 | | Vpshufb, |
1058 | | Vshufps, |
1059 | | Vpsllw, |
1060 | | Vpslld, |
1061 | | Vpsllq, |
1062 | | Vpsraw, |
1063 | | Vpsrad, |
1064 | | Vpmovsxbw, |
1065 | | Vpmovzxbw, |
1066 | | Vpmovsxwd, |
1067 | | Vpmovzxwd, |
1068 | | Vpmovsxdq, |
1069 | | Vpmovzxdq, |
1070 | | Vaddss, |
1071 | | Vaddsd, |
1072 | | Vmulss, |
1073 | | Vmulsd, |
1074 | | Vsubss, |
1075 | | Vsubsd, |
1076 | | Vdivss, |
1077 | | Vdivsd, |
1078 | | Vpabsb, |
1079 | | Vpabsw, |
1080 | | Vpabsd, |
1081 | | Vminss, |
1082 | | Vminsd, |
1083 | | Vmaxss, |
1084 | | Vmaxsd, |
1085 | | Vsqrtps, |
1086 | | Vsqrtpd, |
1087 | | Vroundps, |
1088 | | Vroundpd, |
1089 | | Vcvtdq2pd, |
1090 | | Vcvtdq2ps, |
1091 | | Vcvtpd2ps, |
1092 | | Vcvtps2pd, |
1093 | | Vcvttpd2dq, |
1094 | | Vcvttps2dq, |
1095 | | Vphaddw, |
1096 | | Vphaddd, |
1097 | | Vpunpckhdq, |
1098 | | Vpunpckldq, |
1099 | | Vpunpckhqdq, |
1100 | | Vpunpcklqdq, |
1101 | | Vpshuflw, |
1102 | | Vpshufhw, |
1103 | | Vpshufd, |
1104 | | Vmovss, |
1105 | | Vmovsd, |
1106 | | Vmovups, |
1107 | | Vmovupd, |
1108 | | Vmovdqu, |
1109 | | Vpextrb, |
1110 | | Vpextrw, |
1111 | | Vpextrd, |
1112 | | Vpextrq, |
1113 | | Vpblendw, |
1114 | | Vmovddup, |
1115 | | Vpbroadcastb, |
1116 | | Vpbroadcastw, |
1117 | | Vpbroadcastd, |
1118 | | Vbroadcastss, |
1119 | | Vmovd, |
1120 | | Vmovq, |
1121 | | Vmovmskps, |
1122 | | Vmovmskpd, |
1123 | | Vpmovmskb, |
1124 | | Vcvtsi2ss, |
1125 | | Vcvtsi2sd, |
1126 | | Vcvtss2sd, |
1127 | | Vcvtsd2ss, |
1128 | | Vsqrtss, |
1129 | | Vsqrtsd, |
1130 | | Vroundss, |
1131 | | Vroundsd, |
1132 | | } |
1133 | | |
1134 | | /// Internal type RegisterClass: defined at src/isa/x64/inst.isle line 1585. |
1135 | 0 | #[derive(Clone, Debug)] |
1136 | | pub enum RegisterClass { |
1137 | | Gpr { |
1138 | | single_register: bool, |
1139 | | }, |
1140 | | Xmm, |
1141 | | } |
1142 | | |
1143 | | /// Internal type ExtendKind: defined at src/isa/x64/inst.isle line 1726. |
1144 | 0 | #[derive(Copy, Clone, PartialEq, Eq, Debug)] |
1145 | | pub enum ExtendKind { |
1146 | | Sign, |
1147 | | Zero, |
1148 | | } |
1149 | | |
1150 | | /// Internal type IcmpCondResult: defined at src/isa/x64/inst.isle line 4359. |
1151 | 196k | #[derive(Clone, Debug0 )] |
1152 | | pub enum IcmpCondResult { |
1153 | | Condition { |
1154 | | producer: ProducesFlags, |
1155 | | cc: CC, |
1156 | | }, |
1157 | | } |
1158 | | |
1159 | | /// Internal type FcmpCondResult: defined at src/isa/x64/inst.isle line 4472. |
1160 | 0 | #[derive(Clone, Debug)] |
1161 | | pub enum FcmpCondResult { |
1162 | | Condition { |
1163 | | producer: ProducesFlags, |
1164 | | cc: CC, |
1165 | | }, |
1166 | | AndCondition { |
1167 | | producer: ProducesFlags, |
1168 | | cc1: CC, |
1169 | | cc2: CC, |
1170 | | }, |
1171 | | OrCondition { |
1172 | | producer: ProducesFlags, |
1173 | | cc1: CC, |
1174 | | cc2: CC, |
1175 | | }, |
1176 | | } |
1177 | | |
1178 | | // Generated as internal constructor for term output_reg. |
1179 | 2.00M | pub fn constructor_output_reg<C: Context>( |
1180 | 2.00M | ctx: &mut C, |
1181 | 2.00M | arg0: Reg, |
1182 | 2.00M | ) -> InstOutput { |
1183 | 2.00M | let v1 = C::value_reg(ctx, arg0); |
1184 | 2.00M | let v2 = C::output(ctx, v1); |
1185 | 2.00M | // Rule at src/prelude_lower.isle line 55. |
1186 | 2.00M | return v2; |
1187 | 2.00M | } |
1188 | | |
1189 | | // Generated as internal constructor for term output_value. |
1190 | 0 | pub fn constructor_output_value<C: Context>( |
1191 | 0 | ctx: &mut C, |
1192 | 0 | arg0: Value, |
1193 | 0 | ) -> InstOutput { |
1194 | 0 | let v1 = C::put_in_regs(ctx, arg0); |
1195 | 0 | let v2 = C::output(ctx, v1); |
1196 | 0 | // Rule at src/prelude_lower.isle line 59. |
1197 | 0 | return v2; |
1198 | 0 | } |
1199 | | |
1200 | | // Generated as internal constructor for term temp_reg. |
1201 | 0 | pub fn constructor_temp_reg<C: Context>( |
1202 | 0 | ctx: &mut C, |
1203 | 0 | arg0: Type, |
1204 | 0 | ) -> Reg { |
1205 | 0 | let v1 = C::temp_writable_reg(ctx, arg0); |
1206 | 0 | let v2 = C::writable_reg_to_reg(ctx, v1); |
1207 | 0 | // Rule at src/prelude_lower.isle line 79. |
1208 | 0 | return v2; |
1209 | 0 | } |
1210 | | |
1211 | | // Generated as internal constructor for term value_regs_range. |
1212 | 0 | pub fn constructor_value_regs_range<C: Context>( |
1213 | 0 | ctx: &mut C, |
1214 | 0 | arg0: ValueRegs, |
1215 | 0 | ) -> Range { |
1216 | 0 | let v2 = C::value_regs_len(ctx, arg0); |
1217 | 0 | let v3 = C::range(ctx, 0x0, v2); |
1218 | 0 | // Rule at src/prelude_lower.isle line 128. |
1219 | 0 | return v3; |
1220 | 0 | } |
1221 | | |
1222 | | // Generated as internal constructor for term lo_reg. |
1223 | 0 | pub fn constructor_lo_reg<C: Context>( |
1224 | 0 | ctx: &mut C, |
1225 | 0 | arg0: Value, |
1226 | 0 | ) -> Reg { |
1227 | 0 | let v1 = C::put_in_regs(ctx, arg0); |
1228 | 0 | let v3 = C::value_regs_get(ctx, v1, 0x0); |
1229 | 0 | // Rule at src/prelude_lower.isle line 139. |
1230 | 0 | return v3; |
1231 | 0 | } |
1232 | | |
1233 | | // Generated as internal constructor for term emit_side_effect. |
1234 | 848k | pub fn constructor_emit_side_effect<C: Context>( |
1235 | 848k | ctx: &mut C, |
1236 | 848k | arg0: &SideEffectNoResult, |
1237 | 848k | ) -> Unit { |
1238 | 848k | match arg0 { |
1239 | | &SideEffectNoResult::Inst { |
1240 | 615k | inst: ref v1, |
1241 | 615k | } => { |
1242 | 615k | let v2 = C::emit(ctx, v1); |
1243 | 615k | // Rule at src/prelude_lower.isle line 292. |
1244 | 615k | return v2; |
1245 | | } |
1246 | | &SideEffectNoResult::Inst2 { |
1247 | 233k | inst1: ref v3, |
1248 | 233k | inst2: ref v4, |
1249 | 233k | } => { |
1250 | 233k | let v5 = C::emit(ctx, v3); |
1251 | 233k | let v6 = C::emit(ctx, v4); |
1252 | 233k | // Rule at src/prelude_lower.isle line 294. |
1253 | 233k | return v6; |
1254 | | } |
1255 | | &SideEffectNoResult::Inst3 { |
1256 | 0 | inst1: ref v7, |
1257 | 0 | inst2: ref v8, |
1258 | 0 | inst3: ref v9, |
1259 | 0 | } => { |
1260 | 0 | let v10 = C::emit(ctx, v7); |
1261 | 0 | let v11 = C::emit(ctx, v8); |
1262 | 0 | let v12 = C::emit(ctx, v9); |
1263 | 0 | // Rule at src/prelude_lower.isle line 297. |
1264 | 0 | return v12; |
1265 | | } |
1266 | 0 | _ => {} |
1267 | 0 | } |
1268 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "emit_side_effect", "src/prelude_lower.isle line 291") |
1269 | 848k | } |
1270 | | |
1271 | | // Generated as internal constructor for term side_effect. |
1272 | 451k | pub fn constructor_side_effect<C: Context>( |
1273 | 451k | ctx: &mut C, |
1274 | 451k | arg0: &SideEffectNoResult, |
1275 | 451k | ) -> InstOutput { |
1276 | 451k | let v1 = constructor_emit_side_effect(ctx, arg0); |
1277 | 451k | let v2 = C::output_none(ctx); |
1278 | 451k | // Rule at src/prelude_lower.isle line 305. |
1279 | 451k | return v2; |
1280 | 451k | } |
1281 | | |
1282 | | // Generated as internal constructor for term side_effect_concat. |
1283 | 0 | pub fn constructor_side_effect_concat<C: Context>( |
1284 | 0 | ctx: &mut C, |
1285 | 0 | arg0: &SideEffectNoResult, |
1286 | 0 | arg1: &SideEffectNoResult, |
1287 | 0 | ) -> SideEffectNoResult { |
1288 | 0 | match arg0 { |
1289 | | &SideEffectNoResult::Inst { |
1290 | 0 | inst: ref v1, |
1291 | 0 | } => { |
1292 | 0 | match arg1 { |
1293 | | &SideEffectNoResult::Inst { |
1294 | 0 | inst: ref v3, |
1295 | 0 | } => { |
1296 | 0 | let v4 = SideEffectNoResult::Inst2 { |
1297 | 0 | inst1: v1.clone(), |
1298 | 0 | inst2: v3.clone(), |
1299 | 0 | }; |
1300 | 0 | // Rule at src/prelude_lower.isle line 310. |
1301 | 0 | return v4; |
1302 | | } |
1303 | | &SideEffectNoResult::Inst2 { |
1304 | 0 | inst1: ref v5, |
1305 | 0 | inst2: ref v6, |
1306 | 0 | } => { |
1307 | 0 | let v7 = SideEffectNoResult::Inst3 { |
1308 | 0 | inst1: v1.clone(), |
1309 | 0 | inst2: v5.clone(), |
1310 | 0 | inst3: v6.clone(), |
1311 | 0 | }; |
1312 | 0 | // Rule at src/prelude_lower.isle line 312. |
1313 | 0 | return v7; |
1314 | | } |
1315 | 0 | _ => {} |
1316 | | } |
1317 | | } |
1318 | | &SideEffectNoResult::Inst2 { |
1319 | 0 | inst1: ref v8, |
1320 | 0 | inst2: ref v9, |
1321 | | } => { |
1322 | | if let &SideEffectNoResult::Inst { |
1323 | 0 | inst: ref v3, |
1324 | 0 | } = arg1 { |
1325 | 0 | let v10 = SideEffectNoResult::Inst3 { |
1326 | 0 | inst1: v8.clone(), |
1327 | 0 | inst2: v9.clone(), |
1328 | 0 | inst3: v3.clone(), |
1329 | 0 | }; |
1330 | 0 | // Rule at src/prelude_lower.isle line 314. |
1331 | 0 | return v10; |
1332 | 0 | } |
1333 | | } |
1334 | 0 | _ => {} |
1335 | | } |
1336 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "side_effect_concat", "src/prelude_lower.isle line 309") |
1337 | 0 | } |
1338 | | |
1339 | | // Generated as internal constructor for term produces_flags_append. |
1340 | 0 | pub fn constructor_produces_flags_append<C: Context>( |
1341 | 0 | ctx: &mut C, |
1342 | 0 | arg0: &ProducesFlags, |
1343 | 0 | arg1: &MInst, |
1344 | 0 | ) -> ProducesFlags { |
1345 | | if let &ProducesFlags::ProducesFlagsSideEffect { |
1346 | 0 | inst: ref v1, |
1347 | 0 | } = arg0 { |
1348 | 0 | let v3 = ProducesFlags::ProducesFlagsTwiceSideEffect { |
1349 | 0 | inst1: v1.clone(), |
1350 | 0 | inst2: arg1.clone(), |
1351 | 0 | }; |
1352 | 0 | // Rule at src/prelude_lower.isle line 339. |
1353 | 0 | return v3; |
1354 | 0 | } |
1355 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "produces_flags_append", "src/prelude_lower.isle line 338") |
1356 | 0 | } |
1357 | | |
1358 | | // Generated as internal constructor for term produces_flags_get_reg. |
1359 | 0 | pub fn constructor_produces_flags_get_reg<C: Context>( |
1360 | 0 | ctx: &mut C, |
1361 | 0 | arg0: &ProducesFlags, |
1362 | 0 | ) -> Reg { |
1363 | 0 | match arg0 { |
1364 | | &ProducesFlags::ProducesFlagsReturnsReg { |
1365 | 0 | inst: ref v1, |
1366 | 0 | result: v2, |
1367 | 0 | } => { |
1368 | 0 | // Rule at src/prelude_lower.isle line 364. |
1369 | 0 | return v2; |
1370 | | } |
1371 | | &ProducesFlags::ProducesFlagsReturnsResultWithConsumer { |
1372 | 0 | inst: ref v3, |
1373 | 0 | result: v4, |
1374 | 0 | } => { |
1375 | 0 | // Rule at src/prelude_lower.isle line 365. |
1376 | 0 | return v4; |
1377 | | } |
1378 | 0 | _ => {} |
1379 | 0 | } |
1380 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "produces_flags_get_reg", "src/prelude_lower.isle line 363") |
1381 | 0 | } |
1382 | | |
1383 | | // Generated as internal constructor for term produces_flags_ignore. |
1384 | 0 | pub fn constructor_produces_flags_ignore<C: Context>( |
1385 | 0 | ctx: &mut C, |
1386 | 0 | arg0: &ProducesFlags, |
1387 | 0 | ) -> ProducesFlags { |
1388 | 0 | match arg0 { |
1389 | | &ProducesFlags::ProducesFlagsReturnsReg { |
1390 | 0 | inst: ref v1, |
1391 | 0 | result: v2, |
1392 | 0 | } => { |
1393 | 0 | let v3 = ProducesFlags::ProducesFlagsSideEffect { |
1394 | 0 | inst: v1.clone(), |
1395 | 0 | }; |
1396 | 0 | // Rule at src/prelude_lower.isle line 370. |
1397 | 0 | return v3; |
1398 | | } |
1399 | | &ProducesFlags::ProducesFlagsReturnsResultWithConsumer { |
1400 | 0 | inst: ref v4, |
1401 | 0 | result: v5, |
1402 | 0 | } => { |
1403 | 0 | let v6 = ProducesFlags::ProducesFlagsSideEffect { |
1404 | 0 | inst: v4.clone(), |
1405 | 0 | }; |
1406 | 0 | // Rule at src/prelude_lower.isle line 372. |
1407 | 0 | return v6; |
1408 | | } |
1409 | 0 | _ => {} |
1410 | 0 | } |
1411 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "produces_flags_ignore", "src/prelude_lower.isle line 369") |
1412 | 0 | } |
1413 | | |
1414 | | // Generated as internal constructor for term consumes_flags_concat. |
1415 | 0 | pub fn constructor_consumes_flags_concat<C: Context>( |
1416 | 0 | ctx: &mut C, |
1417 | 0 | arg0: &ConsumesFlags, |
1418 | 0 | arg1: &ConsumesFlags, |
1419 | 0 | ) -> ConsumesFlags { |
1420 | 0 | match arg0 { |
1421 | | &ConsumesFlags::ConsumesFlagsSideEffect { |
1422 | 0 | inst: ref v8, |
1423 | | } => { |
1424 | | if let &ConsumesFlags::ConsumesFlagsSideEffect { |
1425 | 0 | inst: ref v9, |
1426 | 0 | } = arg1 { |
1427 | 0 | let v10 = ConsumesFlags::ConsumesFlagsSideEffect2 { |
1428 | 0 | inst1: v8.clone(), |
1429 | 0 | inst2: v9.clone(), |
1430 | 0 | }; |
1431 | 0 | // Rule at src/prelude_lower.isle line 385. |
1432 | 0 | return v10; |
1433 | 0 | } |
1434 | | } |
1435 | | &ConsumesFlags::ConsumesFlagsReturnsReg { |
1436 | 0 | inst: ref v1, |
1437 | 0 | result: v2, |
1438 | | } => { |
1439 | | if let &ConsumesFlags::ConsumesFlagsReturnsReg { |
1440 | 0 | inst: ref v4, |
1441 | 0 | result: v5, |
1442 | 0 | } = arg1 { |
1443 | 0 | let v6 = C::value_regs(ctx, v2, v5); |
1444 | 0 | let v7 = ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs { |
1445 | 0 | inst1: v1.clone(), |
1446 | 0 | inst2: v4.clone(), |
1447 | 0 | result: v6, |
1448 | 0 | }; |
1449 | 0 | // Rule at src/prelude_lower.isle line 379. |
1450 | 0 | return v7; |
1451 | 0 | } |
1452 | | } |
1453 | 0 | _ => {} |
1454 | | } |
1455 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "consumes_flags_concat", "src/prelude_lower.isle line 378") |
1456 | 0 | } |
1457 | | |
1458 | | // Generated as internal constructor for term with_flags. |
1459 | 51.5k | pub fn constructor_with_flags<C: Context>( |
1460 | 51.5k | ctx: &mut C, |
1461 | 51.5k | arg0: &ProducesFlags, |
1462 | 51.5k | arg1: &ConsumesFlags, |
1463 | 51.5k | ) -> ValueRegs { |
1464 | 51.5k | match arg0 { |
1465 | | &ProducesFlags::ProducesFlagsSideEffect { |
1466 | 51.5k | inst: ref v12, |
1467 | 51.5k | } => { |
1468 | 51.5k | match arg1 { |
1469 | | &ConsumesFlags::ConsumesFlagsReturnsReg { |
1470 | 51.5k | inst: ref v13, |
1471 | 51.5k | result: v14, |
1472 | 51.5k | } => { |
1473 | 51.5k | let v15 = C::emit(ctx, v12); |
1474 | 51.5k | let v16 = C::emit(ctx, v13); |
1475 | 51.5k | let v17 = C::value_reg(ctx, v14); |
1476 | 51.5k | // Rule at src/prelude_lower.isle line 416. |
1477 | 51.5k | return v17; |
1478 | | } |
1479 | | &ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs { |
1480 | 0 | inst1: ref v18, |
1481 | 0 | inst2: ref v19, |
1482 | 0 | result: v20, |
1483 | 0 | } => { |
1484 | 0 | let v15 = C::emit(ctx, v12); |
1485 | 0 | let v21 = C::emit(ctx, v18); |
1486 | 0 | let v22 = C::emit(ctx, v19); |
1487 | 0 | // Rule at src/prelude_lower.isle line 422. |
1488 | 0 | return v20; |
1489 | | } |
1490 | | &ConsumesFlags::ConsumesFlagsFourTimesReturnsValueRegs { |
1491 | 0 | inst1: ref v23, |
1492 | 0 | inst2: ref v24, |
1493 | 0 | inst3: ref v25, |
1494 | 0 | inst4: ref v26, |
1495 | 0 | result: v27, |
1496 | 0 | } => { |
1497 | 0 | let v15 = C::emit(ctx, v12); |
1498 | 0 | let v28 = C::emit(ctx, v23); |
1499 | 0 | let v29 = C::emit(ctx, v24); |
1500 | 0 | let v30 = C::emit(ctx, v25); |
1501 | 0 | let v31 = C::emit(ctx, v26); |
1502 | 0 | // Rule at src/prelude_lower.isle line 434. |
1503 | 0 | return v27; |
1504 | | } |
1505 | 0 | _ => {} |
1506 | | } |
1507 | | } |
1508 | | &ProducesFlags::ProducesFlagsTwiceSideEffect { |
1509 | 0 | inst1: ref v32, |
1510 | 0 | inst2: ref v33, |
1511 | 0 | } => { |
1512 | 0 | match arg1 { |
1513 | | &ConsumesFlags::ConsumesFlagsReturnsReg { |
1514 | 0 | inst: ref v13, |
1515 | 0 | result: v14, |
1516 | 0 | } => { |
1517 | 0 | let v34 = C::emit(ctx, v32); |
1518 | 0 | let v35 = C::emit(ctx, v33); |
1519 | 0 | let v36 = C::emit(ctx, v13); |
1520 | 0 | let v37 = C::value_reg(ctx, v14); |
1521 | 0 | // Rule at src/prelude_lower.isle line 450. |
1522 | 0 | return v37; |
1523 | | } |
1524 | | &ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs { |
1525 | 0 | inst1: ref v18, |
1526 | 0 | inst2: ref v19, |
1527 | 0 | result: v20, |
1528 | 0 | } => { |
1529 | 0 | let v34 = C::emit(ctx, v32); |
1530 | 0 | let v35 = C::emit(ctx, v33); |
1531 | 0 | let v38 = C::emit(ctx, v18); |
1532 | 0 | let v39 = C::emit(ctx, v19); |
1533 | 0 | // Rule at src/prelude_lower.isle line 457. |
1534 | 0 | return v20; |
1535 | | } |
1536 | | &ConsumesFlags::ConsumesFlagsFourTimesReturnsValueRegs { |
1537 | 0 | inst1: ref v23, |
1538 | 0 | inst2: ref v24, |
1539 | 0 | inst3: ref v25, |
1540 | 0 | inst4: ref v26, |
1541 | 0 | result: v27, |
1542 | 0 | } => { |
1543 | 0 | let v34 = C::emit(ctx, v32); |
1544 | 0 | let v35 = C::emit(ctx, v33); |
1545 | 0 | let v40 = C::emit(ctx, v23); |
1546 | 0 | let v41 = C::emit(ctx, v24); |
1547 | 0 | let v42 = C::emit(ctx, v25); |
1548 | 0 | let v43 = C::emit(ctx, v26); |
1549 | 0 | // Rule at src/prelude_lower.isle line 470. |
1550 | 0 | return v27; |
1551 | | } |
1552 | 0 | _ => {} |
1553 | | } |
1554 | | } |
1555 | | &ProducesFlags::ProducesFlagsReturnsResultWithConsumer { |
1556 | 0 | inst: ref v1, |
1557 | 0 | result: v2, |
1558 | 0 | } => { |
1559 | 0 | match arg1 { |
1560 | | &ConsumesFlags::ConsumesFlagsSideEffect { |
1561 | 0 | inst: ref v9, |
1562 | 0 | } => { |
1563 | 0 | let v6 = C::emit(ctx, v1); |
1564 | 0 | let v10 = C::emit(ctx, v9); |
1565 | 0 | let v11 = C::value_reg(ctx, v2); |
1566 | 0 | // Rule at src/prelude_lower.isle line 410. |
1567 | 0 | return v11; |
1568 | | } |
1569 | | &ConsumesFlags::ConsumesFlagsReturnsResultWithProducer { |
1570 | 0 | inst: ref v4, |
1571 | 0 | result: v5, |
1572 | 0 | } => { |
1573 | 0 | let v6 = C::emit(ctx, v1); |
1574 | 0 | let v7 = C::emit(ctx, v4); |
1575 | 0 | let v8 = C::value_regs(ctx, v2, v5); |
1576 | 0 | // Rule at src/prelude_lower.isle line 402. |
1577 | 0 | return v8; |
1578 | | } |
1579 | 0 | _ => {} |
1580 | | } |
1581 | | } |
1582 | 0 | _ => {} |
1583 | | } |
1584 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "with_flags", "src/prelude_lower.isle line 400") |
1585 | 51.5k | } |
1586 | | |
1587 | | // Generated as internal constructor for term with_flags_reg. |
1588 | 9.09k | pub fn constructor_with_flags_reg<C: Context>( |
1589 | 9.09k | ctx: &mut C, |
1590 | 9.09k | arg0: &ProducesFlags, |
1591 | 9.09k | arg1: &ConsumesFlags, |
1592 | 9.09k | ) -> Reg { |
1593 | 9.09k | let v2 = constructor_with_flags(ctx, arg0, arg1); |
1594 | 9.09k | let v4 = C::value_regs_get(ctx, v2, 0x0); |
1595 | 9.09k | // Rule at src/prelude_lower.isle line 488. |
1596 | 9.09k | return v4; |
1597 | 9.09k | } |
1598 | | |
1599 | | // Generated as internal constructor for term flags_to_producesflags. |
1600 | 0 | pub fn constructor_flags_to_producesflags<C: Context>( |
1601 | 0 | ctx: &mut C, |
1602 | 0 | arg0: Value, |
1603 | 0 | ) -> ProducesFlags { |
1604 | 0 | let v1 = C::mark_value_used(ctx, arg0); |
1605 | 0 | // Rule at src/prelude_lower.isle line 495. |
1606 | 0 | return ProducesFlags::AlreadyExistingFlags; |
1607 | 0 | } |
1608 | | |
1609 | | // Generated as internal constructor for term with_flags_side_effect. |
1610 | 233k | pub fn constructor_with_flags_side_effect<C: Context>( |
1611 | 233k | ctx: &mut C, |
1612 | 233k | arg0: &ProducesFlags, |
1613 | 233k | arg1: &ConsumesFlags, |
1614 | 233k | ) -> SideEffectNoResult { |
1615 | 233k | match arg0 { |
1616 | | &ProducesFlags::AlreadyExistingFlags => { |
1617 | 0 | match arg1 { |
1618 | | &ConsumesFlags::ConsumesFlagsSideEffect { |
1619 | 0 | inst: ref v2, |
1620 | 0 | } => { |
1621 | 0 | let v3 = SideEffectNoResult::Inst { |
1622 | 0 | inst: v2.clone(), |
1623 | 0 | }; |
1624 | 0 | // Rule at src/prelude_lower.isle line 506. |
1625 | 0 | return v3; |
1626 | | } |
1627 | | &ConsumesFlags::ConsumesFlagsSideEffect2 { |
1628 | 0 | inst1: ref v4, |
1629 | 0 | inst2: ref v5, |
1630 | 0 | } => { |
1631 | 0 | let v6 = SideEffectNoResult::Inst2 { |
1632 | 0 | inst1: v4.clone(), |
1633 | 0 | inst2: v5.clone(), |
1634 | 0 | }; |
1635 | 0 | // Rule at src/prelude_lower.isle line 511. |
1636 | 0 | return v6; |
1637 | | } |
1638 | 0 | _ => {} |
1639 | | } |
1640 | | } |
1641 | | &ProducesFlags::ProducesFlagsSideEffect { |
1642 | 233k | inst: ref v7, |
1643 | 233k | } => { |
1644 | 233k | match arg1 { |
1645 | | &ConsumesFlags::ConsumesFlagsSideEffect { |
1646 | 233k | inst: ref v2, |
1647 | 233k | } => { |
1648 | 233k | let v8 = SideEffectNoResult::Inst2 { |
1649 | 233k | inst1: v7.clone(), |
1650 | 233k | inst2: v2.clone(), |
1651 | 233k | }; |
1652 | 233k | // Rule at src/prelude_lower.isle line 516. |
1653 | 233k | return v8; |
1654 | | } |
1655 | | &ConsumesFlags::ConsumesFlagsSideEffect2 { |
1656 | 0 | inst1: ref v4, |
1657 | 0 | inst2: ref v5, |
1658 | 0 | } => { |
1659 | 0 | let v9 = SideEffectNoResult::Inst3 { |
1660 | 0 | inst1: v7.clone(), |
1661 | 0 | inst2: v4.clone(), |
1662 | 0 | inst3: v5.clone(), |
1663 | 0 | }; |
1664 | 0 | // Rule at src/prelude_lower.isle line 521. |
1665 | 0 | return v9; |
1666 | | } |
1667 | 0 | _ => {} |
1668 | | } |
1669 | | } |
1670 | | &ProducesFlags::ProducesFlagsTwiceSideEffect { |
1671 | 0 | inst1: ref v10, |
1672 | 0 | inst2: ref v11, |
1673 | | } => { |
1674 | | if let &ConsumesFlags::ConsumesFlagsSideEffect { |
1675 | 0 | inst: ref v2, |
1676 | 0 | } = arg1 { |
1677 | 0 | let v12 = SideEffectNoResult::Inst3 { |
1678 | 0 | inst1: v10.clone(), |
1679 | 0 | inst2: v11.clone(), |
1680 | 0 | inst3: v2.clone(), |
1681 | 0 | }; |
1682 | 0 | // Rule at src/prelude_lower.isle line 526. |
1683 | 0 | return v12; |
1684 | 0 | } |
1685 | | } |
1686 | 0 | _ => {} |
1687 | | } |
1688 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "with_flags_side_effect", "src/prelude_lower.isle line 504") |
1689 | 233k | } |
1690 | | |
1691 | | // Generated as internal constructor for term lower_return. |
1692 | 14.3k | pub fn constructor_lower_return<C: Context>( |
1693 | 14.3k | ctx: &mut C, |
1694 | 14.3k | arg0: Range, |
1695 | 14.3k | arg1: ValueSlice, |
1696 | 14.3k | ) -> InstOutput { |
1697 | 14.3k | let v2 = C::gen_return(ctx, arg1); |
1698 | 14.3k | let v3 = C::output_none(ctx); |
1699 | 14.3k | // Rule at src/prelude_lower.isle line 715. |
1700 | 14.3k | return v3; |
1701 | 14.3k | } |
1702 | | |
1703 | | // Generated as internal constructor for term operand_size_bits. |
1704 | 97.7k | pub fn constructor_operand_size_bits<C: Context>( |
1705 | 97.7k | ctx: &mut C, |
1706 | 97.7k | arg0: &OperandSize, |
1707 | 97.7k | ) -> u16 { |
1708 | 97.7k | match arg0 { |
1709 | | &OperandSize::Size8 => { |
1710 | | // Rule at src/isa/x64/inst.isle line 704. |
1711 | 0 | return 0x8; |
1712 | | } |
1713 | | &OperandSize::Size16 => { |
1714 | | // Rule at src/isa/x64/inst.isle line 705. |
1715 | 0 | return 0x10; |
1716 | | } |
1717 | | &OperandSize::Size32 => { |
1718 | | // Rule at src/isa/x64/inst.isle line 706. |
1719 | 6.18k | return 0x20; |
1720 | | } |
1721 | | &OperandSize::Size64 => { |
1722 | | // Rule at src/isa/x64/inst.isle line 707. |
1723 | 91.5k | return 0x40; |
1724 | | } |
1725 | 0 | _ => {} |
1726 | 0 | } |
1727 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "operand_size_bits", "src/isa/x64/inst.isle line 703") |
1728 | 97.7k | } |
1729 | | |
1730 | | // Generated as internal constructor for term reg_mem_to_reg_mem_imm. |
1731 | 0 | pub fn constructor_reg_mem_to_reg_mem_imm<C: Context>( |
1732 | 0 | ctx: &mut C, |
1733 | 0 | arg0: &RegMem, |
1734 | 0 | ) -> RegMemImm { |
1735 | 0 | match arg0 { |
1736 | | &RegMem::Reg { |
1737 | 0 | reg: v1, |
1738 | 0 | } => { |
1739 | 0 | let v2 = RegMemImm::Reg { |
1740 | 0 | reg: v1, |
1741 | 0 | }; |
1742 | 0 | // Rule at src/isa/x64/inst.isle line 945. |
1743 | 0 | return v2; |
1744 | | } |
1745 | | &RegMem::Mem { |
1746 | 0 | addr: ref v3, |
1747 | 0 | } => { |
1748 | 0 | let v4 = RegMemImm::Mem { |
1749 | 0 | addr: v3.clone(), |
1750 | 0 | }; |
1751 | 0 | // Rule at src/isa/x64/inst.isle line 947. |
1752 | 0 | return v4; |
1753 | | } |
1754 | 0 | _ => {} |
1755 | 0 | } |
1756 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "reg_mem_to_reg_mem_imm", "src/isa/x64/inst.isle line 944") |
1757 | 0 | } |
1758 | | |
1759 | | // Generated as internal constructor for term to_amode. |
1760 | 1.56M | pub fn constructor_to_amode<C: Context>( |
1761 | 1.56M | ctx: &mut C, |
1762 | 1.56M | arg0: MemFlags, |
1763 | 1.56M | arg1: Value, |
1764 | 1.56M | arg2: Offset32, |
1765 | 1.56M | ) -> Amode { |
1766 | 1.56M | let v6 = C::def_inst(ctx, arg1); |
1767 | 1.56M | if let Some(v71.21M ) = v6 { |
1768 | 1.21M | let v8 = &C::inst_data(ctx, v7); |
1769 | | if let &InstructionData::Binary { |
1770 | 1.05M | opcode: ref v9, |
1771 | 1.05M | args: ref v10, |
1772 | 1.21M | } = v8 { |
1773 | 1.05M | if let &Opcode::Iadd = v9 { |
1774 | 1.04M | let v11 = C::unpack_value_array_2(ctx, v10); |
1775 | 1.04M | let v14 = &constructor_to_amode_add(ctx, arg0, v11.0, v11.1, arg2); |
1776 | 1.04M | // Rule at src/isa/x64/inst.isle line 1009. |
1777 | 1.04M | return v14.clone(); |
1778 | 11.5k | } |
1779 | 156k | } |
1780 | 352k | } |
1781 | 520k | let v4 = C::put_in_reg(ctx, arg1); |
1782 | 520k | let v3 = C::offset32_to_u32(ctx, arg2); |
1783 | 520k | let v5 = Amode::ImmReg { |
1784 | 520k | simm32: v3, |
1785 | 520k | base: v4, |
1786 | 520k | flags: arg0, |
1787 | 520k | }; |
1788 | 520k | // Rule at src/isa/x64/inst.isle line 1004. |
1789 | 520k | return v5; |
1790 | 1.56M | } |
1791 | | |
1792 | | // Generated as internal constructor for term to_amode_add. |
1793 | 1.53M | pub fn constructor_to_amode_add<C: Context>( |
1794 | 1.53M | ctx: &mut C, |
1795 | 1.53M | arg0: MemFlags, |
1796 | 1.53M | arg1: Value, |
1797 | 1.53M | arg2: Value, |
1798 | 1.53M | arg3: Offset32, |
1799 | 1.53M | ) -> Amode { |
1800 | 1.53M | let v30 = C::def_inst(ctx, arg1); |
1801 | 1.53M | if let Some(v311.36M ) = v30 { |
1802 | 1.36M | let v32 = &C::inst_data(ctx, v31); |
1803 | | if let &InstructionData::UnaryImm { |
1804 | 18.4E | opcode: ref v71, |
1805 | 18.4E | imm: v72, |
1806 | 1.36M | } = v32 { |
1807 | 18.4E | if let &Opcode::Iconst = v71 { |
1808 | 18.4E | let v73 = C::simm32(ctx, v72); |
1809 | 18.4E | if let Some(v74) = v73 { |
1810 | 18.4E | let v4 = C::offset32_to_u32(ctx, arg3); |
1811 | 18.4E | let v75 = C::s32_add_fallible(ctx, v4, v74); |
1812 | 18.4E | if let Some(v760 ) = v75 { |
1813 | 0 | let v77 = C::u32_to_offset32(ctx, v76); |
1814 | 0 | let v78 = &constructor_to_amode(ctx, arg0, arg2, v77); |
1815 | 0 | // Rule at src/isa/x64/inst.isle line 1048. |
1816 | 0 | return v78.clone(); |
1817 | 0 | } |
1818 | 0 | } |
1819 | 0 | } |
1820 | 1.36M | } |
1821 | 176k | } |
1822 | 1.53M | let v9 = C::def_inst(ctx, arg2); |
1823 | 1.53M | if let Some(v101.52M ) = v9 { |
1824 | 1.52M | let v11 = &C::inst_data(ctx, v10); |
1825 | 1.52M | match v11 { |
1826 | | &InstructionData::Binary { |
1827 | 85.9k | opcode: ref v12, |
1828 | 85.9k | args: ref v13, |
1829 | 85.9k | } => { |
1830 | 85.9k | if let &Opcode::Iadd = v12 { |
1831 | 2.96k | let v14 = C::unpack_value_array_2(ctx, v13); |
1832 | 2.96k | let v17 = C::def_inst(ctx, v14.1); |
1833 | 2.96k | if let Some(v182.93k ) = v17 { |
1834 | 2.93k | let v19 = &C::inst_data(ctx, v18); |
1835 | | if let &InstructionData::UnaryImm { |
1836 | 2.37k | opcode: ref v20, |
1837 | 2.37k | imm: v21, |
1838 | 2.93k | } = v19 { |
1839 | 2.37k | if let &Opcode::Iconst = v20 { |
1840 | 2.37k | let v57 = C::simm32(ctx, v21); |
1841 | 2.37k | if let Some(v582.37k ) = v57 { |
1842 | 2.37k | let v4 = C::offset32_to_u32(ctx, arg3); |
1843 | 2.37k | let v59 = C::s32_add_fallible(ctx, v4, v58); |
1844 | 2.61k | if let Some(v60) = v592.37k { |
1845 | 2.61k | let v61 = C::u32_to_offset32(ctx, v60); |
1846 | 2.61k | let v62 = &constructor_to_amode_add(ctx, arg0, arg1, v14.0, v61); |
1847 | 2.61k | // Rule at src/isa/x64/inst.isle line 1042. |
1848 | 2.61k | return v62.clone(); |
1849 | 0 | } |
1850 | 5 | } |
1851 | 0 | } |
1852 | 557 | } |
1853 | 29 | } |
1854 | 82.9k | } |
1855 | | } |
1856 | | &InstructionData::UnaryImm { |
1857 | 737k | opcode: ref v63, |
1858 | 737k | imm: v64, |
1859 | 737k | } => { |
1860 | 737k | if let &Opcode::Iconst = v63 { |
1861 | 737k | let v65 = C::simm32(ctx, v64); |
1862 | 737k | if let Some(v66581k ) = v65 { |
1863 | 581k | let v4 = C::offset32_to_u32(ctx, arg3); |
1864 | 581k | let v67 = C::s32_add_fallible(ctx, v4, v66); |
1865 | 581k | if let Some(v68) = v67581k { |
1866 | 581k | let v69 = C::u32_to_offset32(ctx, v68); |
1867 | 581k | let v70 = &constructor_to_amode(ctx, arg0, arg1, v69); |
1868 | 581k | // Rule at src/isa/x64/inst.isle line 1045. |
1869 | 581k | return v70.clone(); |
1870 | 0 | } |
1871 | 155k | } |
1872 | 0 | } |
1873 | | } |
1874 | 699k | _ => {} |
1875 | | } |
1876 | 15.7k | } |
1877 | 954k | if let Some(v31937k ) = v30 { |
1878 | 937k | let v32 = &C::inst_data(ctx, v31); |
1879 | | if let &InstructionData::Binary { |
1880 | 11.6k | opcode: ref v33, |
1881 | 11.6k | args: ref v34, |
1882 | 937k | } = v32 { |
1883 | 11.6k | match v33 { |
1884 | | &Opcode::Iadd => { |
1885 | 8.80k | let v35 = C::unpack_value_array_2(ctx, v34); |
1886 | 8.80k | let v38 = C::def_inst(ctx, v35.1); |
1887 | 8.80k | if let Some(v398.55k ) = v38 { |
1888 | 8.55k | let v40 = &C::inst_data(ctx, v39); |
1889 | | if let &InstructionData::UnaryImm { |
1890 | 3.18k | opcode: ref v41, |
1891 | 3.18k | imm: v42, |
1892 | 8.55k | } = v40 { |
1893 | 3.18k | if let &Opcode::Iconst = v41 { |
1894 | 3.18k | let v51 = C::simm32(ctx, v42); |
1895 | 3.18k | if let Some(v522.75k ) = v51 { |
1896 | 2.75k | let v4 = C::offset32_to_u32(ctx, arg3); |
1897 | 2.75k | let v53 = C::s32_add_fallible(ctx, v4, v52); |
1898 | 2.75k | if let Some(v542.42k ) = v53 { |
1899 | 2.42k | let v55 = C::u32_to_offset32(ctx, v54); |
1900 | 2.42k | let v56 = &constructor_to_amode_add(ctx, arg0, v35.0, arg2, v55); |
1901 | 2.42k | // Rule at src/isa/x64/inst.isle line 1039. |
1902 | 2.42k | return v56.clone(); |
1903 | 0 | } |
1904 | 423 | } |
1905 | 0 | } |
1906 | 5.37k | } |
1907 | 250 | } |
1908 | | } |
1909 | | &Opcode::Ishl => { |
1910 | 474 | let v35 = C::unpack_value_array_2(ctx, v34); |
1911 | 474 | let v38 = C::def_inst(ctx, v35.1); |
1912 | 474 | if let Some(v39) = v38 { |
1913 | 474 | let v40 = &C::inst_data(ctx, v39); |
1914 | | if let &InstructionData::UnaryImm { |
1915 | 469 | opcode: ref v41, |
1916 | 469 | imm: v42, |
1917 | 474 | } = v40 { |
1918 | 469 | if let &Opcode::Iconst = v41 { |
1919 | 469 | let v43 = C::uimm8(ctx, v42); |
1920 | 469 | if let Some(v44) = v43 { |
1921 | 469 | let v45 = C::u8_as_u32(ctx, v44); |
1922 | 469 | let v46 = C::u32_lteq(ctx, v45, 0x3); |
1923 | 469 | if let Some(v47435 ) = v46 { |
1924 | 435 | let v48 = constructor_put_in_gpr(ctx, arg2); |
1925 | 435 | let v49 = constructor_put_in_gpr(ctx, v35.0); |
1926 | 435 | let v4 = C::offset32_to_u32(ctx, arg3); |
1927 | 435 | let v50 = Amode::ImmRegRegShift { |
1928 | 435 | simm32: v4, |
1929 | 435 | base: v48, |
1930 | 435 | index: v49, |
1931 | 435 | shift: v44, |
1932 | 435 | flags: arg0, |
1933 | 435 | }; |
1934 | 435 | // Rule at src/isa/x64/inst.isle line 1026. |
1935 | 435 | return v50; |
1936 | 34 | } |
1937 | 0 | } |
1938 | 0 | } |
1939 | 5 | } |
1940 | 0 | } |
1941 | | } |
1942 | 2.39k | _ => {} |
1943 | | } |
1944 | 925k | } |
1945 | 17.2k | } |
1946 | 951k | if let Some(v10936k ) = v9 { |
1947 | 936k | let v11 = &C::inst_data(ctx, v10); |
1948 | | if let &InstructionData::Binary { |
1949 | 81.4k | opcode: ref v12, |
1950 | 81.4k | args: ref v13, |
1951 | 936k | } = v11 { |
1952 | 81.4k | if let &Opcode::Ishl = v12 { |
1953 | 32.8k | let v14 = C::unpack_value_array_2(ctx, v13); |
1954 | 32.8k | let v17 = C::def_inst(ctx, v14.1); |
1955 | 32.8k | if let Some(v18) = v17 { |
1956 | 32.8k | let v19 = &C::inst_data(ctx, v18); |
1957 | | if let &InstructionData::UnaryImm { |
1958 | 32.8k | opcode: ref v20, |
1959 | 32.8k | imm: v21, |
1960 | 32.8k | } = v19 { |
1961 | 32.8k | if let &Opcode::Iconst = v20 { |
1962 | 32.8k | let v22 = C::uimm8(ctx, v21); |
1963 | 32.8k | if let Some(v23) = v22 { |
1964 | 32.8k | let v24 = C::u8_as_u32(ctx, v23); |
1965 | 32.8k | let v26 = C::u32_lteq(ctx, v24, 0x3); |
1966 | 32.8k | if let Some(v2729.1k ) = v26 { |
1967 | 29.1k | let v5 = constructor_put_in_gpr(ctx, arg1); |
1968 | 29.1k | let v28 = constructor_put_in_gpr(ctx, v14.0); |
1969 | 29.1k | let v4 = C::offset32_to_u32(ctx, arg3); |
1970 | 29.1k | let v29 = Amode::ImmRegRegShift { |
1971 | 29.1k | simm32: v4, |
1972 | 29.1k | base: v5, |
1973 | 29.1k | index: v28, |
1974 | 29.1k | shift: v23, |
1975 | 29.1k | flags: arg0, |
1976 | 29.1k | }; |
1977 | 29.1k | // Rule at src/isa/x64/inst.isle line 1023. |
1978 | 29.1k | return v29; |
1979 | 3.64k | } |
1980 | 0 | } |
1981 | 0 | } |
1982 | 0 | } |
1983 | 0 | } |
1984 | 48.5k | } |
1985 | 854k | } |
1986 | 15.4k | } |
1987 | 922k | let v5 = constructor_put_in_gpr(ctx, arg1); |
1988 | 922k | let v6 = constructor_put_in_gpr(ctx, arg2); |
1989 | 922k | let v4 = C::offset32_to_u32(ctx, arg3); |
1990 | 922k | let v8 = Amode::ImmRegRegShift { |
1991 | 922k | simm32: v4, |
1992 | 922k | base: v5, |
1993 | 922k | index: v6, |
1994 | 922k | shift: 0x0, |
1995 | 922k | flags: arg0, |
1996 | 922k | }; |
1997 | 922k | // Rule at src/isa/x64/inst.isle line 1018. |
1998 | 922k | return v8; |
1999 | 1.53M | } |
2000 | | |
2001 | | // Generated as internal constructor for term put_masked_in_imm8_gpr. |
2002 | 15.7k | pub fn constructor_put_masked_in_imm8_gpr<C: Context>( |
2003 | 15.7k | ctx: &mut C, |
2004 | 15.7k | arg0: Value, |
2005 | 15.7k | arg1: Type, |
2006 | 15.7k | ) -> Imm8Gpr { |
2007 | 15.7k | let v1 = C::def_inst(ctx, arg0); |
2008 | 15.7k | if let Some(v215.7k ) = v1 { |
2009 | 15.7k | let v3 = &C::inst_data(ctx, v2); |
2010 | | if let &InstructionData::UnaryImm { |
2011 | 15.3k | opcode: ref v4, |
2012 | 15.3k | imm: v5, |
2013 | 15.7k | } = v3 { |
2014 | 15.3k | if let &Opcode::Iconst = v4 { |
2015 | 15.3k | let v6 = C::u64_from_imm64(ctx, v5); |
2016 | 15.3k | let v8 = &C::const_to_type_masked_imm8(ctx, v6, arg1); |
2017 | 15.3k | // Rule at src/isa/x64/inst.isle line 1084. |
2018 | 15.3k | return v8.clone(); |
2019 | 0 | } |
2020 | 374 | } |
2021 | 13 | } |
2022 | 387 | let v9 = C::fits_in_16(ctx, arg1); |
2023 | 387 | if let Some(v100 ) = v9 { |
2024 | 0 | let v12 = C::put_in_regs(ctx, arg0); |
2025 | 0 | let v14 = constructor_value_regs_get_gpr(ctx, v12, 0x0); |
2026 | 0 | let v15 = C::shift_mask(ctx, v10); |
2027 | 0 | let v16 = RegMemImm::Imm { |
2028 | 0 | simm32: v15, |
2029 | 0 | }; |
2030 | 0 | let v17 = &C::gpr_mem_imm_new(ctx, &v16); |
2031 | 0 | let v18 = constructor_x64_and(ctx, I64, v14, v17); |
2032 | 0 | let v19 = &C::gpr_to_imm8_gpr(ctx, v18); |
2033 | 0 | // Rule at src/isa/x64/inst.isle line 1086. |
2034 | 0 | return v19.clone(); |
2035 | 387 | } |
2036 | 387 | let v12 = C::put_in_regs(ctx, arg0); |
2037 | 387 | let v14 = constructor_value_regs_get_gpr(ctx, v12, 0x0); |
2038 | 387 | let v20 = &C::gpr_to_imm8_gpr(ctx, v14); |
2039 | 387 | // Rule at src/isa/x64/inst.isle line 1088. |
2040 | 387 | return v20.clone(); |
2041 | 15.7k | } |
2042 | | |
2043 | | // Generated as internal constructor for term reg_to_gpr_mem_imm. |
2044 | 9.09k | pub fn constructor_reg_to_gpr_mem_imm<C: Context>( |
2045 | 9.09k | ctx: &mut C, |
2046 | 9.09k | arg0: Reg, |
2047 | 9.09k | ) -> GprMemImm { |
2048 | 9.09k | let v1 = C::gpr_new(ctx, arg0); |
2049 | 9.09k | let v2 = &C::gpr_to_gpr_mem_imm(ctx, v1); |
2050 | 9.09k | // Rule at src/isa/x64/inst.isle line 1493. |
2051 | 9.09k | return v2.clone(); |
2052 | 9.09k | } |
2053 | | |
2054 | | // Generated as internal constructor for term put_in_gpr. |
2055 | 2.96M | pub fn constructor_put_in_gpr<C: Context>( |
2056 | 2.96M | ctx: &mut C, |
2057 | 2.96M | arg0: Value, |
2058 | 2.96M | ) -> Gpr { |
2059 | 2.96M | let v1 = C::put_in_reg(ctx, arg0); |
2060 | 2.96M | let v2 = C::gpr_new(ctx, v1); |
2061 | 2.96M | // Rule at src/isa/x64/inst.isle line 1500. |
2062 | 2.96M | return v2; |
2063 | 2.96M | } |
2064 | | |
2065 | | // Generated as internal constructor for term put_in_gpr_mem. |
2066 | 106k | pub fn constructor_put_in_gpr_mem<C: Context>( |
2067 | 106k | ctx: &mut C, |
2068 | 106k | arg0: Value, |
2069 | 106k | ) -> GprMem { |
2070 | 106k | let v1 = &C::put_in_reg_mem(ctx, arg0); |
2071 | 106k | let v2 = &C::reg_mem_to_gpr_mem(ctx, v1); |
2072 | 106k | // Rule at src/isa/x64/inst.isle line 1507. |
2073 | 106k | return v2.clone(); |
2074 | 106k | } |
2075 | | |
2076 | | // Generated as internal constructor for term put_in_gpr_mem_imm. |
2077 | 250k | pub fn constructor_put_in_gpr_mem_imm<C: Context>( |
2078 | 250k | ctx: &mut C, |
2079 | 250k | arg0: Value, |
2080 | 250k | ) -> GprMemImm { |
2081 | 250k | let v1 = &C::put_in_reg_mem_imm(ctx, arg0); |
2082 | 250k | let v2 = &C::gpr_mem_imm_new(ctx, v1); |
2083 | 250k | // Rule at src/isa/x64/inst.isle line 1514. |
2084 | 250k | return v2.clone(); |
2085 | 250k | } |
2086 | | |
2087 | | // Generated as internal constructor for term put_in_xmm. |
2088 | 1 | pub fn constructor_put_in_xmm<C: Context>( |
2089 | 1 | ctx: &mut C, |
2090 | 1 | arg0: Value, |
2091 | 1 | ) -> Xmm { |
2092 | 1 | let v1 = C::put_in_reg(ctx, arg0); |
2093 | 1 | let v2 = C::xmm_new(ctx, v1); |
2094 | 1 | // Rule at src/isa/x64/inst.isle line 1521. |
2095 | 1 | return v2; |
2096 | 1 | } |
2097 | | |
2098 | | // Generated as internal constructor for term output_gpr. |
2099 | 1.32M | pub fn constructor_output_gpr<C: Context>( |
2100 | 1.32M | ctx: &mut C, |
2101 | 1.32M | arg0: Gpr, |
2102 | 1.32M | ) -> InstOutput { |
2103 | 1.32M | let v1 = C::gpr_to_reg(ctx, arg0); |
2104 | 1.32M | let v2 = constructor_output_reg(ctx, v1); |
2105 | 1.32M | // Rule at src/isa/x64/inst.isle line 1538. |
2106 | 1.32M | return v2; |
2107 | 1.32M | } |
2108 | | |
2109 | | // Generated as internal constructor for term value_gprs. |
2110 | 0 | pub fn constructor_value_gprs<C: Context>( |
2111 | 0 | ctx: &mut C, |
2112 | 0 | arg0: Gpr, |
2113 | 0 | arg1: Gpr, |
2114 | 0 | ) -> ValueRegs { |
2115 | 0 | let v2 = C::gpr_to_reg(ctx, arg0); |
2116 | 0 | let v3 = C::gpr_to_reg(ctx, arg1); |
2117 | 0 | let v4 = C::value_regs(ctx, v2, v3); |
2118 | 0 | // Rule at src/isa/x64/inst.isle line 1543. |
2119 | 0 | return v4; |
2120 | 0 | } |
2121 | | |
2122 | | // Generated as internal constructor for term output_xmm. |
2123 | 0 | pub fn constructor_output_xmm<C: Context>( |
2124 | 0 | ctx: &mut C, |
2125 | 0 | arg0: Xmm, |
2126 | 0 | ) -> InstOutput { |
2127 | 0 | let v1 = C::xmm_to_reg(ctx, arg0); |
2128 | 0 | let v2 = constructor_output_reg(ctx, v1); |
2129 | 0 | // Rule at src/isa/x64/inst.isle line 1548. |
2130 | 0 | return v2; |
2131 | 0 | } |
2132 | | |
2133 | | // Generated as internal constructor for term value_regs_get_gpr. |
2134 | 6.68k | pub fn constructor_value_regs_get_gpr<C: Context>( |
2135 | 6.68k | ctx: &mut C, |
2136 | 6.68k | arg0: ValueRegs, |
2137 | 6.68k | arg1: usize, |
2138 | 6.68k | ) -> Gpr { |
2139 | 6.68k | let v2 = C::value_regs_get(ctx, arg0, arg1); |
2140 | 6.68k | let v3 = C::gpr_new(ctx, v2); |
2141 | 6.68k | // Rule at src/isa/x64/inst.isle line 1555. |
2142 | 6.68k | return v3; |
2143 | 6.68k | } |
2144 | | |
2145 | | // Generated as internal constructor for term lo_gpr. |
2146 | 0 | pub fn constructor_lo_gpr<C: Context>( |
2147 | 0 | ctx: &mut C, |
2148 | 0 | arg0: Value, |
2149 | 0 | ) -> Gpr { |
2150 | 0 | let v1 = constructor_lo_reg(ctx, arg0); |
2151 | 0 | let v2 = C::gpr_new(ctx, v1); |
2152 | 0 | // Rule at src/isa/x64/inst.isle line 1568. |
2153 | 0 | return v2; |
2154 | 0 | } |
2155 | | |
2156 | | // Generated as internal constructor for term sink_load_to_gpr_mem_imm. |
2157 | 6.82k | pub fn constructor_sink_load_to_gpr_mem_imm<C: Context>( |
2158 | 6.82k | ctx: &mut C, |
2159 | 6.82k | arg0: &SinkableLoad, |
2160 | 6.82k | ) -> GprMemImm { |
2161 | 6.82k | let v1 = &constructor_sink_load_to_reg_mem_imm(ctx, arg0); |
2162 | 6.82k | let v2 = &C::gpr_mem_imm_new(ctx, v1); |
2163 | 6.82k | // Rule at src/isa/x64/inst.isle line 1703. |
2164 | 6.82k | return v2.clone(); |
2165 | 6.82k | } |
2166 | | |
2167 | | // Generated as internal constructor for term sink_load_to_xmm_mem. |
2168 | 0 | pub fn constructor_sink_load_to_xmm_mem<C: Context>( |
2169 | 0 | ctx: &mut C, |
2170 | 0 | arg0: &SinkableLoad, |
2171 | 0 | ) -> XmmMem { |
2172 | 0 | let v1 = &constructor_sink_load_to_reg_mem(ctx, arg0); |
2173 | 0 | let v2 = &C::reg_mem_to_xmm_mem(ctx, v1); |
2174 | 0 | // Rule at src/isa/x64/inst.isle line 1707. |
2175 | 0 | return v2.clone(); |
2176 | 0 | } |
2177 | | |
2178 | | // Generated as internal constructor for term sink_load_to_reg_mem. |
2179 | 0 | pub fn constructor_sink_load_to_reg_mem<C: Context>( |
2180 | 0 | ctx: &mut C, |
2181 | 0 | arg0: &SinkableLoad, |
2182 | 0 | ) -> RegMem { |
2183 | 0 | let v1 = &C::sink_load(ctx, arg0); |
2184 | 0 | let v2 = RegMem::Mem { |
2185 | 0 | addr: v1.clone(), |
2186 | 0 | }; |
2187 | 0 | // Rule at src/isa/x64/inst.isle line 1711. |
2188 | 0 | return v2; |
2189 | 0 | } |
2190 | | |
2191 | | // Generated as internal constructor for term sink_load_to_gpr_mem. |
2192 | 0 | pub fn constructor_sink_load_to_gpr_mem<C: Context>( |
2193 | 0 | ctx: &mut C, |
2194 | 0 | arg0: &SinkableLoad, |
2195 | 0 | ) -> GprMem { |
2196 | 0 | let v1 = &C::sink_load(ctx, arg0); |
2197 | 0 | let v2 = RegMem::Mem { |
2198 | 0 | addr: v1.clone(), |
2199 | 0 | }; |
2200 | 0 | let v3 = &C::reg_mem_to_gpr_mem(ctx, &v2); |
2201 | 0 | // Rule at src/isa/x64/inst.isle line 1714. |
2202 | 0 | return v3.clone(); |
2203 | 0 | } |
2204 | | |
2205 | | // Generated as internal constructor for term sink_load_to_reg_mem_imm. |
2206 | 8.26k | pub fn constructor_sink_load_to_reg_mem_imm<C: Context>( |
2207 | 8.26k | ctx: &mut C, |
2208 | 8.26k | arg0: &SinkableLoad, |
2209 | 8.26k | ) -> RegMemImm { |
2210 | 8.26k | let v1 = &C::sink_load(ctx, arg0); |
2211 | 8.26k | let v2 = RegMemImm::Mem { |
2212 | 8.26k | addr: v1.clone(), |
2213 | 8.26k | }; |
2214 | 8.26k | // Rule at src/isa/x64/inst.isle line 1717. |
2215 | 8.26k | return v2; |
2216 | 8.26k | } |
2217 | | |
2218 | | // Generated as internal constructor for term extend_to_gpr. |
2219 | 393k | pub fn constructor_extend_to_gpr<C: Context>( |
2220 | 393k | ctx: &mut C, |
2221 | 393k | arg0: Value, |
2222 | 393k | arg1: Type, |
2223 | 393k | arg2: &ExtendKind, |
2224 | 393k | ) -> Gpr { |
2225 | 393k | let v1 = C::value_type(ctx, arg0); |
2226 | 393k | if v1 == arg1 { |
2227 | 6.78k | let v4 = constructor_put_in_gpr(ctx, arg0); |
2228 | 6.78k | // Rule at src/isa/x64/inst.isle line 1738. |
2229 | 6.78k | return v4; |
2230 | 386k | } |
2231 | 386k | if let &ExtendKind::Zero = arg2 { |
2232 | 386k | if v1 == I32 { |
2233 | 377k | if arg1 == I64 { |
2234 | 377k | let v5 = constructor_value32_zeros_upper32(ctx, arg0); |
2235 | 377k | if v5 == true { |
2236 | 289k | let v4 = constructor_put_in_gpr(ctx, arg0); |
2237 | 289k | // Rule at src/isa/x64/inst.isle line 1746. |
2238 | 289k | return v4; |
2239 | 88.9k | } |
2240 | 85 | } |
2241 | 8.85k | } |
2242 | 97.8k | let v6 = C::def_inst(ctx, arg0); |
2243 | 97.8k | if let Some(v761.4k ) = v6 { |
2244 | 61.4k | let v8 = &C::inst_data(ctx, v7); |
2245 | | if let &InstructionData::BinaryImm8 { |
2246 | 110 | opcode: ref v9, |
2247 | 110 | arg: v10, |
2248 | 110 | imm: v11, |
2249 | 61.4k | } = v8 { |
2250 | 110 | if let &Opcode::Extractlane = v9 { |
2251 | 0 | let v4 = constructor_put_in_gpr(ctx, arg0); |
2252 | 0 | // Rule at src/isa/x64/inst.isle line 1762. |
2253 | 0 | return v4; |
2254 | 0 | } |
2255 | 61.3k | } |
2256 | 36.4k | } |
2257 | 4 | } |
2258 | 97.7k | let v13 = &C::operand_size_of_type_32_64(ctx, arg1); |
2259 | 97.7k | let v14 = constructor_operand_size_bits(ctx, v13); |
2260 | 97.7k | let v12 = C::ty_bits_u16(ctx, v1); |
2261 | 97.7k | let v15 = &C::ext_mode(ctx, v12, v14); |
2262 | 97.7k | let v16 = &constructor_put_in_gpr_mem(ctx, arg0); |
2263 | 97.7k | let v17 = constructor_extend(ctx, arg2, arg1, v15, v16); |
2264 | 97.7k | // Rule at src/isa/x64/inst.isle line 1765. |
2265 | 97.7k | return v17; |
2266 | 393k | } |
2267 | | |
2268 | | // Generated as internal constructor for term extend. |
2269 | 97.7k | pub fn constructor_extend<C: Context>( |
2270 | 97.7k | ctx: &mut C, |
2271 | 97.7k | arg0: &ExtendKind, |
2272 | 97.7k | arg1: Type, |
2273 | 97.7k | arg2: &ExtMode, |
2274 | 97.7k | arg3: &GprMem, |
2275 | 97.7k | ) -> Gpr { |
2276 | 97.7k | match arg0 { |
2277 | | &ExtendKind::Sign => { |
2278 | 4 | let v5 = constructor_x64_movsx(ctx, arg2, arg3); |
2279 | 4 | // Rule at src/isa/x64/inst.isle line 1785. |
2280 | 4 | return v5; |
2281 | | } |
2282 | | &ExtendKind::Zero => { |
2283 | 97.7k | let v4 = constructor_x64_movzx(ctx, arg2, arg3); |
2284 | 97.7k | // Rule at src/isa/x64/inst.isle line 1781. |
2285 | 97.7k | return v4; |
2286 | | } |
2287 | 0 | _ => {} |
2288 | 0 | } |
2289 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "extend", "src/isa/x64/inst.isle line 1778") |
2290 | 97.7k | } |
2291 | | |
2292 | | // Generated as internal constructor for term value32_zeros_upper32. |
2293 | 377k | pub fn constructor_value32_zeros_upper32<C: Context>( |
2294 | 377k | ctx: &mut C, |
2295 | 377k | arg0: Value, |
2296 | 377k | ) -> bool { |
2297 | 377k | let v1 = C::def_inst(ctx, arg0); |
2298 | 377k | if let Some(v2341k ) = v1 { |
2299 | 341k | let v3 = &C::inst_data(ctx, v2); |
2300 | 341k | match v3 { |
2301 | | &InstructionData::Binary { |
2302 | 289k | opcode: ref v4, |
2303 | 289k | args: ref v5, |
2304 | 289k | } => { |
2305 | 289k | match v4 { |
2306 | | &Opcode::Iadd => { |
2307 | | // Rule at src/isa/x64/inst.isle line 1792. |
2308 | 275k | return true; |
2309 | | } |
2310 | | &Opcode::Isub => { |
2311 | | // Rule at src/isa/x64/inst.isle line 1793. |
2312 | 12.3k | return true; |
2313 | | } |
2314 | | &Opcode::Imul => { |
2315 | | // Rule at src/isa/x64/inst.isle line 1794. |
2316 | 3 | return true; |
2317 | | } |
2318 | | &Opcode::Band => { |
2319 | | // Rule at src/isa/x64/inst.isle line 1795. |
2320 | 401 | return true; |
2321 | | } |
2322 | | &Opcode::Bor => { |
2323 | | // Rule at src/isa/x64/inst.isle line 1796. |
2324 | 429 | return true; |
2325 | | } |
2326 | | &Opcode::Bxor => { |
2327 | | // Rule at src/isa/x64/inst.isle line 1797. |
2328 | 28 | return true; |
2329 | | } |
2330 | | &Opcode::Ishl => { |
2331 | | // Rule at src/isa/x64/inst.isle line 1798. |
2332 | 14 | return true; |
2333 | | } |
2334 | | &Opcode::Ushr => { |
2335 | | // Rule at src/isa/x64/inst.isle line 1799. |
2336 | 72 | return true; |
2337 | | } |
2338 | 669 | _ => {} |
2339 | | } |
2340 | | } |
2341 | | &InstructionData::Load { |
2342 | 43.7k | opcode: ref v10, |
2343 | 43.7k | arg: v11, |
2344 | 43.7k | flags: v12, |
2345 | 43.7k | offset: v13, |
2346 | 43.7k | } => { |
2347 | 43.7k | if let &Opcode::Uload32 = v10 { |
2348 | | // Rule at src/isa/x64/inst.isle line 1800. |
2349 | 0 | return true; |
2350 | 43.7k | } |
2351 | | } |
2352 | 8.08k | _ => {} |
2353 | | } |
2354 | 36.4k | } |
2355 | | // Rule at src/isa/x64/inst.isle line 1801. |
2356 | 88.9k | return false; |
2357 | 378k | } |
2358 | | |
2359 | | // Generated as internal constructor for term vec_int_type. |
2360 | 0 | pub fn constructor_vec_int_type<C: Context>( |
2361 | 0 | ctx: &mut C, |
2362 | 0 | arg0: Type, |
2363 | 0 | ) -> Type { |
2364 | 0 | let v1 = C::multi_lane(ctx, arg0); |
2365 | 0 | if let Some(v2) = v1 { |
2366 | 0 | match v2.0 { |
2367 | | 0x8 => { |
2368 | 0 | if v2.1 == 0x10 { |
2369 | | // Rule at src/isa/x64/inst.isle line 1807. |
2370 | 0 | return I8X16; |
2371 | 0 | } |
2372 | | } |
2373 | | 0x10 => { |
2374 | 0 | if v2.1 == 0x8 { |
2375 | | // Rule at src/isa/x64/inst.isle line 1808. |
2376 | 0 | return I16X8; |
2377 | 0 | } |
2378 | | } |
2379 | | 0x20 => { |
2380 | 0 | if v2.1 == 0x4 { |
2381 | | // Rule at src/isa/x64/inst.isle line 1809. |
2382 | 0 | return I32X4; |
2383 | 0 | } |
2384 | | } |
2385 | | 0x40 => { |
2386 | 0 | if v2.1 == 0x2 { |
2387 | | // Rule at src/isa/x64/inst.isle line 1810. |
2388 | 0 | return I64X2; |
2389 | 0 | } |
2390 | | } |
2391 | 0 | _ => {} |
2392 | | } |
2393 | 0 | } |
2394 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "vec_int_type", "src/isa/x64/inst.isle line 1806") |
2395 | 0 | } |
2396 | | |
2397 | | // Generated as internal constructor for term x64_xor_vector. |
2398 | 0 | pub fn constructor_x64_xor_vector<C: Context>( |
2399 | 0 | ctx: &mut C, |
2400 | 0 | arg0: Type, |
2401 | 0 | arg1: Xmm, |
2402 | 0 | arg2: &XmmMem, |
2403 | 0 | ) -> Xmm { |
2404 | 0 | match arg0 { |
2405 | | F32 => { |
2406 | 0 | let v3 = constructor_x64_xorps(ctx, arg1, arg2); |
2407 | 0 | // Rule at src/isa/x64/inst.isle line 1814. |
2408 | 0 | return v3; |
2409 | | } |
2410 | | F64 => { |
2411 | 0 | let v4 = constructor_x64_xorpd(ctx, arg1, arg2); |
2412 | 0 | // Rule at src/isa/x64/inst.isle line 1815. |
2413 | 0 | return v4; |
2414 | | } |
2415 | | F32X4 => { |
2416 | 0 | let v3 = constructor_x64_xorps(ctx, arg1, arg2); |
2417 | 0 | // Rule at src/isa/x64/inst.isle line 1816. |
2418 | 0 | return v3; |
2419 | | } |
2420 | | F64X2 => { |
2421 | 0 | let v4 = constructor_x64_xorpd(ctx, arg1, arg2); |
2422 | 0 | // Rule at src/isa/x64/inst.isle line 1817. |
2423 | 0 | return v4; |
2424 | | } |
2425 | 0 | _ => {} |
2426 | 0 | } |
2427 | 0 | let v5 = C::multi_lane(ctx, arg0); |
2428 | 0 | if let Some(v6) = v5 { |
2429 | 0 | let v9 = constructor_x64_pxor(ctx, arg1, arg2); |
2430 | 0 | // Rule at src/isa/x64/inst.isle line 1818. |
2431 | 0 | return v9; |
2432 | 0 | } |
2433 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "x64_xor_vector", "src/isa/x64/inst.isle line 1813") |
2434 | 0 | } |
2435 | | |
2436 | | // Generated as internal constructor for term vector_all_ones. |
2437 | 0 | pub fn constructor_vector_all_ones<C: Context>( |
2438 | 0 | ctx: &mut C, |
2439 | 0 | ) -> Xmm { |
2440 | 0 | let v0 = constructor_xmm_uninit_value(ctx); |
2441 | 0 | let v1 = &C::xmm_to_xmm_mem(ctx, v0); |
2442 | 0 | let v2 = constructor_x64_pcmpeqd(ctx, v0, v1); |
2443 | 0 | // Rule at src/isa/x64/inst.isle line 1830. |
2444 | 0 | return v2; |
2445 | 0 | } |
2446 | | |
2447 | | // Generated as internal constructor for term xmm_uninit_value. |
2448 | 0 | pub fn constructor_xmm_uninit_value<C: Context>( |
2449 | 0 | ctx: &mut C, |
2450 | 0 | ) -> Xmm { |
2451 | 0 | let v0 = C::temp_writable_xmm(ctx); |
2452 | 0 | let v1 = MInst::XmmUninitializedValue { |
2453 | 0 | dst: v0, |
2454 | 0 | }; |
2455 | 0 | let v2 = C::emit(ctx, &v1); |
2456 | 0 | let v3 = C::writable_xmm_to_xmm(ctx, v0); |
2457 | 0 | // Rule at src/isa/x64/inst.isle line 1836. |
2458 | 0 | return v3; |
2459 | 0 | } |
2460 | | |
2461 | | // Generated as internal constructor for term make_i64x2_from_lanes. |
2462 | 0 | pub fn constructor_make_i64x2_from_lanes<C: Context>( |
2463 | 0 | ctx: &mut C, |
2464 | 0 | arg0: &GprMem, |
2465 | 0 | arg1: &GprMem, |
2466 | 0 | ) -> Xmm { |
2467 | 0 | let v2 = constructor_xmm_uninit_value(ctx); |
2468 | 0 | let v4 = constructor_x64_pinsrq(ctx, v2, arg0, 0x0); |
2469 | 0 | let v6 = constructor_x64_pinsrq(ctx, v4, arg1, 0x1); |
2470 | 0 | // Rule at src/isa/x64/inst.isle line 1843. |
2471 | 0 | return v6; |
2472 | 0 | } |
2473 | | |
2474 | | // Generated as internal constructor for term mov_rmi_to_xmm. |
2475 | 0 | pub fn constructor_mov_rmi_to_xmm<C: Context>( |
2476 | 0 | ctx: &mut C, |
2477 | 0 | arg0: &RegMemImm, |
2478 | 0 | ) -> XmmMemImm { |
2479 | 0 | match arg0 { |
2480 | | &RegMemImm::Reg { |
2481 | 0 | reg: v4, |
2482 | 0 | } => { |
2483 | 0 | let v5 = &C::reg_to_gpr_mem(ctx, v4); |
2484 | 0 | let v6 = constructor_x64_movd_to_xmm(ctx, v5); |
2485 | 0 | let v7 = &C::xmm_to_xmm_mem_imm(ctx, v6); |
2486 | 0 | // Rule at src/isa/x64/inst.isle line 1853. |
2487 | 0 | return v7.clone(); |
2488 | | } |
2489 | | &RegMemImm::Mem { |
2490 | 0 | addr: ref v1, |
2491 | 0 | } => { |
2492 | 0 | let v2 = &C::xmm_mem_imm_new(ctx, arg0); |
2493 | 0 | // Rule at src/isa/x64/inst.isle line 1851. |
2494 | 0 | return v2.clone(); |
2495 | | } |
2496 | | &RegMemImm::Imm { |
2497 | 0 | simm32: v3, |
2498 | 0 | } => { |
2499 | 0 | let v2 = &C::xmm_mem_imm_new(ctx, arg0); |
2500 | 0 | // Rule at src/isa/x64/inst.isle line 1852. |
2501 | 0 | return v2.clone(); |
2502 | | } |
2503 | 0 | _ => {} |
2504 | 0 | } |
2505 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "mov_rmi_to_xmm", "src/isa/x64/inst.isle line 1850") |
2506 | 0 | } |
2507 | | |
2508 | | // Generated as internal constructor for term load_ext_name. |
2509 | 0 | pub fn constructor_load_ext_name<C: Context>( |
2510 | 0 | ctx: &mut C, |
2511 | 0 | arg0: ExternalName, |
2512 | 0 | arg1: i64, |
2513 | 0 | ) -> Reg { |
2514 | 0 | let v2 = C::temp_writable_gpr(ctx); |
2515 | 0 | let v3 = C::writable_gpr_to_reg(ctx, v2); |
2516 | 0 | let v4 = C::box_external_name(ctx, arg0); |
2517 | 0 | let v5 = MInst::LoadExtName { |
2518 | 0 | dst: v3, |
2519 | 0 | name: v4, |
2520 | 0 | offset: arg1, |
2521 | 0 | }; |
2522 | 0 | let v6 = C::emit(ctx, &v5); |
2523 | 0 | let v7 = constructor_writable_gpr_to_r_reg(ctx, v2); |
2524 | 0 | // Rule at src/isa/x64/inst.isle line 1867. |
2525 | 0 | return v7; |
2526 | 0 | } |
2527 | | |
2528 | | // Generated as internal constructor for term x64_load. |
2529 | 0 | pub fn constructor_x64_load<C: Context>( |
2530 | 0 | ctx: &mut C, |
2531 | 0 | arg0: Type, |
2532 | 0 | arg1: &SyntheticAmode, |
2533 | 0 | arg2: &ExtKind, |
2534 | 0 | ) -> Reg { |
2535 | 0 | match arg0 { |
2536 | | I64 => { |
2537 | 0 | let v11 = C::temp_writable_gpr(ctx); |
2538 | 0 | let v12 = MInst::Mov64MR { |
2539 | 0 | src: arg1.clone(), |
2540 | 0 | dst: v11, |
2541 | 0 | }; |
2542 | 0 | let v13 = C::emit(ctx, &v12); |
2543 | 0 | let v14 = constructor_writable_gpr_to_r_reg(ctx, v11); |
2544 | 0 | // Rule at src/isa/x64/inst.isle line 1879. |
2545 | 0 | return v14; |
2546 | | } |
2547 | | F32 => { |
2548 | 0 | let v15 = constructor_x64_movss_load(ctx, arg1); |
2549 | 0 | let v16 = C::xmm_to_reg(ctx, v15); |
2550 | 0 | // Rule at src/isa/x64/inst.isle line 1884. |
2551 | 0 | return v16; |
2552 | | } |
2553 | | F64 => { |
2554 | 0 | let v17 = constructor_x64_movsd_load(ctx, arg1); |
2555 | 0 | let v18 = C::xmm_to_reg(ctx, v17); |
2556 | 0 | // Rule at src/isa/x64/inst.isle line 1887. |
2557 | 0 | return v18; |
2558 | | } |
2559 | | F32X4 => { |
2560 | 0 | let v19 = constructor_x64_movups_load(ctx, arg1); |
2561 | 0 | let v20 = C::xmm_to_reg(ctx, v19); |
2562 | 0 | // Rule at src/isa/x64/inst.isle line 1890. |
2563 | 0 | return v20; |
2564 | | } |
2565 | | F64X2 => { |
2566 | 0 | let v21 = constructor_x64_movupd_load(ctx, arg1); |
2567 | 0 | let v22 = C::xmm_to_reg(ctx, v21); |
2568 | 0 | // Rule at src/isa/x64/inst.isle line 1893. |
2569 | 0 | return v22; |
2570 | | } |
2571 | 0 | _ => {} |
2572 | 0 | } |
2573 | 0 | let v1 = C::fits_in_32(ctx, arg0); |
2574 | 0 | if let Some(v2) = v1 { |
2575 | 0 | if let &ExtKind::SignExtend = arg2 { |
2576 | 0 | let v5 = C::ty_bytes(ctx, v2); |
2577 | 0 | let v7 = &C::ext_mode(ctx, v5, 0x8); |
2578 | 0 | let v8 = &constructor_synthetic_amode_to_gpr_mem(ctx, arg1); |
2579 | 0 | let v9 = constructor_x64_movsx(ctx, v7, v8); |
2580 | 0 | let v10 = C::gpr_to_reg(ctx, v9); |
2581 | 0 | // Rule at src/isa/x64/inst.isle line 1875. |
2582 | 0 | return v10; |
2583 | 0 | } |
2584 | 0 | } |
2585 | 0 | let v23 = C::multi_lane(ctx, arg0); |
2586 | 0 | if let Some(v24) = v23 { |
2587 | 0 | let v27 = &constructor_synthetic_amode_to_xmm_mem(ctx, arg1); |
2588 | 0 | let v28 = constructor_x64_movdqu_load(ctx, v27); |
2589 | 0 | let v29 = C::xmm_to_reg(ctx, v28); |
2590 | 0 | // Rule at src/isa/x64/inst.isle line 1896. |
2591 | 0 | return v29; |
2592 | 0 | } |
2593 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "x64_load", "src/isa/x64/inst.isle line 1873") |
2594 | 0 | } |
2595 | | |
2596 | | // Generated as internal constructor for term x64_mov. |
2597 | 297k | pub fn constructor_x64_mov<C: Context>( |
2598 | 297k | ctx: &mut C, |
2599 | 297k | arg0: &Amode, |
2600 | 297k | ) -> Reg { |
2601 | 297k | let v1 = C::temp_writable_gpr(ctx); |
2602 | 297k | let v2 = &C::amode_to_synthetic_amode(ctx, arg0); |
2603 | 297k | let v3 = MInst::Mov64MR { |
2604 | 297k | src: v2.clone(), |
2605 | 297k | dst: v1, |
2606 | 297k | }; |
2607 | 297k | let v4 = C::emit(ctx, &v3); |
2608 | 297k | let v5 = constructor_writable_gpr_to_r_reg(ctx, v1); |
2609 | 297k | // Rule at src/isa/x64/inst.isle line 1900. |
2610 | 297k | return v5; |
2611 | 297k | } |
2612 | | |
2613 | | // Generated as internal constructor for term x64_movzx. |
2614 | 423k | pub fn constructor_x64_movzx<C: Context>( |
2615 | 423k | ctx: &mut C, |
2616 | 423k | arg0: &ExtMode, |
2617 | 423k | arg1: &GprMem, |
2618 | 423k | ) -> Gpr { |
2619 | 423k | let v2 = C::temp_writable_gpr(ctx); |
2620 | 423k | let v3 = MInst::MovzxRmR { |
2621 | 423k | ext_mode: arg0.clone(), |
2622 | 423k | src: arg1.clone(), |
2623 | 423k | dst: v2, |
2624 | 423k | }; |
2625 | 423k | let v4 = C::emit(ctx, &v3); |
2626 | 423k | let v5 = C::writable_gpr_to_gpr(ctx, v2); |
2627 | 423k | // Rule at src/isa/x64/inst.isle line 1906. |
2628 | 423k | return v5; |
2629 | 423k | } |
2630 | | |
2631 | | // Generated as internal constructor for term x64_movsx. |
2632 | 103 | pub fn constructor_x64_movsx<C: Context>( |
2633 | 103 | ctx: &mut C, |
2634 | 103 | arg0: &ExtMode, |
2635 | 103 | arg1: &GprMem, |
2636 | 103 | ) -> Gpr { |
2637 | 103 | let v2 = C::temp_writable_gpr(ctx); |
2638 | 103 | let v3 = MInst::MovsxRmR { |
2639 | 103 | ext_mode: arg0.clone(), |
2640 | 103 | src: arg1.clone(), |
2641 | 103 | dst: v2, |
2642 | 103 | }; |
2643 | 103 | let v4 = C::emit(ctx, &v3); |
2644 | 103 | let v5 = C::writable_gpr_to_gpr(ctx, v2); |
2645 | 103 | // Rule at src/isa/x64/inst.isle line 1912. |
2646 | 103 | return v5; |
2647 | 103 | } |
2648 | | |
2649 | | // Generated as internal constructor for term x64_movss_load. |
2650 | 0 | pub fn constructor_x64_movss_load<C: Context>( |
2651 | 0 | ctx: &mut C, |
2652 | 0 | arg0: &SyntheticAmode, |
2653 | 0 | ) -> Xmm { |
2654 | 0 | let v4 = C::use_avx_simd(ctx); |
2655 | 0 | if v4 == true { |
2656 | 0 | let v2 = &constructor_synthetic_amode_to_xmm_mem(ctx, arg0); |
2657 | 0 | let v6 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vmovss, v2); |
2658 | 0 | // Rule at src/isa/x64/inst.isle line 1920. |
2659 | 0 | return v6; |
2660 | 0 | } |
2661 | 0 | let v2 = &constructor_synthetic_amode_to_xmm_mem(ctx, arg0); |
2662 | 0 | let v3 = constructor_xmm_unary_rm_r_unaligned(ctx, &SseOpcode::Movss, v2); |
2663 | 0 | // Rule at src/isa/x64/inst.isle line 1918. |
2664 | 0 | return v3; |
2665 | 0 | } |
2666 | | |
2667 | | // Generated as internal constructor for term x64_movss_store. |
2668 | 0 | pub fn constructor_x64_movss_store<C: Context>( |
2669 | 0 | ctx: &mut C, |
2670 | 0 | arg0: &SyntheticAmode, |
2671 | 0 | arg1: Xmm, |
2672 | 0 | ) -> SideEffectNoResult { |
2673 | 0 | let v4 = C::use_avx_simd(ctx); |
2674 | 0 | if v4 == true { |
2675 | 0 | let v6 = &constructor_xmm_movrm_vex(ctx, &AvxOpcode::Vmovss, arg0, arg1); |
2676 | 0 | // Rule at src/isa/x64/inst.isle line 1927. |
2677 | 0 | return v6.clone(); |
2678 | 0 | } |
2679 | 0 | let v3 = &constructor_xmm_movrm(ctx, &SseOpcode::Movss, arg0, arg1); |
2680 | 0 | // Rule at src/isa/x64/inst.isle line 1925. |
2681 | 0 | return v3.clone(); |
2682 | 0 | } |
2683 | | |
2684 | | // Generated as internal constructor for term x64_movsd_load. |
2685 | 0 | pub fn constructor_x64_movsd_load<C: Context>( |
2686 | 0 | ctx: &mut C, |
2687 | 0 | arg0: &SyntheticAmode, |
2688 | 0 | ) -> Xmm { |
2689 | 0 | let v4 = C::use_avx_simd(ctx); |
2690 | 0 | if v4 == true { |
2691 | 0 | let v2 = &constructor_synthetic_amode_to_xmm_mem(ctx, arg0); |
2692 | 0 | let v6 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vmovsd, v2); |
2693 | 0 | // Rule at src/isa/x64/inst.isle line 1934. |
2694 | 0 | return v6; |
2695 | 0 | } |
2696 | 0 | let v2 = &constructor_synthetic_amode_to_xmm_mem(ctx, arg0); |
2697 | 0 | let v3 = constructor_xmm_unary_rm_r_unaligned(ctx, &SseOpcode::Movsd, v2); |
2698 | 0 | // Rule at src/isa/x64/inst.isle line 1932. |
2699 | 0 | return v3; |
2700 | 0 | } |
2701 | | |
2702 | | // Generated as internal constructor for term x64_movsd_store. |
2703 | 1 | pub fn constructor_x64_movsd_store<C: Context>( |
2704 | 1 | ctx: &mut C, |
2705 | 1 | arg0: &SyntheticAmode, |
2706 | 1 | arg1: Xmm, |
2707 | 1 | ) -> SideEffectNoResult { |
2708 | 1 | let v4 = C::use_avx_simd(ctx); |
2709 | 1 | if v4 == true { |
2710 | 0 | let v6 = &constructor_xmm_movrm_vex(ctx, &AvxOpcode::Vmovsd, arg0, arg1); |
2711 | 0 | // Rule at src/isa/x64/inst.isle line 1941. |
2712 | 0 | return v6.clone(); |
2713 | 1 | } |
2714 | 1 | let v3 = &constructor_xmm_movrm(ctx, &SseOpcode::Movsd, arg0, arg1); |
2715 | 1 | // Rule at src/isa/x64/inst.isle line 1939. |
2716 | 1 | return v3.clone(); |
2717 | 1 | } |
2718 | | |
2719 | | // Generated as internal constructor for term x64_movups_load. |
2720 | 0 | pub fn constructor_x64_movups_load<C: Context>( |
2721 | 0 | ctx: &mut C, |
2722 | 0 | arg0: &SyntheticAmode, |
2723 | 0 | ) -> Xmm { |
2724 | 0 | let v4 = C::use_avx_simd(ctx); |
2725 | 0 | if v4 == true { |
2726 | 0 | let v2 = &constructor_synthetic_amode_to_xmm_mem(ctx, arg0); |
2727 | 0 | let v6 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vmovups, v2); |
2728 | 0 | // Rule at src/isa/x64/inst.isle line 1948. |
2729 | 0 | return v6; |
2730 | 0 | } |
2731 | 0 | let v2 = &constructor_synthetic_amode_to_xmm_mem(ctx, arg0); |
2732 | 0 | let v3 = constructor_xmm_unary_rm_r_unaligned(ctx, &SseOpcode::Movups, v2); |
2733 | 0 | // Rule at src/isa/x64/inst.isle line 1946. |
2734 | 0 | return v3; |
2735 | 0 | } |
2736 | | |
2737 | | // Generated as internal constructor for term x64_movups_store. |
2738 | 0 | pub fn constructor_x64_movups_store<C: Context>( |
2739 | 0 | ctx: &mut C, |
2740 | 0 | arg0: &SyntheticAmode, |
2741 | 0 | arg1: Xmm, |
2742 | 0 | ) -> SideEffectNoResult { |
2743 | 0 | let v4 = C::use_avx_simd(ctx); |
2744 | 0 | if v4 == true { |
2745 | 0 | let v6 = &constructor_xmm_movrm_vex(ctx, &AvxOpcode::Vmovups, arg0, arg1); |
2746 | 0 | // Rule at src/isa/x64/inst.isle line 1955. |
2747 | 0 | return v6.clone(); |
2748 | 0 | } |
2749 | 0 | let v3 = &constructor_xmm_movrm(ctx, &SseOpcode::Movups, arg0, arg1); |
2750 | 0 | // Rule at src/isa/x64/inst.isle line 1953. |
2751 | 0 | return v3.clone(); |
2752 | 0 | } |
2753 | | |
2754 | | // Generated as internal constructor for term x64_movupd_load. |
2755 | 0 | pub fn constructor_x64_movupd_load<C: Context>( |
2756 | 0 | ctx: &mut C, |
2757 | 0 | arg0: &SyntheticAmode, |
2758 | 0 | ) -> Xmm { |
2759 | 0 | let v4 = C::use_avx_simd(ctx); |
2760 | 0 | if v4 == true { |
2761 | 0 | let v2 = &constructor_synthetic_amode_to_xmm_mem(ctx, arg0); |
2762 | 0 | let v6 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vmovupd, v2); |
2763 | 0 | // Rule at src/isa/x64/inst.isle line 1962. |
2764 | 0 | return v6; |
2765 | 0 | } |
2766 | 0 | let v2 = &constructor_synthetic_amode_to_xmm_mem(ctx, arg0); |
2767 | 0 | let v3 = constructor_xmm_unary_rm_r_unaligned(ctx, &SseOpcode::Movupd, v2); |
2768 | 0 | // Rule at src/isa/x64/inst.isle line 1960. |
2769 | 0 | return v3; |
2770 | 0 | } |
2771 | | |
2772 | | // Generated as internal constructor for term x64_movupd_store. |
2773 | 0 | pub fn constructor_x64_movupd_store<C: Context>( |
2774 | 0 | ctx: &mut C, |
2775 | 0 | arg0: &SyntheticAmode, |
2776 | 0 | arg1: Xmm, |
2777 | 0 | ) -> SideEffectNoResult { |
2778 | 0 | let v4 = C::use_avx_simd(ctx); |
2779 | 0 | if v4 == true { |
2780 | 0 | let v6 = &constructor_xmm_movrm_vex(ctx, &AvxOpcode::Vmovupd, arg0, arg1); |
2781 | 0 | // Rule at src/isa/x64/inst.isle line 1969. |
2782 | 0 | return v6.clone(); |
2783 | 0 | } |
2784 | 0 | let v3 = &constructor_xmm_movrm(ctx, &SseOpcode::Movupd, arg0, arg1); |
2785 | 0 | // Rule at src/isa/x64/inst.isle line 1967. |
2786 | 0 | return v3.clone(); |
2787 | 0 | } |
2788 | | |
2789 | | // Generated as internal constructor for term x64_movd_to_gpr. |
2790 | 0 | pub fn constructor_x64_movd_to_gpr<C: Context>( |
2791 | 0 | ctx: &mut C, |
2792 | 0 | arg0: Xmm, |
2793 | 0 | ) -> Gpr { |
2794 | 0 | let v4 = C::use_avx_simd(ctx); |
2795 | 0 | if v4 == true { |
2796 | 0 | let v6 = constructor_xmm_to_gpr_vex(ctx, &AvxOpcode::Vmovd, arg0, &OperandSize::Size32); |
2797 | 0 | // Rule at src/isa/x64/inst.isle line 1977. |
2798 | 0 | return v6; |
2799 | 0 | } |
2800 | 0 | let v3 = constructor_xmm_to_gpr(ctx, &SseOpcode::Movd, arg0, &OperandSize::Size32); |
2801 | 0 | // Rule at src/isa/x64/inst.isle line 1975. |
2802 | 0 | return v3; |
2803 | 0 | } |
2804 | | |
2805 | | // Generated as internal constructor for term x64_movd_to_xmm. |
2806 | 0 | pub fn constructor_x64_movd_to_xmm<C: Context>( |
2807 | 0 | ctx: &mut C, |
2808 | 0 | arg0: &GprMem, |
2809 | 0 | ) -> Xmm { |
2810 | 0 | let v4 = C::use_avx_simd(ctx); |
2811 | 0 | if v4 == true { |
2812 | 0 | let v6 = constructor_gpr_to_xmm_vex(ctx, &AvxOpcode::Vmovd, arg0, &OperandSize::Size32); |
2813 | 0 | // Rule at src/isa/x64/inst.isle line 1985. |
2814 | 0 | return v6; |
2815 | 0 | } |
2816 | 0 | let v3 = constructor_gpr_to_xmm(ctx, &SseOpcode::Movd, arg0, &OperandSize::Size32); |
2817 | 0 | // Rule at src/isa/x64/inst.isle line 1983. |
2818 | 0 | return v3; |
2819 | 0 | } |
2820 | | |
2821 | | // Generated as internal constructor for term x64_movq_to_xmm. |
2822 | 0 | pub fn constructor_x64_movq_to_xmm<C: Context>( |
2823 | 0 | ctx: &mut C, |
2824 | 0 | arg0: &GprMem, |
2825 | 0 | ) -> Xmm { |
2826 | 0 | let v4 = C::use_avx_simd(ctx); |
2827 | 0 | if v4 == true { |
2828 | 0 | let v6 = constructor_gpr_to_xmm_vex(ctx, &AvxOpcode::Vmovq, arg0, &OperandSize::Size64); |
2829 | 0 | // Rule at src/isa/x64/inst.isle line 1993. |
2830 | 0 | return v6; |
2831 | 0 | } |
2832 | 0 | let v3 = constructor_gpr_to_xmm(ctx, &SseOpcode::Movq, arg0, &OperandSize::Size64); |
2833 | 0 | // Rule at src/isa/x64/inst.isle line 1991. |
2834 | 0 | return v3; |
2835 | 0 | } |
2836 | | |
2837 | | // Generated as internal constructor for term x64_movq_to_gpr. |
2838 | 0 | pub fn constructor_x64_movq_to_gpr<C: Context>( |
2839 | 0 | ctx: &mut C, |
2840 | 0 | arg0: Xmm, |
2841 | 0 | ) -> Gpr { |
2842 | 0 | let v4 = C::use_avx_simd(ctx); |
2843 | 0 | if v4 == true { |
2844 | 0 | let v6 = constructor_xmm_to_gpr_vex(ctx, &AvxOpcode::Vmovq, arg0, &OperandSize::Size64); |
2845 | 0 | // Rule at src/isa/x64/inst.isle line 2001. |
2846 | 0 | return v6; |
2847 | 0 | } |
2848 | 0 | let v3 = constructor_xmm_to_gpr(ctx, &SseOpcode::Movq, arg0, &OperandSize::Size64); |
2849 | 0 | // Rule at src/isa/x64/inst.isle line 1999. |
2850 | 0 | return v3; |
2851 | 0 | } |
2852 | | |
2853 | | // Generated as internal constructor for term x64_movdqu_load. |
2854 | 0 | pub fn constructor_x64_movdqu_load<C: Context>( |
2855 | 0 | ctx: &mut C, |
2856 | 0 | arg0: &XmmMem, |
2857 | 0 | ) -> Xmm { |
2858 | 0 | let v3 = C::use_avx_simd(ctx); |
2859 | 0 | if v3 == true { |
2860 | 0 | let v5 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vmovdqu, arg0); |
2861 | 0 | // Rule at src/isa/x64/inst.isle line 2008. |
2862 | 0 | return v5; |
2863 | 0 | } |
2864 | 0 | let v2 = constructor_xmm_unary_rm_r_unaligned(ctx, &SseOpcode::Movdqu, arg0); |
2865 | 0 | // Rule at src/isa/x64/inst.isle line 2006. |
2866 | 0 | return v2; |
2867 | 0 | } |
2868 | | |
2869 | | // Generated as internal constructor for term x64_movdqu_store. |
2870 | 0 | pub fn constructor_x64_movdqu_store<C: Context>( |
2871 | 0 | ctx: &mut C, |
2872 | 0 | arg0: &SyntheticAmode, |
2873 | 0 | arg1: Xmm, |
2874 | 0 | ) -> SideEffectNoResult { |
2875 | 0 | let v4 = C::use_avx_simd(ctx); |
2876 | 0 | if v4 == true { |
2877 | 0 | let v6 = &constructor_xmm_movrm_vex(ctx, &AvxOpcode::Vmovdqu, arg0, arg1); |
2878 | 0 | // Rule at src/isa/x64/inst.isle line 2015. |
2879 | 0 | return v6.clone(); |
2880 | 0 | } |
2881 | 0 | let v3 = &constructor_xmm_movrm(ctx, &SseOpcode::Movdqu, arg0, arg1); |
2882 | 0 | // Rule at src/isa/x64/inst.isle line 2013. |
2883 | 0 | return v3.clone(); |
2884 | 0 | } |
2885 | | |
2886 | | // Generated as internal constructor for term x64_pmovsxbw. |
2887 | 0 | pub fn constructor_x64_pmovsxbw<C: Context>( |
2888 | 0 | ctx: &mut C, |
2889 | 0 | arg0: &XmmMem, |
2890 | 0 | ) -> Xmm { |
2891 | 0 | let v3 = C::use_avx_simd(ctx); |
2892 | 0 | if v3 == true { |
2893 | 0 | let v5 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vpmovsxbw, arg0); |
2894 | 0 | // Rule at src/isa/x64/inst.isle line 2022. |
2895 | 0 | return v5; |
2896 | 0 | } |
2897 | 0 | let v2 = constructor_xmm_unary_rm_r_unaligned(ctx, &SseOpcode::Pmovsxbw, arg0); |
2898 | 0 | // Rule at src/isa/x64/inst.isle line 2020. |
2899 | 0 | return v2; |
2900 | 0 | } |
2901 | | |
2902 | | // Generated as internal constructor for term x64_pmovzxbw. |
2903 | 0 | pub fn constructor_x64_pmovzxbw<C: Context>( |
2904 | 0 | ctx: &mut C, |
2905 | 0 | arg0: &XmmMem, |
2906 | 0 | ) -> Xmm { |
2907 | 0 | let v3 = C::use_avx_simd(ctx); |
2908 | 0 | if v3 == true { |
2909 | 0 | let v5 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vpmovzxbw, arg0); |
2910 | 0 | // Rule at src/isa/x64/inst.isle line 2029. |
2911 | 0 | return v5; |
2912 | 0 | } |
2913 | 0 | let v2 = constructor_xmm_unary_rm_r_unaligned(ctx, &SseOpcode::Pmovzxbw, arg0); |
2914 | 0 | // Rule at src/isa/x64/inst.isle line 2027. |
2915 | 0 | return v2; |
2916 | 0 | } |
2917 | | |
2918 | | // Generated as internal constructor for term x64_pmovsxwd. |
2919 | 0 | pub fn constructor_x64_pmovsxwd<C: Context>( |
2920 | 0 | ctx: &mut C, |
2921 | 0 | arg0: &XmmMem, |
2922 | 0 | ) -> Xmm { |
2923 | 0 | let v3 = C::use_avx_simd(ctx); |
2924 | 0 | if v3 == true { |
2925 | 0 | let v5 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vpmovsxwd, arg0); |
2926 | 0 | // Rule at src/isa/x64/inst.isle line 2036. |
2927 | 0 | return v5; |
2928 | 0 | } |
2929 | 0 | let v2 = constructor_xmm_unary_rm_r_unaligned(ctx, &SseOpcode::Pmovsxwd, arg0); |
2930 | 0 | // Rule at src/isa/x64/inst.isle line 2034. |
2931 | 0 | return v2; |
2932 | 0 | } |
2933 | | |
2934 | | // Generated as internal constructor for term x64_pmovzxwd. |
2935 | 0 | pub fn constructor_x64_pmovzxwd<C: Context>( |
2936 | 0 | ctx: &mut C, |
2937 | 0 | arg0: &XmmMem, |
2938 | 0 | ) -> Xmm { |
2939 | 0 | let v3 = C::use_avx_simd(ctx); |
2940 | 0 | if v3 == true { |
2941 | 0 | let v5 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vpmovzxwd, arg0); |
2942 | 0 | // Rule at src/isa/x64/inst.isle line 2043. |
2943 | 0 | return v5; |
2944 | 0 | } |
2945 | 0 | let v2 = constructor_xmm_unary_rm_r_unaligned(ctx, &SseOpcode::Pmovzxwd, arg0); |
2946 | 0 | // Rule at src/isa/x64/inst.isle line 2041. |
2947 | 0 | return v2; |
2948 | 0 | } |
2949 | | |
2950 | | // Generated as internal constructor for term x64_pmovsxdq. |
2951 | 0 | pub fn constructor_x64_pmovsxdq<C: Context>( |
2952 | 0 | ctx: &mut C, |
2953 | 0 | arg0: &XmmMem, |
2954 | 0 | ) -> Xmm { |
2955 | 0 | let v3 = C::use_avx_simd(ctx); |
2956 | 0 | if v3 == true { |
2957 | 0 | let v5 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vpmovsxdq, arg0); |
2958 | 0 | // Rule at src/isa/x64/inst.isle line 2050. |
2959 | 0 | return v5; |
2960 | 0 | } |
2961 | 0 | let v2 = constructor_xmm_unary_rm_r_unaligned(ctx, &SseOpcode::Pmovsxdq, arg0); |
2962 | 0 | // Rule at src/isa/x64/inst.isle line 2048. |
2963 | 0 | return v2; |
2964 | 0 | } |
2965 | | |
2966 | | // Generated as internal constructor for term x64_pmovzxdq. |
2967 | 0 | pub fn constructor_x64_pmovzxdq<C: Context>( |
2968 | 0 | ctx: &mut C, |
2969 | 0 | arg0: &XmmMem, |
2970 | 0 | ) -> Xmm { |
2971 | 0 | let v3 = C::use_avx_simd(ctx); |
2972 | 0 | if v3 == true { |
2973 | 0 | let v5 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vpmovzxdq, arg0); |
2974 | 0 | // Rule at src/isa/x64/inst.isle line 2057. |
2975 | 0 | return v5; |
2976 | 0 | } |
2977 | 0 | let v2 = constructor_xmm_unary_rm_r_unaligned(ctx, &SseOpcode::Pmovzxdq, arg0); |
2978 | 0 | // Rule at src/isa/x64/inst.isle line 2055. |
2979 | 0 | return v2; |
2980 | 0 | } |
2981 | | |
2982 | | // Generated as internal constructor for term x64_movrm. |
2983 | 363k | pub fn constructor_x64_movrm<C: Context>( |
2984 | 363k | ctx: &mut C, |
2985 | 363k | arg0: Type, |
2986 | 363k | arg1: &SyntheticAmode, |
2987 | 363k | arg2: Gpr, |
2988 | 363k | ) -> SideEffectNoResult { |
2989 | 363k | let v3 = &C::raw_operand_size_of_type(ctx, arg0); |
2990 | 363k | let v4 = MInst::MovRM { |
2991 | 363k | size: v3.clone(), |
2992 | 363k | src: arg2, |
2993 | 363k | dst: arg1.clone(), |
2994 | 363k | }; |
2995 | 363k | let v5 = SideEffectNoResult::Inst { |
2996 | 363k | inst: v4, |
2997 | 363k | }; |
2998 | 363k | // Rule at src/isa/x64/inst.isle line 2062. |
2999 | 363k | return v5; |
3000 | 363k | } |
3001 | | |
3002 | | // Generated as internal constructor for term xmm_movrm. |
3003 | 1 | pub fn constructor_xmm_movrm<C: Context>( |
3004 | 1 | ctx: &mut C, |
3005 | 1 | arg0: &SseOpcode, |
3006 | 1 | arg1: &SyntheticAmode, |
3007 | 1 | arg2: Xmm, |
3008 | 1 | ) -> SideEffectNoResult { |
3009 | 1 | let v3 = MInst::XmmMovRM { |
3010 | 1 | op: arg0.clone(), |
3011 | 1 | src: arg2, |
3012 | 1 | dst: arg1.clone(), |
3013 | 1 | }; |
3014 | 1 | let v4 = SideEffectNoResult::Inst { |
3015 | 1 | inst: v3, |
3016 | 1 | }; |
3017 | 1 | // Rule at src/isa/x64/inst.isle line 2067. |
3018 | 1 | return v4; |
3019 | 1 | } |
3020 | | |
3021 | | // Generated as internal constructor for term xmm_movrm_imm. |
3022 | 0 | pub fn constructor_xmm_movrm_imm<C: Context>( |
3023 | 0 | ctx: &mut C, |
3024 | 0 | arg0: &SseOpcode, |
3025 | 0 | arg1: &SyntheticAmode, |
3026 | 0 | arg2: Xmm, |
3027 | 0 | arg3: u8, |
3028 | 0 | ) -> SideEffectNoResult { |
3029 | 0 | let v4 = MInst::XmmMovRMImm { |
3030 | 0 | op: arg0.clone(), |
3031 | 0 | src: arg2, |
3032 | 0 | dst: arg1.clone(), |
3033 | 0 | imm: arg3, |
3034 | 0 | }; |
3035 | 0 | let v5 = SideEffectNoResult::Inst { |
3036 | 0 | inst: v4, |
3037 | 0 | }; |
3038 | 0 | // Rule at src/isa/x64/inst.isle line 2071. |
3039 | 0 | return v5; |
3040 | 0 | } |
3041 | | |
3042 | | // Generated as internal constructor for term xmm_movrm_vex. |
3043 | 0 | pub fn constructor_xmm_movrm_vex<C: Context>( |
3044 | 0 | ctx: &mut C, |
3045 | 0 | arg0: &AvxOpcode, |
3046 | 0 | arg1: &SyntheticAmode, |
3047 | 0 | arg2: Xmm, |
3048 | 0 | ) -> SideEffectNoResult { |
3049 | 0 | let v3 = MInst::XmmMovRMVex { |
3050 | 0 | op: arg0.clone(), |
3051 | 0 | src: arg2, |
3052 | 0 | dst: arg1.clone(), |
3053 | 0 | }; |
3054 | 0 | let v4 = SideEffectNoResult::Inst { |
3055 | 0 | inst: v3, |
3056 | 0 | }; |
3057 | 0 | // Rule at src/isa/x64/inst.isle line 2075. |
3058 | 0 | return v4; |
3059 | 0 | } |
3060 | | |
3061 | | // Generated as internal constructor for term xmm_movrm_imm_vex. |
3062 | 0 | pub fn constructor_xmm_movrm_imm_vex<C: Context>( |
3063 | 0 | ctx: &mut C, |
3064 | 0 | arg0: &AvxOpcode, |
3065 | 0 | arg1: &SyntheticAmode, |
3066 | 0 | arg2: Xmm, |
3067 | 0 | arg3: u8, |
3068 | 0 | ) -> SideEffectNoResult { |
3069 | 0 | let v4 = MInst::XmmMovRMImmVex { |
3070 | 0 | op: arg0.clone(), |
3071 | 0 | src: arg2, |
3072 | 0 | dst: arg1.clone(), |
3073 | 0 | imm: arg3, |
3074 | 0 | }; |
3075 | 0 | let v5 = SideEffectNoResult::Inst { |
3076 | 0 | inst: v4, |
3077 | 0 | }; |
3078 | 0 | // Rule at src/isa/x64/inst.isle line 2079. |
3079 | 0 | return v5; |
3080 | 0 | } |
3081 | | |
3082 | | // Generated as internal constructor for term x64_xmm_load_const. |
3083 | 0 | pub fn constructor_x64_xmm_load_const<C: Context>( |
3084 | 0 | ctx: &mut C, |
3085 | 0 | arg0: Type, |
3086 | 0 | arg1: VCodeConstant, |
3087 | 0 | ) -> Xmm { |
3088 | 0 | let v2 = &C::const_to_synthetic_amode(ctx, arg1); |
3089 | 0 | let v4 = constructor_x64_load(ctx, arg0, v2, &ExtKind::None); |
3090 | 0 | let v5 = C::xmm_new(ctx, v4); |
3091 | 0 | // Rule at src/isa/x64/inst.isle line 2084. |
3092 | 0 | return v5; |
3093 | 0 | } |
3094 | | |
3095 | | // Generated as internal constructor for term alu_rmi_r. |
3096 | 110k | pub fn constructor_alu_rmi_r<C: Context>( |
3097 | 110k | ctx: &mut C, |
3098 | 110k | arg0: Type, |
3099 | 110k | arg1: &AluRmiROpcode, |
3100 | 110k | arg2: Gpr, |
3101 | 110k | arg3: &GprMemImm, |
3102 | 110k | ) -> Gpr { |
3103 | 110k | let v4 = C::temp_writable_gpr(ctx); |
3104 | 110k | let v5 = &C::operand_size_of_type_32_64(ctx, arg0); |
3105 | 110k | let v6 = MInst::AluRmiR { |
3106 | 110k | size: v5.clone(), |
3107 | 110k | op: arg1.clone(), |
3108 | 110k | src1: arg2, |
3109 | 110k | src2: arg3.clone(), |
3110 | 110k | dst: v4, |
3111 | 110k | }; |
3112 | 110k | let v7 = C::emit(ctx, &v6); |
3113 | 110k | let v8 = C::writable_gpr_to_gpr(ctx, v4); |
3114 | 110k | // Rule at src/isa/x64/inst.isle line 2095. |
3115 | 110k | return v8; |
3116 | 110k | } |
3117 | | |
3118 | | // Generated as internal constructor for term x64_add. |
3119 | 5.99k | pub fn constructor_x64_add<C: Context>( |
3120 | 5.99k | ctx: &mut C, |
3121 | 5.99k | arg0: Type, |
3122 | 5.99k | arg1: Gpr, |
3123 | 5.99k | arg2: &GprMemImm, |
3124 | 5.99k | ) -> Gpr { |
3125 | 5.99k | let v4 = constructor_alu_rmi_r(ctx, arg0, &AluRmiROpcode::Add, arg1, arg2); |
3126 | 5.99k | // Rule at src/isa/x64/inst.isle line 2103. |
3127 | 5.99k | return v4; |
3128 | 5.99k | } |
3129 | | |
3130 | | // Generated as internal constructor for term x64_add_with_flags_paired. |
3131 | 0 | pub fn constructor_x64_add_with_flags_paired<C: Context>( |
3132 | 0 | ctx: &mut C, |
3133 | 0 | arg0: Type, |
3134 | 0 | arg1: Gpr, |
3135 | 0 | arg2: &GprMemImm, |
3136 | 0 | ) -> ProducesFlags { |
3137 | 0 | let v3 = C::temp_writable_gpr(ctx); |
3138 | 0 | let v4 = &C::operand_size_of_type_32_64(ctx, arg0); |
3139 | 0 | let v7 = constructor_writable_gpr_to_r_reg(ctx, v3); |
3140 | 0 | let v6 = MInst::AluRmiR { |
3141 | 0 | size: v4.clone(), |
3142 | 0 | op: AluRmiROpcode::Add, |
3143 | 0 | src1: arg1, |
3144 | 0 | src2: arg2.clone(), |
3145 | 0 | dst: v3, |
3146 | 0 | }; |
3147 | 0 | let v8 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer { |
3148 | 0 | inst: v6, |
3149 | 0 | result: v7, |
3150 | 0 | }; |
3151 | 0 | // Rule at src/isa/x64/inst.isle line 2111. |
3152 | 0 | return v8; |
3153 | 0 | } |
3154 | | |
3155 | | // Generated as internal constructor for term x64_adc_paired. |
3156 | 0 | pub fn constructor_x64_adc_paired<C: Context>( |
3157 | 0 | ctx: &mut C, |
3158 | 0 | arg0: Type, |
3159 | 0 | arg1: Gpr, |
3160 | 0 | arg2: &GprMemImm, |
3161 | 0 | ) -> ConsumesFlags { |
3162 | 0 | let v3 = C::temp_writable_gpr(ctx); |
3163 | 0 | let v4 = &C::operand_size_of_type_32_64(ctx, arg0); |
3164 | 0 | let v7 = constructor_writable_gpr_to_r_reg(ctx, v3); |
3165 | 0 | let v6 = MInst::AluRmiR { |
3166 | 0 | size: v4.clone(), |
3167 | 0 | op: AluRmiROpcode::Adc, |
3168 | 0 | src1: arg1, |
3169 | 0 | src2: arg2.clone(), |
3170 | 0 | dst: v3, |
3171 | 0 | }; |
3172 | 0 | let v8 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer { |
3173 | 0 | inst: v6, |
3174 | 0 | result: v7, |
3175 | 0 | }; |
3176 | 0 | // Rule at src/isa/x64/inst.isle line 2123. |
3177 | 0 | return v8; |
3178 | 0 | } |
3179 | | |
3180 | | // Generated as internal constructor for term x64_sub. |
3181 | 32.2k | pub fn constructor_x64_sub<C: Context>( |
3182 | 32.2k | ctx: &mut C, |
3183 | 32.2k | arg0: Type, |
3184 | 32.2k | arg1: Gpr, |
3185 | 32.2k | arg2: &GprMemImm, |
3186 | 32.2k | ) -> Gpr { |
3187 | 32.2k | let v4 = constructor_alu_rmi_r(ctx, arg0, &AluRmiROpcode::Sub, arg1, arg2); |
3188 | 32.2k | // Rule at src/isa/x64/inst.isle line 2135. |
3189 | 32.2k | return v4; |
3190 | 32.2k | } |
3191 | | |
3192 | | // Generated as internal constructor for term x64_sub_with_flags_paired. |
3193 | 0 | pub fn constructor_x64_sub_with_flags_paired<C: Context>( |
3194 | 0 | ctx: &mut C, |
3195 | 0 | arg0: Type, |
3196 | 0 | arg1: Gpr, |
3197 | 0 | arg2: &GprMemImm, |
3198 | 0 | ) -> ProducesFlags { |
3199 | 0 | let v3 = C::temp_writable_gpr(ctx); |
3200 | 0 | let v4 = &C::operand_size_of_type_32_64(ctx, arg0); |
3201 | 0 | let v7 = constructor_writable_gpr_to_r_reg(ctx, v3); |
3202 | 0 | let v6 = MInst::AluRmiR { |
3203 | 0 | size: v4.clone(), |
3204 | 0 | op: AluRmiROpcode::Sub, |
3205 | 0 | src1: arg1, |
3206 | 0 | src2: arg2.clone(), |
3207 | 0 | dst: v3, |
3208 | 0 | }; |
3209 | 0 | let v8 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer { |
3210 | 0 | inst: v6, |
3211 | 0 | result: v7, |
3212 | 0 | }; |
3213 | 0 | // Rule at src/isa/x64/inst.isle line 2143. |
3214 | 0 | return v8; |
3215 | 0 | } |
3216 | | |
3217 | | // Generated as internal constructor for term x64_sbb_paired. |
3218 | 0 | pub fn constructor_x64_sbb_paired<C: Context>( |
3219 | 0 | ctx: &mut C, |
3220 | 0 | arg0: Type, |
3221 | 0 | arg1: Gpr, |
3222 | 0 | arg2: &GprMemImm, |
3223 | 0 | ) -> ConsumesFlags { |
3224 | 0 | let v3 = C::temp_writable_gpr(ctx); |
3225 | 0 | let v4 = &C::operand_size_of_type_32_64(ctx, arg0); |
3226 | 0 | let v7 = constructor_writable_gpr_to_r_reg(ctx, v3); |
3227 | 0 | let v6 = MInst::AluRmiR { |
3228 | 0 | size: v4.clone(), |
3229 | 0 | op: AluRmiROpcode::Sbb, |
3230 | 0 | src1: arg1, |
3231 | 0 | src2: arg2.clone(), |
3232 | 0 | dst: v3, |
3233 | 0 | }; |
3234 | 0 | let v8 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer { |
3235 | 0 | inst: v6, |
3236 | 0 | result: v7, |
3237 | 0 | }; |
3238 | 0 | // Rule at src/isa/x64/inst.isle line 2155. |
3239 | 0 | return v8; |
3240 | 0 | } |
3241 | | |
3242 | | // Generated as internal constructor for term x64_mul. |
3243 | 20.4k | pub fn constructor_x64_mul<C: Context>( |
3244 | 20.4k | ctx: &mut C, |
3245 | 20.4k | arg0: Type, |
3246 | 20.4k | arg1: Gpr, |
3247 | 20.4k | arg2: &GprMemImm, |
3248 | 20.4k | ) -> Gpr { |
3249 | 20.4k | let v4 = constructor_alu_rmi_r(ctx, arg0, &AluRmiROpcode::Mul, arg1, arg2); |
3250 | 20.4k | // Rule at src/isa/x64/inst.isle line 2167. |
3251 | 20.4k | return v4; |
3252 | 20.4k | } |
3253 | | |
3254 | | // Generated as internal constructor for term x64_and. |
3255 | 42.3k | pub fn constructor_x64_and<C: Context>( |
3256 | 42.3k | ctx: &mut C, |
3257 | 42.3k | arg0: Type, |
3258 | 42.3k | arg1: Gpr, |
3259 | 42.3k | arg2: &GprMemImm, |
3260 | 42.3k | ) -> Gpr { |
3261 | 42.3k | let v4 = constructor_alu_rmi_r(ctx, arg0, &AluRmiROpcode::And, arg1, arg2); |
3262 | 42.3k | // Rule at src/isa/x64/inst.isle line 2175. |
3263 | 42.3k | return v4; |
3264 | 42.3k | } |
3265 | | |
3266 | | // Generated as internal constructor for term x64_and_with_flags_paired. |
3267 | 0 | pub fn constructor_x64_and_with_flags_paired<C: Context>( |
3268 | 0 | ctx: &mut C, |
3269 | 0 | arg0: Type, |
3270 | 0 | arg1: Gpr, |
3271 | 0 | arg2: &GprMemImm, |
3272 | 0 | ) -> ProducesFlags { |
3273 | 0 | let v3 = C::temp_writable_gpr(ctx); |
3274 | 0 | let v4 = &C::operand_size_of_type_32_64(ctx, arg0); |
3275 | 0 | let v6 = MInst::AluRmiR { |
3276 | 0 | size: v4.clone(), |
3277 | 0 | op: AluRmiROpcode::And, |
3278 | 0 | src1: arg1, |
3279 | 0 | src2: arg2.clone(), |
3280 | 0 | dst: v3, |
3281 | 0 | }; |
3282 | 0 | let v7 = ProducesFlags::ProducesFlagsSideEffect { |
3283 | 0 | inst: v6, |
3284 | 0 | }; |
3285 | 0 | // Rule at src/isa/x64/inst.isle line 2182. |
3286 | 0 | return v7; |
3287 | 0 | } |
3288 | | |
3289 | | // Generated as internal constructor for term x64_or. |
3290 | 7.66k | pub fn constructor_x64_or<C: Context>( |
3291 | 7.66k | ctx: &mut C, |
3292 | 7.66k | arg0: Type, |
3293 | 7.66k | arg1: Gpr, |
3294 | 7.66k | arg2: &GprMemImm, |
3295 | 7.66k | ) -> Gpr { |
3296 | 7.66k | let v4 = constructor_alu_rmi_r(ctx, arg0, &AluRmiROpcode::Or, arg1, arg2); |
3297 | 7.66k | // Rule at src/isa/x64/inst.isle line 2193. |
3298 | 7.66k | return v4; |
3299 | 7.66k | } |
3300 | | |
3301 | | // Generated as internal constructor for term x64_xor. |
3302 | 1.91k | pub fn constructor_x64_xor<C: Context>( |
3303 | 1.91k | ctx: &mut C, |
3304 | 1.91k | arg0: Type, |
3305 | 1.91k | arg1: Gpr, |
3306 | 1.91k | arg2: &GprMemImm, |
3307 | 1.91k | ) -> Gpr { |
3308 | 1.91k | let v4 = constructor_alu_rmi_r(ctx, arg0, &AluRmiROpcode::Xor, arg1, arg2); |
3309 | 1.91k | // Rule at src/isa/x64/inst.isle line 2201. |
3310 | 1.91k | return v4; |
3311 | 1.91k | } |
3312 | | |
3313 | | // Generated as internal constructor for term alu_rm_r_vex. |
3314 | 149 | pub fn constructor_alu_rm_r_vex<C: Context>( |
3315 | 149 | ctx: &mut C, |
3316 | 149 | arg0: Type, |
3317 | 149 | arg1: &AluRmROpcode, |
3318 | 149 | arg2: Gpr, |
3319 | 149 | arg3: Gpr, |
3320 | 149 | ) -> Gpr { |
3321 | 149 | let v4 = C::temp_writable_gpr(ctx); |
3322 | 149 | let v5 = &C::operand_size_of_type_32_64(ctx, arg0); |
3323 | 149 | let v6 = MInst::AluRmRVex { |
3324 | 149 | size: v5.clone(), |
3325 | 149 | op: arg1.clone(), |
3326 | 149 | src1: arg2, |
3327 | 149 | src2: arg3, |
3328 | 149 | dst: v4, |
3329 | 149 | }; |
3330 | 149 | let v7 = C::emit(ctx, &v6); |
3331 | 149 | let v8 = C::writable_gpr_to_gpr(ctx, v4); |
3332 | 149 | // Rule at src/isa/x64/inst.isle line 2209. |
3333 | 149 | return v8; |
3334 | 149 | } |
3335 | | |
3336 | | // Generated as internal constructor for term x64_andn. |
3337 | 149 | pub fn constructor_x64_andn<C: Context>( |
3338 | 149 | ctx: &mut C, |
3339 | 149 | arg0: Type, |
3340 | 149 | arg1: Gpr, |
3341 | 149 | arg2: Gpr, |
3342 | 149 | ) -> Gpr { |
3343 | 149 | let v4 = constructor_alu_rm_r_vex(ctx, arg0, &AluRmROpcode::Andn, arg1, arg2); |
3344 | 149 | // Rule at src/isa/x64/inst.isle line 2216. |
3345 | 149 | return v4; |
3346 | 149 | } |
3347 | | |
3348 | | // Generated as internal constructor for term imm_i64. |
3349 | 0 | pub fn constructor_imm_i64<C: Context>( |
3350 | 0 | ctx: &mut C, |
3351 | 0 | arg0: Type, |
3352 | 0 | arg1: i64, |
3353 | 0 | ) -> Reg { |
3354 | 0 | let v2 = C::i64_as_u64(ctx, arg1); |
3355 | 0 | let v3 = constructor_imm(ctx, arg0, v2); |
3356 | 0 | // Rule at src/isa/x64/inst.isle line 2223. |
3357 | 0 | return v3; |
3358 | 0 | } |
3359 | | |
3360 | | // Generated as internal constructor for term imm. |
3361 | 396k | pub fn constructor_imm<C: Context>( |
3362 | 396k | ctx: &mut C, |
3363 | 396k | arg0: Type, |
3364 | 396k | arg1: u64, |
3365 | 396k | ) -> Reg { |
3366 | 396k | match arg0 { |
3367 | | I64 => { |
3368 | 42.8k | let v20 = C::nonzero_u64_fits_in_u32(ctx, arg1); |
3369 | 42.8k | if let Some(v2110.5k ) = v20 { |
3370 | 10.5k | let v5 = C::temp_writable_gpr(ctx); |
3371 | 10.5k | let v23 = MInst::Imm { |
3372 | 10.5k | dst_size: OperandSize::Size32, |
3373 | 10.5k | simm64: v21, |
3374 | 10.5k | dst: v5, |
3375 | 10.5k | }; |
3376 | 10.5k | let v24 = C::emit(ctx, &v23); |
3377 | 10.5k | let v25 = constructor_writable_gpr_to_r_reg(ctx, v5); |
3378 | 10.5k | // Rule at src/isa/x64/inst.isle line 2254. |
3379 | 10.5k | return v25; |
3380 | 32.3k | } |
3381 | | } |
3382 | | F32 => { |
3383 | 0 | let v4 = C::u64_is_zero(ctx, arg1); |
3384 | 0 | match v4 { |
3385 | | true => { |
3386 | 0 | let v35 = constructor_xmm_zero(ctx, arg0); |
3387 | 0 | let v36 = C::xmm_to_reg(ctx, v35); |
3388 | 0 | // Rule at src/isa/x64/inst.isle line 2272. |
3389 | 0 | return v36; |
3390 | | } |
3391 | | false => { |
3392 | 0 | let v11 = constructor_imm(ctx, I32, arg1); |
3393 | 0 | let v12 = &C::reg_to_gpr_mem(ctx, v11); |
3394 | 0 | let v13 = constructor_x64_movd_to_xmm(ctx, v12); |
3395 | 0 | let v14 = C::xmm_to_reg(ctx, v13); |
3396 | 0 | // Rule at src/isa/x64/inst.isle line 2245. |
3397 | 0 | return v14; |
3398 | | } |
3399 | | _ => {} |
3400 | | } |
3401 | | } |
3402 | | F64 => { |
3403 | 0 | let v4 = C::u64_is_zero(ctx, arg1); |
3404 | 0 | match v4 { |
3405 | | true => { |
3406 | 0 | let v35 = constructor_xmm_zero(ctx, arg0); |
3407 | 0 | let v36 = C::xmm_to_reg(ctx, v35); |
3408 | 0 | // Rule at src/isa/x64/inst.isle line 2277. |
3409 | 0 | return v36; |
3410 | | } |
3411 | | false => { |
3412 | 0 | let v16 = constructor_imm(ctx, I64, arg1); |
3413 | 0 | let v17 = &C::reg_to_gpr_mem(ctx, v16); |
3414 | 0 | let v18 = constructor_x64_movq_to_xmm(ctx, v17); |
3415 | 0 | let v19 = C::xmm_to_reg(ctx, v18); |
3416 | 0 | // Rule at src/isa/x64/inst.isle line 2249. |
3417 | 0 | return v19; |
3418 | | } |
3419 | | _ => {} |
3420 | | } |
3421 | | } |
3422 | 353k | _ => {} |
3423 | | } |
3424 | 385k | let v1 = C::fits_in_64(ctx, arg0); |
3425 | 385k | if let Some(v2) = v1 { |
3426 | 385k | let v4 = C::u64_is_zero(ctx, arg1); |
3427 | 385k | match v4 { |
3428 | | true => { |
3429 | 65.9k | let v5 = C::temp_writable_gpr(ctx); |
3430 | 65.9k | let v6 = &C::operand_size_of_type_32_64(ctx, v2); |
3431 | 65.9k | let v27 = MInst::AluConstOp { |
3432 | 65.9k | op: AluRmiROpcode::Xor, |
3433 | 65.9k | size: v6.clone(), |
3434 | 65.9k | dst: v5, |
3435 | 65.9k | }; |
3436 | 65.9k | let v28 = C::emit(ctx, &v27); |
3437 | 65.9k | let v29 = C::writable_gpr_to_gpr(ctx, v5); |
3438 | 65.9k | let v30 = C::gpr_to_reg(ctx, v29); |
3439 | 65.9k | // Rule at src/isa/x64/inst.isle line 2260. |
3440 | 65.9k | return v30; |
3441 | | } |
3442 | | false => { |
3443 | 319k | let v5 = C::temp_writable_gpr(ctx); |
3444 | 319k | let v6 = &C::operand_size_of_type_32_64(ctx, v2); |
3445 | 319k | let v7 = MInst::Imm { |
3446 | 319k | dst_size: v6.clone(), |
3447 | 319k | simm64: arg1, |
3448 | 319k | dst: v5, |
3449 | 319k | }; |
3450 | 319k | let v8 = C::emit(ctx, &v7); |
3451 | 319k | let v9 = constructor_writable_gpr_to_r_reg(ctx, v5); |
3452 | 319k | // Rule at src/isa/x64/inst.isle line 2238. |
3453 | 319k | return v9; |
3454 | | } |
3455 | | _ => {} |
3456 | | } |
3457 | 0 | } |
3458 | 0 | if arg1 == 0x0 { |
3459 | 0 | let v31 = C::multi_lane(ctx, arg0); |
3460 | 0 | if let Some(v32) = v31 { |
3461 | 0 | let v35 = constructor_xmm_zero(ctx, arg0); |
3462 | 0 | let v36 = C::xmm_to_reg(ctx, v35); |
3463 | 0 | // Rule at src/isa/x64/inst.isle line 2268. |
3464 | 0 | return v36; |
3465 | 0 | } |
3466 | 0 | } |
3467 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "imm", "src/isa/x64/inst.isle line 2235") |
3468 | 396k | } |
3469 | | |
3470 | | // Generated as internal constructor for term xmm_zero. |
3471 | 0 | pub fn constructor_xmm_zero<C: Context>( |
3472 | 0 | ctx: &mut C, |
3473 | 0 | arg0: Type, |
3474 | 0 | ) -> Xmm { |
3475 | 0 | let v1 = constructor_xmm_uninit_value(ctx); |
3476 | 0 | let v2 = &C::xmm_to_xmm_mem(ctx, v1); |
3477 | 0 | let v3 = constructor_x64_xor_vector(ctx, arg0, v1, v2); |
3478 | 0 | // Rule at src/isa/x64/inst.isle line 2282. |
3479 | 0 | return v3; |
3480 | 0 | } |
3481 | | |
3482 | | // Generated as internal constructor for term shift_r. |
3483 | 15.7k | pub fn constructor_shift_r<C: Context>( |
3484 | 15.7k | ctx: &mut C, |
3485 | 15.7k | arg0: Type, |
3486 | 15.7k | arg1: &ShiftKind, |
3487 | 15.7k | arg2: Gpr, |
3488 | 15.7k | arg3: &Imm8Gpr, |
3489 | 15.7k | ) -> Gpr { |
3490 | 15.7k | let v4 = C::temp_writable_gpr(ctx); |
3491 | 15.7k | let v5 = &C::raw_operand_size_of_type(ctx, arg0); |
3492 | 15.7k | let v6 = MInst::ShiftR { |
3493 | 15.7k | size: v5.clone(), |
3494 | 15.7k | kind: arg1.clone(), |
3495 | 15.7k | src: arg2, |
3496 | 15.7k | num_bits: arg3.clone(), |
3497 | 15.7k | dst: v4, |
3498 | 15.7k | }; |
3499 | 15.7k | let v7 = C::emit(ctx, &v6); |
3500 | 15.7k | let v8 = C::writable_gpr_to_gpr(ctx, v4); |
3501 | 15.7k | // Rule at src/isa/x64/inst.isle line 2288. |
3502 | 15.7k | return v8; |
3503 | 15.7k | } |
3504 | | |
3505 | | // Generated as internal constructor for term x64_rotl. |
3506 | 687 | pub fn constructor_x64_rotl<C: Context>( |
3507 | 687 | ctx: &mut C, |
3508 | 687 | arg0: Type, |
3509 | 687 | arg1: Gpr, |
3510 | 687 | arg2: &Imm8Gpr, |
3511 | 687 | ) -> Gpr { |
3512 | 687 | let v4 = constructor_shift_r(ctx, arg0, &ShiftKind::RotateLeft, arg1, arg2); |
3513 | 687 | // Rule at src/isa/x64/inst.isle line 2298. |
3514 | 687 | return v4; |
3515 | 687 | } |
3516 | | |
3517 | | // Generated as internal constructor for term x64_rotr. |
3518 | 1 | pub fn constructor_x64_rotr<C: Context>( |
3519 | 1 | ctx: &mut C, |
3520 | 1 | arg0: Type, |
3521 | 1 | arg1: Gpr, |
3522 | 1 | arg2: &Imm8Gpr, |
3523 | 1 | ) -> Gpr { |
3524 | 1 | let v4 = constructor_shift_r(ctx, arg0, &ShiftKind::RotateRight, arg1, arg2); |
3525 | 1 | // Rule at src/isa/x64/inst.isle line 2303. |
3526 | 1 | return v4; |
3527 | 1 | } |
3528 | | |
3529 | | // Generated as internal constructor for term x64_shl. |
3530 | 8.29k | pub fn constructor_x64_shl<C: Context>( |
3531 | 8.29k | ctx: &mut C, |
3532 | 8.29k | arg0: Type, |
3533 | 8.29k | arg1: Gpr, |
3534 | 8.29k | arg2: &Imm8Gpr, |
3535 | 8.29k | ) -> Gpr { |
3536 | 8.29k | let v4 = constructor_shift_r(ctx, arg0, &ShiftKind::ShiftLeft, arg1, arg2); |
3537 | 8.29k | // Rule at src/isa/x64/inst.isle line 2308. |
3538 | 8.29k | return v4; |
3539 | 8.29k | } |
3540 | | |
3541 | | // Generated as internal constructor for term x64_shr. |
3542 | 6.65k | pub fn constructor_x64_shr<C: Context>( |
3543 | 6.65k | ctx: &mut C, |
3544 | 6.65k | arg0: Type, |
3545 | 6.65k | arg1: Gpr, |
3546 | 6.65k | arg2: &Imm8Gpr, |
3547 | 6.65k | ) -> Gpr { |
3548 | 6.65k | let v4 = constructor_shift_r(ctx, arg0, &ShiftKind::ShiftRightLogical, arg1, arg2); |
3549 | 6.65k | // Rule at src/isa/x64/inst.isle line 2313. |
3550 | 6.65k | return v4; |
3551 | 6.65k | } |
3552 | | |
3553 | | // Generated as internal constructor for term x64_sar. |
3554 | 143 | pub fn constructor_x64_sar<C: Context>( |
3555 | 143 | ctx: &mut C, |
3556 | 143 | arg0: Type, |
3557 | 143 | arg1: Gpr, |
3558 | 143 | arg2: &Imm8Gpr, |
3559 | 143 | ) -> Gpr { |
3560 | 143 | let v4 = constructor_shift_r(ctx, arg0, &ShiftKind::ShiftRightArithmetic, arg1, arg2); |
3561 | 143 | // Rule at src/isa/x64/inst.isle line 2318. |
3562 | 143 | return v4; |
3563 | 143 | } |
3564 | | |
3565 | | // Generated as internal constructor for term x64_bswap. |
3566 | 0 | pub fn constructor_x64_bswap<C: Context>( |
3567 | 0 | ctx: &mut C, |
3568 | 0 | arg0: Type, |
3569 | 0 | arg1: Gpr, |
3570 | 0 | ) -> Gpr { |
3571 | 0 | let v2 = C::temp_writable_gpr(ctx); |
3572 | 0 | let v3 = &C::operand_size_of_type_32_64(ctx, arg0); |
3573 | 0 | let v4 = MInst::Bswap { |
3574 | 0 | size: v3.clone(), |
3575 | 0 | src: arg1, |
3576 | 0 | dst: v2, |
3577 | 0 | }; |
3578 | 0 | let v5 = C::emit(ctx, &v4); |
3579 | 0 | let v6 = C::writable_gpr_to_gpr(ctx, v2); |
3580 | 0 | // Rule at src/isa/x64/inst.isle line 2325. |
3581 | 0 | return v6; |
3582 | 0 | } |
3583 | | |
3584 | | // Generated as internal constructor for term cmp_rmi_r. |
3585 | 284k | pub fn constructor_cmp_rmi_r<C: Context>( |
3586 | 284k | ctx: &mut C, |
3587 | 284k | arg0: &OperandSize, |
3588 | 284k | arg1: &CmpOpcode, |
3589 | 284k | arg2: &GprMemImm, |
3590 | 284k | arg3: Gpr, |
3591 | 284k | ) -> ProducesFlags { |
3592 | 284k | let v4 = MInst::CmpRmiR { |
3593 | 284k | size: arg0.clone(), |
3594 | 284k | opcode: arg1.clone(), |
3595 | 284k | src: arg2.clone(), |
3596 | 284k | dst: arg3, |
3597 | 284k | }; |
3598 | 284k | let v5 = ProducesFlags::ProducesFlagsSideEffect { |
3599 | 284k | inst: v4, |
3600 | 284k | }; |
3601 | 284k | // Rule at src/isa/x64/inst.isle line 2333. |
3602 | 284k | return v5; |
3603 | 284k | } |
3604 | | |
3605 | | // Generated as internal constructor for term x64_cmp. |
3606 | 155k | pub fn constructor_x64_cmp<C: Context>( |
3607 | 155k | ctx: &mut C, |
3608 | 155k | arg0: &OperandSize, |
3609 | 155k | arg1: &GprMemImm, |
3610 | 155k | arg2: Gpr, |
3611 | 155k | ) -> ProducesFlags { |
3612 | 155k | let v4 = &constructor_cmp_rmi_r(ctx, arg0, &CmpOpcode::Cmp, arg1, arg2); |
3613 | 155k | // Rule at src/isa/x64/inst.isle line 2342. |
3614 | 155k | return v4.clone(); |
3615 | 155k | } |
3616 | | |
3617 | | // Generated as internal constructor for term x64_cmp_imm. |
3618 | 0 | pub fn constructor_x64_cmp_imm<C: Context>( |
3619 | 0 | ctx: &mut C, |
3620 | 0 | arg0: &OperandSize, |
3621 | 0 | arg1: u32, |
3622 | 0 | arg2: Gpr, |
3623 | 0 | ) -> ProducesFlags { |
3624 | 0 | let v4 = RegMemImm::Imm { |
3625 | 0 | simm32: arg1, |
3626 | 0 | }; |
3627 | 0 | let v5 = &C::gpr_mem_imm_new(ctx, &v4); |
3628 | 0 | let v6 = &constructor_cmp_rmi_r(ctx, arg0, &CmpOpcode::Cmp, v5, arg2); |
3629 | 0 | // Rule at src/isa/x64/inst.isle line 2347. |
3630 | 0 | return v6.clone(); |
3631 | 0 | } |
3632 | | |
3633 | | // Generated as internal constructor for term xmm_cmp_rm_r. |
3634 | 0 | pub fn constructor_xmm_cmp_rm_r<C: Context>( |
3635 | 0 | ctx: &mut C, |
3636 | 0 | arg0: &SseOpcode, |
3637 | 0 | arg1: &XmmMemAligned, |
3638 | 0 | arg2: Xmm, |
3639 | 0 | ) -> ProducesFlags { |
3640 | 0 | let v3 = MInst::XmmCmpRmR { |
3641 | 0 | op: arg0.clone(), |
3642 | 0 | src: arg1.clone(), |
3643 | 0 | dst: arg2, |
3644 | 0 | }; |
3645 | 0 | let v4 = ProducesFlags::ProducesFlagsSideEffect { |
3646 | 0 | inst: v3, |
3647 | 0 | }; |
3648 | 0 | // Rule at src/isa/x64/inst.isle line 2352. |
3649 | 0 | return v4; |
3650 | 0 | } |
3651 | | |
3652 | | // Generated as internal constructor for term x64_ucomis. |
3653 | 0 | pub fn constructor_x64_ucomis<C: Context>( |
3654 | 0 | ctx: &mut C, |
3655 | 0 | arg0: Value, |
3656 | 0 | arg1: Value, |
3657 | 0 | ) -> ProducesFlags { |
3658 | 0 | let v1 = C::value_type(ctx, arg0); |
3659 | 0 | match v1 { |
3660 | | F32 => { |
3661 | 0 | let v4 = constructor_put_in_xmm(ctx, arg0); |
3662 | 0 | let v5 = &constructor_xmm_to_xmm_mem_aligned(ctx, v4); |
3663 | 0 | let v6 = constructor_put_in_xmm(ctx, arg1); |
3664 | 0 | let v7 = &constructor_xmm_cmp_rm_r(ctx, &SseOpcode::Ucomiss, v5, v6); |
3665 | 0 | // Rule at src/isa/x64/inst.isle line 2358. |
3666 | 0 | return v7.clone(); |
3667 | | } |
3668 | | F64 => { |
3669 | 0 | let v4 = constructor_put_in_xmm(ctx, arg0); |
3670 | 0 | let v5 = &constructor_xmm_to_xmm_mem_aligned(ctx, v4); |
3671 | 0 | let v6 = constructor_put_in_xmm(ctx, arg1); |
3672 | 0 | let v9 = &constructor_xmm_cmp_rm_r(ctx, &SseOpcode::Ucomisd, v5, v6); |
3673 | 0 | // Rule at src/isa/x64/inst.isle line 2362. |
3674 | 0 | return v9.clone(); |
3675 | | } |
3676 | 0 | _ => {} |
3677 | 0 | } |
3678 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "x64_ucomis", "src/isa/x64/inst.isle line 2357") |
3679 | 0 | } |
3680 | | |
3681 | | // Generated as internal constructor for term x64_test. |
3682 | 129k | pub fn constructor_x64_test<C: Context>( |
3683 | 129k | ctx: &mut C, |
3684 | 129k | arg0: &OperandSize, |
3685 | 129k | arg1: &GprMemImm, |
3686 | 129k | arg2: Gpr, |
3687 | 129k | ) -> ProducesFlags { |
3688 | 129k | let v4 = &constructor_cmp_rmi_r(ctx, arg0, &CmpOpcode::Test, arg1, arg2); |
3689 | 129k | // Rule at src/isa/x64/inst.isle line 2367. |
3690 | 129k | return v4.clone(); |
3691 | 129k | } |
3692 | | |
3693 | | // Generated as internal constructor for term x64_ptest. |
3694 | 0 | pub fn constructor_x64_ptest<C: Context>( |
3695 | 0 | ctx: &mut C, |
3696 | 0 | arg0: &XmmMem, |
3697 | 0 | arg1: Xmm, |
3698 | 0 | ) -> ProducesFlags { |
3699 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg0); |
3700 | 0 | let v4 = &constructor_xmm_cmp_rm_r(ctx, &SseOpcode::Ptest, v3, arg1); |
3701 | 0 | // Rule at src/isa/x64/inst.isle line 2372. |
3702 | 0 | return v4.clone(); |
3703 | 0 | } |
3704 | | |
3705 | | // Generated as internal constructor for term cmove. |
3706 | 43.0k | pub fn constructor_cmove<C: Context>( |
3707 | 43.0k | ctx: &mut C, |
3708 | 43.0k | arg0: Type, |
3709 | 43.0k | arg1: &CC, |
3710 | 43.0k | arg2: &GprMem, |
3711 | 43.0k | arg3: Gpr, |
3712 | 43.0k | ) -> ConsumesFlags { |
3713 | 43.0k | let v4 = C::temp_writable_gpr(ctx); |
3714 | 43.0k | let v5 = &C::operand_size_of_type_32_64(ctx, arg0); |
3715 | 43.0k | let v7 = constructor_writable_gpr_to_r_reg(ctx, v4); |
3716 | 43.0k | let v6 = MInst::Cmove { |
3717 | 43.0k | size: v5.clone(), |
3718 | 43.0k | cc: arg1.clone(), |
3719 | 43.0k | consequent: arg2.clone(), |
3720 | 43.0k | alternative: arg3, |
3721 | 43.0k | dst: v4, |
3722 | 43.0k | }; |
3723 | 43.0k | let v8 = ConsumesFlags::ConsumesFlagsReturnsReg { |
3724 | 43.0k | inst: v6, |
3725 | 43.0k | result: v7, |
3726 | 43.0k | }; |
3727 | 43.0k | // Rule at src/isa/x64/inst.isle line 2379. |
3728 | 43.0k | return v8; |
3729 | 43.0k | } |
3730 | | |
3731 | | // Generated as internal constructor for term cmove_xmm. |
3732 | 0 | pub fn constructor_cmove_xmm<C: Context>( |
3733 | 0 | ctx: &mut C, |
3734 | 0 | arg0: Type, |
3735 | 0 | arg1: &CC, |
3736 | 0 | arg2: &XmmMemAligned, |
3737 | 0 | arg3: Xmm, |
3738 | 0 | ) -> ConsumesFlags { |
3739 | 0 | let v4 = C::temp_writable_xmm(ctx); |
3740 | 0 | let v6 = constructor_writable_xmm_to_r_reg(ctx, v4); |
3741 | 0 | let v5 = MInst::XmmCmove { |
3742 | 0 | ty: arg0, |
3743 | 0 | cc: arg1.clone(), |
3744 | 0 | consequent: arg2.clone(), |
3745 | 0 | alternative: arg3, |
3746 | 0 | dst: v4, |
3747 | 0 | }; |
3748 | 0 | let v7 = ConsumesFlags::ConsumesFlagsReturnsReg { |
3749 | 0 | inst: v5, |
3750 | 0 | result: v6, |
3751 | 0 | }; |
3752 | 0 | // Rule at src/isa/x64/inst.isle line 2387. |
3753 | 0 | return v7; |
3754 | 0 | } |
3755 | | |
3756 | | // Generated as internal constructor for term cmove_from_values. |
3757 | 9.18k | pub fn constructor_cmove_from_values<C: Context>( |
3758 | 9.18k | ctx: &mut C, |
3759 | 9.18k | arg0: Type, |
3760 | 9.18k | arg1: &CC, |
3761 | 9.18k | arg2: Value, |
3762 | 9.18k | arg3: Value, |
3763 | 9.18k | ) -> ConsumesFlags { |
3764 | 9.18k | let v1 = &C::type_register_class(ctx, arg0); |
3765 | 9.18k | if let Some(v2) = v1 { |
3766 | 9.18k | match v2 { |
3767 | | &RegisterClass::Gpr { |
3768 | 9.18k | single_register: v3, |
3769 | 9.18k | } => { |
3770 | 9.18k | match v3 { |
3771 | | true => { |
3772 | 9.18k | let v26 = &constructor_put_in_gpr_mem(ctx, arg2); |
3773 | 9.18k | let v27 = constructor_put_in_gpr(ctx, arg3); |
3774 | 9.18k | let v28 = &constructor_cmove(ctx, arg0, arg1, v26, v27); |
3775 | 9.18k | // Rule at src/isa/x64/inst.isle line 2418. |
3776 | 9.18k | return v28.clone(); |
3777 | | } |
3778 | | false => { |
3779 | 0 | if arg0 == I128 { |
3780 | 0 | let v7 = C::put_in_regs(ctx, arg2); |
3781 | 0 | let v8 = C::put_in_regs(ctx, arg3); |
3782 | 0 | let v9 = C::temp_writable_gpr(ctx); |
3783 | 0 | let v10 = C::temp_writable_gpr(ctx); |
3784 | 0 | let v13 = constructor_value_regs_get_gpr(ctx, v7, 0x0); |
3785 | 0 | let v14 = &C::gpr_to_gpr_mem(ctx, v13); |
3786 | 0 | let v15 = constructor_value_regs_get_gpr(ctx, v8, 0x0); |
3787 | 0 | let v18 = constructor_value_regs_get_gpr(ctx, v7, 0x1); |
3788 | 0 | let v19 = &C::gpr_to_gpr_mem(ctx, v18); |
3789 | 0 | let v20 = constructor_value_regs_get_gpr(ctx, v8, 0x1); |
3790 | 0 | let v22 = constructor_writable_gpr_to_r_reg(ctx, v9); |
3791 | 0 | let v23 = constructor_writable_gpr_to_r_reg(ctx, v10); |
3792 | 0 | let v24 = C::value_regs(ctx, v22, v23); |
3793 | 0 | let v16 = MInst::Cmove { |
3794 | 0 | size: OperandSize::Size64, |
3795 | 0 | cc: arg1.clone(), |
3796 | 0 | consequent: v14.clone(), |
3797 | 0 | alternative: v15, |
3798 | 0 | dst: v9, |
3799 | 0 | }; |
3800 | 0 | let v21 = MInst::Cmove { |
3801 | 0 | size: OperandSize::Size64, |
3802 | 0 | cc: arg1.clone(), |
3803 | 0 | consequent: v19.clone(), |
3804 | 0 | alternative: v20, |
3805 | 0 | dst: v10, |
3806 | 0 | }; |
3807 | 0 | let v25 = ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs { |
3808 | 0 | inst1: v16, |
3809 | 0 | inst2: v21, |
3810 | 0 | result: v24, |
3811 | 0 | }; |
3812 | 0 | // Rule at src/isa/x64/inst.isle line 2397. |
3813 | 0 | return v25; |
3814 | 0 | } |
3815 | | } |
3816 | | _ => {} |
3817 | | } |
3818 | | } |
3819 | | &RegisterClass::Xmm => { |
3820 | 0 | let v29 = &constructor_put_in_xmm_mem_aligned(ctx, arg2); |
3821 | 0 | let v30 = constructor_put_in_xmm(ctx, arg3); |
3822 | 0 | let v31 = &constructor_cmove_xmm(ctx, arg0, arg1, v29, v30); |
3823 | 0 | // Rule at src/isa/x64/inst.isle line 2421. |
3824 | 0 | return v31.clone(); |
3825 | | } |
3826 | 0 | _ => {} |
3827 | | } |
3828 | 0 | } |
3829 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "cmove_from_values", "src/isa/x64/inst.isle line 2396") |
3830 | 9.18k | } |
3831 | | |
3832 | | // Generated as internal constructor for term cmove_or. |
3833 | 0 | pub fn constructor_cmove_or<C: Context>( |
3834 | 0 | ctx: &mut C, |
3835 | 0 | arg0: Type, |
3836 | 0 | arg1: &CC, |
3837 | 0 | arg2: &CC, |
3838 | 0 | arg3: &GprMem, |
3839 | 0 | arg4: Gpr, |
3840 | 0 | ) -> ConsumesFlags { |
3841 | 0 | let v5 = C::temp_writable_gpr(ctx); |
3842 | 0 | let v6 = C::temp_writable_gpr(ctx); |
3843 | 0 | let v7 = &C::operand_size_of_type_32_64(ctx, arg0); |
3844 | 0 | let v9 = C::writable_gpr_to_gpr(ctx, v6); |
3845 | 0 | let v11 = constructor_writable_gpr_to_value_regs(ctx, v5); |
3846 | 0 | let v8 = MInst::Cmove { |
3847 | 0 | size: v7.clone(), |
3848 | 0 | cc: arg1.clone(), |
3849 | 0 | consequent: arg3.clone(), |
3850 | 0 | alternative: arg4, |
3851 | 0 | dst: v6, |
3852 | 0 | }; |
3853 | 0 | let v10 = MInst::Cmove { |
3854 | 0 | size: v7.clone(), |
3855 | 0 | cc: arg2.clone(), |
3856 | 0 | consequent: arg3.clone(), |
3857 | 0 | alternative: v9, |
3858 | 0 | dst: v5, |
3859 | 0 | }; |
3860 | 0 | let v12 = ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs { |
3861 | 0 | inst1: v8, |
3862 | 0 | inst2: v10, |
3863 | 0 | result: v11, |
3864 | 0 | }; |
3865 | 0 | // Rule at src/isa/x64/inst.isle line 2428. |
3866 | 0 | return v12; |
3867 | 0 | } |
3868 | | |
3869 | | // Generated as internal constructor for term cmove_or_xmm. |
3870 | 0 | pub fn constructor_cmove_or_xmm<C: Context>( |
3871 | 0 | ctx: &mut C, |
3872 | 0 | arg0: Type, |
3873 | 0 | arg1: &CC, |
3874 | 0 | arg2: &CC, |
3875 | 0 | arg3: &XmmMemAligned, |
3876 | 0 | arg4: Xmm, |
3877 | 0 | ) -> ConsumesFlags { |
3878 | 0 | let v5 = C::temp_writable_xmm(ctx); |
3879 | 0 | let v6 = C::temp_writable_xmm(ctx); |
3880 | 0 | let v8 = C::writable_xmm_to_xmm(ctx, v6); |
3881 | 0 | let v10 = constructor_writable_xmm_to_value_regs(ctx, v5); |
3882 | 0 | let v7 = MInst::XmmCmove { |
3883 | 0 | ty: arg0, |
3884 | 0 | cc: arg1.clone(), |
3885 | 0 | consequent: arg3.clone(), |
3886 | 0 | alternative: arg4, |
3887 | 0 | dst: v6, |
3888 | 0 | }; |
3889 | 0 | let v9 = MInst::XmmCmove { |
3890 | 0 | ty: arg0, |
3891 | 0 | cc: arg2.clone(), |
3892 | 0 | consequent: arg3.clone(), |
3893 | 0 | alternative: v8, |
3894 | 0 | dst: v5, |
3895 | 0 | }; |
3896 | 0 | let v11 = ConsumesFlags::ConsumesFlagsTwiceReturnsValueRegs { |
3897 | 0 | inst1: v7, |
3898 | 0 | inst2: v9, |
3899 | 0 | result: v10, |
3900 | 0 | }; |
3901 | 0 | // Rule at src/isa/x64/inst.isle line 2440. |
3902 | 0 | return v11; |
3903 | 0 | } |
3904 | | |
3905 | | // Generated as internal constructor for term cmove_or_from_values. |
3906 | 0 | pub fn constructor_cmove_or_from_values<C: Context>( |
3907 | 0 | ctx: &mut C, |
3908 | 0 | arg0: Type, |
3909 | 0 | arg1: &CC, |
3910 | 0 | arg2: &CC, |
3911 | 0 | arg3: Value, |
3912 | 0 | arg4: Value, |
3913 | 0 | ) -> ConsumesFlags { |
3914 | 0 | let v1 = &C::type_register_class(ctx, arg0); |
3915 | 0 | if let Some(v2) = v1 { |
3916 | 0 | match v2 { |
3917 | | &RegisterClass::Gpr { |
3918 | 0 | single_register: v3, |
3919 | 0 | } => { |
3920 | 0 | match v3 { |
3921 | | true => { |
3922 | 0 | let v37 = &constructor_put_in_gpr_mem(ctx, arg3); |
3923 | 0 | let v38 = constructor_put_in_gpr(ctx, arg4); |
3924 | 0 | let v39 = &constructor_cmove_or(ctx, arg0, arg1, arg2, v37, v38); |
3925 | 0 | // Rule at src/isa/x64/inst.isle line 2473. |
3926 | 0 | return v39.clone(); |
3927 | | } |
3928 | | false => { |
3929 | 0 | if arg0 == I128 { |
3930 | 0 | let v8 = C::put_in_regs(ctx, arg3); |
3931 | 0 | let v9 = C::put_in_regs(ctx, arg4); |
3932 | 0 | let v10 = C::temp_writable_gpr(ctx); |
3933 | 0 | let v11 = C::temp_writable_gpr(ctx); |
3934 | 0 | let v12 = C::temp_writable_gpr(ctx); |
3935 | 0 | let v13 = C::temp_writable_gpr(ctx); |
3936 | 0 | let v16 = constructor_value_regs_get_gpr(ctx, v8, 0x0); |
3937 | 0 | let v17 = &C::gpr_to_gpr_mem(ctx, v16); |
3938 | 0 | let v18 = constructor_value_regs_get_gpr(ctx, v9, 0x0); |
3939 | 0 | let v20 = constructor_value_regs_get_gpr(ctx, v8, 0x0); |
3940 | 0 | let v21 = &C::gpr_to_gpr_mem(ctx, v20); |
3941 | 0 | let v22 = C::writable_gpr_to_gpr(ctx, v12); |
3942 | 0 | let v25 = constructor_value_regs_get_gpr(ctx, v8, 0x1); |
3943 | 0 | let v26 = &C::gpr_to_gpr_mem(ctx, v25); |
3944 | 0 | let v27 = constructor_value_regs_get_gpr(ctx, v9, 0x1); |
3945 | 0 | let v29 = constructor_value_regs_get_gpr(ctx, v8, 0x1); |
3946 | 0 | let v30 = &C::gpr_to_gpr_mem(ctx, v29); |
3947 | 0 | let v31 = C::writable_gpr_to_gpr(ctx, v13); |
3948 | 0 | let v33 = constructor_writable_gpr_to_r_reg(ctx, v10); |
3949 | 0 | let v34 = constructor_writable_gpr_to_r_reg(ctx, v11); |
3950 | 0 | let v35 = C::value_regs(ctx, v33, v34); |
3951 | 0 | let v19 = MInst::Cmove { |
3952 | 0 | size: OperandSize::Size64, |
3953 | 0 | cc: arg1.clone(), |
3954 | 0 | consequent: v17.clone(), |
3955 | 0 | alternative: v18, |
3956 | 0 | dst: v12, |
3957 | 0 | }; |
3958 | 0 | let v23 = MInst::Cmove { |
3959 | 0 | size: OperandSize::Size64, |
3960 | 0 | cc: arg2.clone(), |
3961 | 0 | consequent: v21.clone(), |
3962 | 0 | alternative: v22, |
3963 | 0 | dst: v10, |
3964 | 0 | }; |
3965 | 0 | let v28 = MInst::Cmove { |
3966 | 0 | size: OperandSize::Size64, |
3967 | 0 | cc: arg1.clone(), |
3968 | 0 | consequent: v26.clone(), |
3969 | 0 | alternative: v27, |
3970 | 0 | dst: v13, |
3971 | 0 | }; |
3972 | 0 | let v32 = MInst::Cmove { |
3973 | 0 | size: OperandSize::Size64, |
3974 | 0 | cc: arg2.clone(), |
3975 | 0 | consequent: v30.clone(), |
3976 | 0 | alternative: v31, |
3977 | 0 | dst: v11, |
3978 | 0 | }; |
3979 | 0 | let v36 = ConsumesFlags::ConsumesFlagsFourTimesReturnsValueRegs { |
3980 | 0 | inst1: v19, |
3981 | 0 | inst2: v23, |
3982 | 0 | inst3: v28, |
3983 | 0 | inst4: v32, |
3984 | 0 | result: v35, |
3985 | 0 | }; |
3986 | 0 | // Rule at src/isa/x64/inst.isle line 2454. |
3987 | 0 | return v36; |
3988 | 0 | } |
3989 | | } |
3990 | | _ => {} |
3991 | | } |
3992 | | } |
3993 | | &RegisterClass::Xmm => { |
3994 | 0 | let v40 = &constructor_put_in_xmm_mem_aligned(ctx, arg3); |
3995 | 0 | let v41 = constructor_put_in_xmm(ctx, arg4); |
3996 | 0 | let v42 = &constructor_cmove_or_xmm(ctx, arg0, arg1, arg2, v40, v41); |
3997 | 0 | // Rule at src/isa/x64/inst.isle line 2476. |
3998 | 0 | return v42.clone(); |
3999 | | } |
4000 | 0 | _ => {} |
4001 | | } |
4002 | 0 | } |
4003 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "cmove_or_from_values", "src/isa/x64/inst.isle line 2453") |
4004 | 0 | } |
4005 | | |
4006 | | // Generated as internal constructor for term x64_setcc. |
4007 | 8.49k | pub fn constructor_x64_setcc<C: Context>( |
4008 | 8.49k | ctx: &mut C, |
4009 | 8.49k | arg0: &CC, |
4010 | 8.49k | ) -> ConsumesFlags { |
4011 | 8.49k | let v1 = C::temp_writable_gpr(ctx); |
4012 | 8.49k | let v3 = constructor_writable_gpr_to_r_reg(ctx, v1); |
4013 | 8.49k | let v2 = MInst::Setcc { |
4014 | 8.49k | cc: arg0.clone(), |
4015 | 8.49k | dst: v1, |
4016 | 8.49k | }; |
4017 | 8.49k | let v4 = ConsumesFlags::ConsumesFlagsReturnsReg { |
4018 | 8.49k | inst: v2, |
4019 | 8.49k | result: v3, |
4020 | 8.49k | }; |
4021 | 8.49k | // Rule at src/isa/x64/inst.isle line 2481. |
4022 | 8.49k | return v4; |
4023 | 8.49k | } |
4024 | | |
4025 | | // Generated as internal constructor for term x64_setcc_paired. |
4026 | 0 | pub fn constructor_x64_setcc_paired<C: Context>( |
4027 | 0 | ctx: &mut C, |
4028 | 0 | arg0: &CC, |
4029 | 0 | ) -> ConsumesFlags { |
4030 | 0 | let v1 = C::temp_writable_gpr(ctx); |
4031 | 0 | let v3 = constructor_writable_gpr_to_r_reg(ctx, v1); |
4032 | 0 | let v2 = MInst::Setcc { |
4033 | 0 | cc: arg0.clone(), |
4034 | 0 | dst: v1, |
4035 | 0 | }; |
4036 | 0 | let v4 = ConsumesFlags::ConsumesFlagsReturnsResultWithProducer { |
4037 | 0 | inst: v2, |
4038 | 0 | result: v3, |
4039 | 0 | }; |
4040 | 0 | // Rule at src/isa/x64/inst.isle line 2490. |
4041 | 0 | return v4; |
4042 | 0 | } |
4043 | | |
4044 | | // Generated as internal constructor for term xmm_rm_r. |
4045 | 0 | pub fn constructor_xmm_rm_r<C: Context>( |
4046 | 0 | ctx: &mut C, |
4047 | 0 | arg0: &SseOpcode, |
4048 | 0 | arg1: Xmm, |
4049 | 0 | arg2: &XmmMemAligned, |
4050 | 0 | ) -> Xmm { |
4051 | 0 | let v3 = C::temp_writable_xmm(ctx); |
4052 | 0 | let v4 = MInst::XmmRmR { |
4053 | 0 | op: arg0.clone(), |
4054 | 0 | src1: arg1, |
4055 | 0 | src2: arg2.clone(), |
4056 | 0 | dst: v3, |
4057 | 0 | }; |
4058 | 0 | let v5 = C::emit(ctx, &v4); |
4059 | 0 | let v6 = C::writable_xmm_to_xmm(ctx, v3); |
4060 | 0 | // Rule at src/isa/x64/inst.isle line 2498. |
4061 | 0 | return v6; |
4062 | 0 | } |
4063 | | |
4064 | | // Generated as internal constructor for term xmm_rm_r_unaligned. |
4065 | 0 | pub fn constructor_xmm_rm_r_unaligned<C: Context>( |
4066 | 0 | ctx: &mut C, |
4067 | 0 | arg0: &SseOpcode, |
4068 | 0 | arg1: Xmm, |
4069 | 0 | arg2: &XmmMem, |
4070 | 0 | ) -> Xmm { |
4071 | 0 | let v3 = C::temp_writable_xmm(ctx); |
4072 | 0 | let v4 = MInst::XmmRmRUnaligned { |
4073 | 0 | op: arg0.clone(), |
4074 | 0 | src1: arg1, |
4075 | 0 | src2: arg2.clone(), |
4076 | 0 | dst: v3, |
4077 | 0 | }; |
4078 | 0 | let v5 = C::emit(ctx, &v4); |
4079 | 0 | let v6 = C::writable_xmm_to_xmm(ctx, v3); |
4080 | 0 | // Rule at src/isa/x64/inst.isle line 2505. |
4081 | 0 | return v6; |
4082 | 0 | } |
4083 | | |
4084 | | // Generated as internal constructor for term x64_paddb. |
4085 | 0 | pub fn constructor_x64_paddb<C: Context>( |
4086 | 0 | ctx: &mut C, |
4087 | 0 | arg0: Xmm, |
4088 | 0 | arg1: &XmmMem, |
4089 | 0 | ) -> Xmm { |
4090 | 0 | let v5 = C::use_avx_simd(ctx); |
4091 | 0 | if v5 == true { |
4092 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4093 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpaddb, arg0, v7); |
4094 | 0 | // Rule at src/isa/x64/inst.isle line 2514. |
4095 | 0 | return v8; |
4096 | 0 | } |
4097 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4098 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Paddb, arg0, v3); |
4099 | 0 | // Rule at src/isa/x64/inst.isle line 2512. |
4100 | 0 | return v4; |
4101 | 0 | } |
4102 | | |
4103 | | // Generated as internal constructor for term x64_paddw. |
4104 | 0 | pub fn constructor_x64_paddw<C: Context>( |
4105 | 0 | ctx: &mut C, |
4106 | 0 | arg0: Xmm, |
4107 | 0 | arg1: &XmmMem, |
4108 | 0 | ) -> Xmm { |
4109 | 0 | let v5 = C::use_avx_simd(ctx); |
4110 | 0 | if v5 == true { |
4111 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4112 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpaddw, arg0, v7); |
4113 | 0 | // Rule at src/isa/x64/inst.isle line 2522. |
4114 | 0 | return v8; |
4115 | 0 | } |
4116 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4117 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Paddw, arg0, v3); |
4118 | 0 | // Rule at src/isa/x64/inst.isle line 2520. |
4119 | 0 | return v4; |
4120 | 0 | } |
4121 | | |
4122 | | // Generated as internal constructor for term x64_paddd. |
4123 | 0 | pub fn constructor_x64_paddd<C: Context>( |
4124 | 0 | ctx: &mut C, |
4125 | 0 | arg0: Xmm, |
4126 | 0 | arg1: &XmmMem, |
4127 | 0 | ) -> Xmm { |
4128 | 0 | let v5 = C::use_avx_simd(ctx); |
4129 | 0 | if v5 == true { |
4130 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4131 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpaddd, arg0, v7); |
4132 | 0 | // Rule at src/isa/x64/inst.isle line 2530. |
4133 | 0 | return v8; |
4134 | 0 | } |
4135 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4136 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Paddd, arg0, v3); |
4137 | 0 | // Rule at src/isa/x64/inst.isle line 2528. |
4138 | 0 | return v4; |
4139 | 0 | } |
4140 | | |
4141 | | // Generated as internal constructor for term x64_paddq. |
4142 | 0 | pub fn constructor_x64_paddq<C: Context>( |
4143 | 0 | ctx: &mut C, |
4144 | 0 | arg0: Xmm, |
4145 | 0 | arg1: &XmmMem, |
4146 | 0 | ) -> Xmm { |
4147 | 0 | let v5 = C::use_avx_simd(ctx); |
4148 | 0 | if v5 == true { |
4149 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4150 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpaddq, arg0, v7); |
4151 | 0 | // Rule at src/isa/x64/inst.isle line 2538. |
4152 | 0 | return v8; |
4153 | 0 | } |
4154 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4155 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Paddq, arg0, v3); |
4156 | 0 | // Rule at src/isa/x64/inst.isle line 2536. |
4157 | 0 | return v4; |
4158 | 0 | } |
4159 | | |
4160 | | // Generated as internal constructor for term x64_paddsb. |
4161 | 0 | pub fn constructor_x64_paddsb<C: Context>( |
4162 | 0 | ctx: &mut C, |
4163 | 0 | arg0: Xmm, |
4164 | 0 | arg1: &XmmMem, |
4165 | 0 | ) -> Xmm { |
4166 | 0 | let v5 = C::use_avx_simd(ctx); |
4167 | 0 | if v5 == true { |
4168 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4169 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpaddsb, arg0, v7); |
4170 | 0 | // Rule at src/isa/x64/inst.isle line 2546. |
4171 | 0 | return v8; |
4172 | 0 | } |
4173 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4174 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Paddsb, arg0, v3); |
4175 | 0 | // Rule at src/isa/x64/inst.isle line 2544. |
4176 | 0 | return v4; |
4177 | 0 | } |
4178 | | |
4179 | | // Generated as internal constructor for term x64_paddsw. |
4180 | 0 | pub fn constructor_x64_paddsw<C: Context>( |
4181 | 0 | ctx: &mut C, |
4182 | 0 | arg0: Xmm, |
4183 | 0 | arg1: &XmmMem, |
4184 | 0 | ) -> Xmm { |
4185 | 0 | let v5 = C::use_avx_simd(ctx); |
4186 | 0 | if v5 == true { |
4187 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4188 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpaddsw, arg0, v7); |
4189 | 0 | // Rule at src/isa/x64/inst.isle line 2554. |
4190 | 0 | return v8; |
4191 | 0 | } |
4192 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4193 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Paddsw, arg0, v3); |
4194 | 0 | // Rule at src/isa/x64/inst.isle line 2552. |
4195 | 0 | return v4; |
4196 | 0 | } |
4197 | | |
4198 | | // Generated as internal constructor for term x64_phaddw. |
4199 | 0 | pub fn constructor_x64_phaddw<C: Context>( |
4200 | 0 | ctx: &mut C, |
4201 | 0 | arg0: Xmm, |
4202 | 0 | arg1: &XmmMem, |
4203 | 0 | ) -> Xmm { |
4204 | 0 | let v5 = C::use_avx_simd(ctx); |
4205 | 0 | if v5 == true { |
4206 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4207 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vphaddw, arg0, v7); |
4208 | 0 | // Rule at src/isa/x64/inst.isle line 2562. |
4209 | 0 | return v8; |
4210 | 0 | } |
4211 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4212 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Phaddw, arg0, v3); |
4213 | 0 | // Rule at src/isa/x64/inst.isle line 2560. |
4214 | 0 | return v4; |
4215 | 0 | } |
4216 | | |
4217 | | // Generated as internal constructor for term x64_phaddd. |
4218 | 0 | pub fn constructor_x64_phaddd<C: Context>( |
4219 | 0 | ctx: &mut C, |
4220 | 0 | arg0: Xmm, |
4221 | 0 | arg1: &XmmMem, |
4222 | 0 | ) -> Xmm { |
4223 | 0 | let v5 = C::use_avx_simd(ctx); |
4224 | 0 | if v5 == true { |
4225 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4226 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vphaddd, arg0, v7); |
4227 | 0 | // Rule at src/isa/x64/inst.isle line 2570. |
4228 | 0 | return v8; |
4229 | 0 | } |
4230 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4231 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Phaddd, arg0, v3); |
4232 | 0 | // Rule at src/isa/x64/inst.isle line 2568. |
4233 | 0 | return v4; |
4234 | 0 | } |
4235 | | |
4236 | | // Generated as internal constructor for term x64_paddusb. |
4237 | 0 | pub fn constructor_x64_paddusb<C: Context>( |
4238 | 0 | ctx: &mut C, |
4239 | 0 | arg0: Xmm, |
4240 | 0 | arg1: &XmmMem, |
4241 | 0 | ) -> Xmm { |
4242 | 0 | let v5 = C::use_avx_simd(ctx); |
4243 | 0 | if v5 == true { |
4244 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4245 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpaddusb, arg0, v7); |
4246 | 0 | // Rule at src/isa/x64/inst.isle line 2578. |
4247 | 0 | return v8; |
4248 | 0 | } |
4249 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4250 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Paddusb, arg0, v3); |
4251 | 0 | // Rule at src/isa/x64/inst.isle line 2576. |
4252 | 0 | return v4; |
4253 | 0 | } |
4254 | | |
4255 | | // Generated as internal constructor for term x64_paddusw. |
4256 | 0 | pub fn constructor_x64_paddusw<C: Context>( |
4257 | 0 | ctx: &mut C, |
4258 | 0 | arg0: Xmm, |
4259 | 0 | arg1: &XmmMem, |
4260 | 0 | ) -> Xmm { |
4261 | 0 | let v5 = C::use_avx_simd(ctx); |
4262 | 0 | if v5 == true { |
4263 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4264 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpaddusw, arg0, v7); |
4265 | 0 | // Rule at src/isa/x64/inst.isle line 2586. |
4266 | 0 | return v8; |
4267 | 0 | } |
4268 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4269 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Paddusw, arg0, v3); |
4270 | 0 | // Rule at src/isa/x64/inst.isle line 2584. |
4271 | 0 | return v4; |
4272 | 0 | } |
4273 | | |
4274 | | // Generated as internal constructor for term x64_psubb. |
4275 | 0 | pub fn constructor_x64_psubb<C: Context>( |
4276 | 0 | ctx: &mut C, |
4277 | 0 | arg0: Xmm, |
4278 | 0 | arg1: &XmmMem, |
4279 | 0 | ) -> Xmm { |
4280 | 0 | let v5 = C::use_avx_simd(ctx); |
4281 | 0 | if v5 == true { |
4282 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4283 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpsubb, arg0, v7); |
4284 | 0 | // Rule at src/isa/x64/inst.isle line 2594. |
4285 | 0 | return v8; |
4286 | 0 | } |
4287 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4288 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Psubb, arg0, v3); |
4289 | 0 | // Rule at src/isa/x64/inst.isle line 2592. |
4290 | 0 | return v4; |
4291 | 0 | } |
4292 | | |
4293 | | // Generated as internal constructor for term x64_psubw. |
4294 | 0 | pub fn constructor_x64_psubw<C: Context>( |
4295 | 0 | ctx: &mut C, |
4296 | 0 | arg0: Xmm, |
4297 | 0 | arg1: &XmmMem, |
4298 | 0 | ) -> Xmm { |
4299 | 0 | let v5 = C::use_avx_simd(ctx); |
4300 | 0 | if v5 == true { |
4301 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4302 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpsubw, arg0, v7); |
4303 | 0 | // Rule at src/isa/x64/inst.isle line 2602. |
4304 | 0 | return v8; |
4305 | 0 | } |
4306 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4307 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Psubw, arg0, v3); |
4308 | 0 | // Rule at src/isa/x64/inst.isle line 2600. |
4309 | 0 | return v4; |
4310 | 0 | } |
4311 | | |
4312 | | // Generated as internal constructor for term x64_psubd. |
4313 | 0 | pub fn constructor_x64_psubd<C: Context>( |
4314 | 0 | ctx: &mut C, |
4315 | 0 | arg0: Xmm, |
4316 | 0 | arg1: &XmmMem, |
4317 | 0 | ) -> Xmm { |
4318 | 0 | let v5 = C::use_avx_simd(ctx); |
4319 | 0 | if v5 == true { |
4320 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4321 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpsubd, arg0, v7); |
4322 | 0 | // Rule at src/isa/x64/inst.isle line 2610. |
4323 | 0 | return v8; |
4324 | 0 | } |
4325 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4326 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Psubd, arg0, v3); |
4327 | 0 | // Rule at src/isa/x64/inst.isle line 2608. |
4328 | 0 | return v4; |
4329 | 0 | } |
4330 | | |
4331 | | // Generated as internal constructor for term x64_psubq. |
4332 | 0 | pub fn constructor_x64_psubq<C: Context>( |
4333 | 0 | ctx: &mut C, |
4334 | 0 | arg0: Xmm, |
4335 | 0 | arg1: &XmmMem, |
4336 | 0 | ) -> Xmm { |
4337 | 0 | let v5 = C::use_avx_simd(ctx); |
4338 | 0 | if v5 == true { |
4339 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4340 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpsubq, arg0, v7); |
4341 | 0 | // Rule at src/isa/x64/inst.isle line 2618. |
4342 | 0 | return v8; |
4343 | 0 | } |
4344 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4345 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Psubq, arg0, v3); |
4346 | 0 | // Rule at src/isa/x64/inst.isle line 2616. |
4347 | 0 | return v4; |
4348 | 0 | } |
4349 | | |
4350 | | // Generated as internal constructor for term x64_psubsb. |
4351 | 0 | pub fn constructor_x64_psubsb<C: Context>( |
4352 | 0 | ctx: &mut C, |
4353 | 0 | arg0: Xmm, |
4354 | 0 | arg1: &XmmMem, |
4355 | 0 | ) -> Xmm { |
4356 | 0 | let v5 = C::use_avx_simd(ctx); |
4357 | 0 | if v5 == true { |
4358 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4359 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpsubsb, arg0, v7); |
4360 | 0 | // Rule at src/isa/x64/inst.isle line 2626. |
4361 | 0 | return v8; |
4362 | 0 | } |
4363 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4364 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Psubsb, arg0, v3); |
4365 | 0 | // Rule at src/isa/x64/inst.isle line 2624. |
4366 | 0 | return v4; |
4367 | 0 | } |
4368 | | |
4369 | | // Generated as internal constructor for term x64_psubsw. |
4370 | 0 | pub fn constructor_x64_psubsw<C: Context>( |
4371 | 0 | ctx: &mut C, |
4372 | 0 | arg0: Xmm, |
4373 | 0 | arg1: &XmmMem, |
4374 | 0 | ) -> Xmm { |
4375 | 0 | let v5 = C::use_avx_simd(ctx); |
4376 | 0 | if v5 == true { |
4377 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4378 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpsubsw, arg0, v7); |
4379 | 0 | // Rule at src/isa/x64/inst.isle line 2634. |
4380 | 0 | return v8; |
4381 | 0 | } |
4382 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4383 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Psubsw, arg0, v3); |
4384 | 0 | // Rule at src/isa/x64/inst.isle line 2632. |
4385 | 0 | return v4; |
4386 | 0 | } |
4387 | | |
4388 | | // Generated as internal constructor for term x64_psubusb. |
4389 | 0 | pub fn constructor_x64_psubusb<C: Context>( |
4390 | 0 | ctx: &mut C, |
4391 | 0 | arg0: Xmm, |
4392 | 0 | arg1: &XmmMem, |
4393 | 0 | ) -> Xmm { |
4394 | 0 | let v5 = C::use_avx_simd(ctx); |
4395 | 0 | if v5 == true { |
4396 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4397 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpsubusb, arg0, v7); |
4398 | 0 | // Rule at src/isa/x64/inst.isle line 2642. |
4399 | 0 | return v8; |
4400 | 0 | } |
4401 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4402 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Psubusb, arg0, v3); |
4403 | 0 | // Rule at src/isa/x64/inst.isle line 2640. |
4404 | 0 | return v4; |
4405 | 0 | } |
4406 | | |
4407 | | // Generated as internal constructor for term x64_psubusw. |
4408 | 0 | pub fn constructor_x64_psubusw<C: Context>( |
4409 | 0 | ctx: &mut C, |
4410 | 0 | arg0: Xmm, |
4411 | 0 | arg1: &XmmMem, |
4412 | 0 | ) -> Xmm { |
4413 | 0 | let v5 = C::use_avx_simd(ctx); |
4414 | 0 | if v5 == true { |
4415 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4416 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpsubusw, arg0, v7); |
4417 | 0 | // Rule at src/isa/x64/inst.isle line 2650. |
4418 | 0 | return v8; |
4419 | 0 | } |
4420 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4421 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Psubusw, arg0, v3); |
4422 | 0 | // Rule at src/isa/x64/inst.isle line 2648. |
4423 | 0 | return v4; |
4424 | 0 | } |
4425 | | |
4426 | | // Generated as internal constructor for term x64_pavgb. |
4427 | 0 | pub fn constructor_x64_pavgb<C: Context>( |
4428 | 0 | ctx: &mut C, |
4429 | 0 | arg0: Xmm, |
4430 | 0 | arg1: &XmmMem, |
4431 | 0 | ) -> Xmm { |
4432 | 0 | let v5 = C::use_avx_simd(ctx); |
4433 | 0 | if v5 == true { |
4434 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4435 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpavgb, arg0, v7); |
4436 | 0 | // Rule at src/isa/x64/inst.isle line 2658. |
4437 | 0 | return v8; |
4438 | 0 | } |
4439 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4440 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pavgb, arg0, v3); |
4441 | 0 | // Rule at src/isa/x64/inst.isle line 2656. |
4442 | 0 | return v4; |
4443 | 0 | } |
4444 | | |
4445 | | // Generated as internal constructor for term x64_pavgw. |
4446 | 0 | pub fn constructor_x64_pavgw<C: Context>( |
4447 | 0 | ctx: &mut C, |
4448 | 0 | arg0: Xmm, |
4449 | 0 | arg1: &XmmMem, |
4450 | 0 | ) -> Xmm { |
4451 | 0 | let v5 = C::use_avx_simd(ctx); |
4452 | 0 | if v5 == true { |
4453 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4454 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpavgw, arg0, v7); |
4455 | 0 | // Rule at src/isa/x64/inst.isle line 2666. |
4456 | 0 | return v8; |
4457 | 0 | } |
4458 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4459 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pavgw, arg0, v3); |
4460 | 0 | // Rule at src/isa/x64/inst.isle line 2664. |
4461 | 0 | return v4; |
4462 | 0 | } |
4463 | | |
4464 | | // Generated as internal constructor for term x64_pand. |
4465 | 0 | pub fn constructor_x64_pand<C: Context>( |
4466 | 0 | ctx: &mut C, |
4467 | 0 | arg0: Xmm, |
4468 | 0 | arg1: &XmmMem, |
4469 | 0 | ) -> Xmm { |
4470 | 0 | let v5 = C::use_avx_simd(ctx); |
4471 | 0 | if v5 == true { |
4472 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4473 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpand, arg0, v7); |
4474 | 0 | // Rule at src/isa/x64/inst.isle line 2674. |
4475 | 0 | return v8; |
4476 | 0 | } |
4477 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4478 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pand, arg0, v3); |
4479 | 0 | // Rule at src/isa/x64/inst.isle line 2672. |
4480 | 0 | return v4; |
4481 | 0 | } |
4482 | | |
4483 | | // Generated as internal constructor for term x64_andps. |
4484 | 0 | pub fn constructor_x64_andps<C: Context>( |
4485 | 0 | ctx: &mut C, |
4486 | 0 | arg0: Xmm, |
4487 | 0 | arg1: &XmmMem, |
4488 | 0 | ) -> Xmm { |
4489 | 0 | let v5 = C::use_avx_simd(ctx); |
4490 | 0 | if v5 == true { |
4491 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4492 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vandps, arg0, v7); |
4493 | 0 | // Rule at src/isa/x64/inst.isle line 2682. |
4494 | 0 | return v8; |
4495 | 0 | } |
4496 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4497 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Andps, arg0, v3); |
4498 | 0 | // Rule at src/isa/x64/inst.isle line 2680. |
4499 | 0 | return v4; |
4500 | 0 | } |
4501 | | |
4502 | | // Generated as internal constructor for term x64_andpd. |
4503 | 0 | pub fn constructor_x64_andpd<C: Context>( |
4504 | 0 | ctx: &mut C, |
4505 | 0 | arg0: Xmm, |
4506 | 0 | arg1: &XmmMem, |
4507 | 0 | ) -> Xmm { |
4508 | 0 | let v5 = C::use_avx_simd(ctx); |
4509 | 0 | if v5 == true { |
4510 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4511 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vandpd, arg0, v7); |
4512 | 0 | // Rule at src/isa/x64/inst.isle line 2690. |
4513 | 0 | return v8; |
4514 | 0 | } |
4515 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4516 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Andpd, arg0, v3); |
4517 | 0 | // Rule at src/isa/x64/inst.isle line 2688. |
4518 | 0 | return v4; |
4519 | 0 | } |
4520 | | |
4521 | | // Generated as internal constructor for term x64_por. |
4522 | 0 | pub fn constructor_x64_por<C: Context>( |
4523 | 0 | ctx: &mut C, |
4524 | 0 | arg0: Xmm, |
4525 | 0 | arg1: &XmmMem, |
4526 | 0 | ) -> Xmm { |
4527 | 0 | let v5 = C::use_avx_simd(ctx); |
4528 | 0 | if v5 == true { |
4529 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4530 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpor, arg0, v7); |
4531 | 0 | // Rule at src/isa/x64/inst.isle line 2698. |
4532 | 0 | return v8; |
4533 | 0 | } |
4534 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4535 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Por, arg0, v3); |
4536 | 0 | // Rule at src/isa/x64/inst.isle line 2696. |
4537 | 0 | return v4; |
4538 | 0 | } |
4539 | | |
4540 | | // Generated as internal constructor for term x64_orps. |
4541 | 0 | pub fn constructor_x64_orps<C: Context>( |
4542 | 0 | ctx: &mut C, |
4543 | 0 | arg0: Xmm, |
4544 | 0 | arg1: &XmmMem, |
4545 | 0 | ) -> Xmm { |
4546 | 0 | let v5 = C::use_avx_simd(ctx); |
4547 | 0 | if v5 == true { |
4548 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4549 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vorps, arg0, v7); |
4550 | 0 | // Rule at src/isa/x64/inst.isle line 2706. |
4551 | 0 | return v8; |
4552 | 0 | } |
4553 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4554 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Orps, arg0, v3); |
4555 | 0 | // Rule at src/isa/x64/inst.isle line 2704. |
4556 | 0 | return v4; |
4557 | 0 | } |
4558 | | |
4559 | | // Generated as internal constructor for term x64_orpd. |
4560 | 0 | pub fn constructor_x64_orpd<C: Context>( |
4561 | 0 | ctx: &mut C, |
4562 | 0 | arg0: Xmm, |
4563 | 0 | arg1: &XmmMem, |
4564 | 0 | ) -> Xmm { |
4565 | 0 | let v5 = C::use_avx_simd(ctx); |
4566 | 0 | if v5 == true { |
4567 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4568 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vorpd, arg0, v7); |
4569 | 0 | // Rule at src/isa/x64/inst.isle line 2714. |
4570 | 0 | return v8; |
4571 | 0 | } |
4572 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4573 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Orpd, arg0, v3); |
4574 | 0 | // Rule at src/isa/x64/inst.isle line 2712. |
4575 | 0 | return v4; |
4576 | 0 | } |
4577 | | |
4578 | | // Generated as internal constructor for term x64_pxor. |
4579 | 0 | pub fn constructor_x64_pxor<C: Context>( |
4580 | 0 | ctx: &mut C, |
4581 | 0 | arg0: Xmm, |
4582 | 0 | arg1: &XmmMem, |
4583 | 0 | ) -> Xmm { |
4584 | 0 | let v5 = C::use_avx_simd(ctx); |
4585 | 0 | if v5 == true { |
4586 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4587 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpxor, arg0, v7); |
4588 | 0 | // Rule at src/isa/x64/inst.isle line 2722. |
4589 | 0 | return v8; |
4590 | 0 | } |
4591 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4592 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pxor, arg0, v3); |
4593 | 0 | // Rule at src/isa/x64/inst.isle line 2720. |
4594 | 0 | return v4; |
4595 | 0 | } |
4596 | | |
4597 | | // Generated as internal constructor for term x64_xorps. |
4598 | 0 | pub fn constructor_x64_xorps<C: Context>( |
4599 | 0 | ctx: &mut C, |
4600 | 0 | arg0: Xmm, |
4601 | 0 | arg1: &XmmMem, |
4602 | 0 | ) -> Xmm { |
4603 | 0 | let v5 = C::use_avx_simd(ctx); |
4604 | 0 | if v5 == true { |
4605 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4606 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vxorps, arg0, v7); |
4607 | 0 | // Rule at src/isa/x64/inst.isle line 2730. |
4608 | 0 | return v8; |
4609 | 0 | } |
4610 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4611 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Xorps, arg0, v3); |
4612 | 0 | // Rule at src/isa/x64/inst.isle line 2728. |
4613 | 0 | return v4; |
4614 | 0 | } |
4615 | | |
4616 | | // Generated as internal constructor for term x64_xorpd. |
4617 | 0 | pub fn constructor_x64_xorpd<C: Context>( |
4618 | 0 | ctx: &mut C, |
4619 | 0 | arg0: Xmm, |
4620 | 0 | arg1: &XmmMem, |
4621 | 0 | ) -> Xmm { |
4622 | 0 | let v5 = C::use_avx_simd(ctx); |
4623 | 0 | if v5 == true { |
4624 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4625 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vxorpd, arg0, v7); |
4626 | 0 | // Rule at src/isa/x64/inst.isle line 2738. |
4627 | 0 | return v8; |
4628 | 0 | } |
4629 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4630 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Xorpd, arg0, v3); |
4631 | 0 | // Rule at src/isa/x64/inst.isle line 2736. |
4632 | 0 | return v4; |
4633 | 0 | } |
4634 | | |
4635 | | // Generated as internal constructor for term x64_pmullw. |
4636 | 0 | pub fn constructor_x64_pmullw<C: Context>( |
4637 | 0 | ctx: &mut C, |
4638 | 0 | arg0: Xmm, |
4639 | 0 | arg1: &XmmMem, |
4640 | 0 | ) -> Xmm { |
4641 | 0 | let v5 = C::use_avx_simd(ctx); |
4642 | 0 | if v5 == true { |
4643 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4644 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpmullw, arg0, v7); |
4645 | 0 | // Rule at src/isa/x64/inst.isle line 2746. |
4646 | 0 | return v8; |
4647 | 0 | } |
4648 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4649 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pmullw, arg0, v3); |
4650 | 0 | // Rule at src/isa/x64/inst.isle line 2744. |
4651 | 0 | return v4; |
4652 | 0 | } |
4653 | | |
4654 | | // Generated as internal constructor for term x64_pmulld. |
4655 | 0 | pub fn constructor_x64_pmulld<C: Context>( |
4656 | 0 | ctx: &mut C, |
4657 | 0 | arg0: Xmm, |
4658 | 0 | arg1: &XmmMem, |
4659 | 0 | ) -> Xmm { |
4660 | 0 | let v5 = C::use_avx_simd(ctx); |
4661 | 0 | if v5 == true { |
4662 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4663 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpmulld, arg0, v7); |
4664 | 0 | // Rule at src/isa/x64/inst.isle line 2754. |
4665 | 0 | return v8; |
4666 | 0 | } |
4667 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4668 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pmulld, arg0, v3); |
4669 | 0 | // Rule at src/isa/x64/inst.isle line 2752. |
4670 | 0 | return v4; |
4671 | 0 | } |
4672 | | |
4673 | | // Generated as internal constructor for term x64_pmulhw. |
4674 | 0 | pub fn constructor_x64_pmulhw<C: Context>( |
4675 | 0 | ctx: &mut C, |
4676 | 0 | arg0: Xmm, |
4677 | 0 | arg1: &XmmMem, |
4678 | 0 | ) -> Xmm { |
4679 | 0 | let v5 = C::use_avx_simd(ctx); |
4680 | 0 | if v5 == true { |
4681 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4682 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpmulhw, arg0, v7); |
4683 | 0 | // Rule at src/isa/x64/inst.isle line 2762. |
4684 | 0 | return v8; |
4685 | 0 | } |
4686 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4687 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pmulhw, arg0, v3); |
4688 | 0 | // Rule at src/isa/x64/inst.isle line 2760. |
4689 | 0 | return v4; |
4690 | 0 | } |
4691 | | |
4692 | | // Generated as internal constructor for term x64_pmulhrsw. |
4693 | 0 | pub fn constructor_x64_pmulhrsw<C: Context>( |
4694 | 0 | ctx: &mut C, |
4695 | 0 | arg0: Xmm, |
4696 | 0 | arg1: &XmmMem, |
4697 | 0 | ) -> Xmm { |
4698 | 0 | let v5 = C::use_avx_simd(ctx); |
4699 | 0 | if v5 == true { |
4700 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4701 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpmulhrsw, arg0, v7); |
4702 | 0 | // Rule at src/isa/x64/inst.isle line 2770. |
4703 | 0 | return v8; |
4704 | 0 | } |
4705 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4706 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pmulhrsw, arg0, v3); |
4707 | 0 | // Rule at src/isa/x64/inst.isle line 2768. |
4708 | 0 | return v4; |
4709 | 0 | } |
4710 | | |
4711 | | // Generated as internal constructor for term x64_pmulhuw. |
4712 | 0 | pub fn constructor_x64_pmulhuw<C: Context>( |
4713 | 0 | ctx: &mut C, |
4714 | 0 | arg0: Xmm, |
4715 | 0 | arg1: &XmmMem, |
4716 | 0 | ) -> Xmm { |
4717 | 0 | let v5 = C::use_avx_simd(ctx); |
4718 | 0 | if v5 == true { |
4719 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4720 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpmulhuw, arg0, v7); |
4721 | 0 | // Rule at src/isa/x64/inst.isle line 2778. |
4722 | 0 | return v8; |
4723 | 0 | } |
4724 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4725 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pmulhuw, arg0, v3); |
4726 | 0 | // Rule at src/isa/x64/inst.isle line 2776. |
4727 | 0 | return v4; |
4728 | 0 | } |
4729 | | |
4730 | | // Generated as internal constructor for term x64_pmuldq. |
4731 | 0 | pub fn constructor_x64_pmuldq<C: Context>( |
4732 | 0 | ctx: &mut C, |
4733 | 0 | arg0: Xmm, |
4734 | 0 | arg1: &XmmMem, |
4735 | 0 | ) -> Xmm { |
4736 | 0 | let v5 = C::use_avx_simd(ctx); |
4737 | 0 | if v5 == true { |
4738 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4739 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpmuldq, arg0, v7); |
4740 | 0 | // Rule at src/isa/x64/inst.isle line 2786. |
4741 | 0 | return v8; |
4742 | 0 | } |
4743 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4744 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pmuldq, arg0, v3); |
4745 | 0 | // Rule at src/isa/x64/inst.isle line 2784. |
4746 | 0 | return v4; |
4747 | 0 | } |
4748 | | |
4749 | | // Generated as internal constructor for term x64_pmuludq. |
4750 | 0 | pub fn constructor_x64_pmuludq<C: Context>( |
4751 | 0 | ctx: &mut C, |
4752 | 0 | arg0: Xmm, |
4753 | 0 | arg1: &XmmMem, |
4754 | 0 | ) -> Xmm { |
4755 | 0 | let v5 = C::use_avx_simd(ctx); |
4756 | 0 | if v5 == true { |
4757 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4758 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpmuludq, arg0, v7); |
4759 | 0 | // Rule at src/isa/x64/inst.isle line 2794. |
4760 | 0 | return v8; |
4761 | 0 | } |
4762 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4763 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pmuludq, arg0, v3); |
4764 | 0 | // Rule at src/isa/x64/inst.isle line 2792. |
4765 | 0 | return v4; |
4766 | 0 | } |
4767 | | |
4768 | | // Generated as internal constructor for term x64_punpckhwd. |
4769 | 0 | pub fn constructor_x64_punpckhwd<C: Context>( |
4770 | 0 | ctx: &mut C, |
4771 | 0 | arg0: Xmm, |
4772 | 0 | arg1: &XmmMem, |
4773 | 0 | ) -> Xmm { |
4774 | 0 | let v5 = C::use_avx_simd(ctx); |
4775 | 0 | if v5 == true { |
4776 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4777 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpunpckhwd, arg0, v7); |
4778 | 0 | // Rule at src/isa/x64/inst.isle line 2802. |
4779 | 0 | return v8; |
4780 | 0 | } |
4781 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4782 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Punpckhwd, arg0, v3); |
4783 | 0 | // Rule at src/isa/x64/inst.isle line 2800. |
4784 | 0 | return v4; |
4785 | 0 | } |
4786 | | |
4787 | | // Generated as internal constructor for term x64_punpcklwd. |
4788 | 0 | pub fn constructor_x64_punpcklwd<C: Context>( |
4789 | 0 | ctx: &mut C, |
4790 | 0 | arg0: Xmm, |
4791 | 0 | arg1: &XmmMem, |
4792 | 0 | ) -> Xmm { |
4793 | 0 | let v5 = C::use_avx_simd(ctx); |
4794 | 0 | if v5 == true { |
4795 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4796 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpunpcklwd, arg0, v7); |
4797 | 0 | // Rule at src/isa/x64/inst.isle line 2810. |
4798 | 0 | return v8; |
4799 | 0 | } |
4800 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4801 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Punpcklwd, arg0, v3); |
4802 | 0 | // Rule at src/isa/x64/inst.isle line 2808. |
4803 | 0 | return v4; |
4804 | 0 | } |
4805 | | |
4806 | | // Generated as internal constructor for term x64_punpckldq. |
4807 | 0 | pub fn constructor_x64_punpckldq<C: Context>( |
4808 | 0 | ctx: &mut C, |
4809 | 0 | arg0: Xmm, |
4810 | 0 | arg1: &XmmMem, |
4811 | 0 | ) -> Xmm { |
4812 | 0 | let v5 = C::use_avx_simd(ctx); |
4813 | 0 | if v5 == true { |
4814 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4815 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpunpckldq, arg0, v7); |
4816 | 0 | // Rule at src/isa/x64/inst.isle line 2818. |
4817 | 0 | return v8; |
4818 | 0 | } |
4819 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4820 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Punpckldq, arg0, v3); |
4821 | 0 | // Rule at src/isa/x64/inst.isle line 2816. |
4822 | 0 | return v4; |
4823 | 0 | } |
4824 | | |
4825 | | // Generated as internal constructor for term x64_punpckhdq. |
4826 | 0 | pub fn constructor_x64_punpckhdq<C: Context>( |
4827 | 0 | ctx: &mut C, |
4828 | 0 | arg0: Xmm, |
4829 | 0 | arg1: &XmmMem, |
4830 | 0 | ) -> Xmm { |
4831 | 0 | let v5 = C::use_avx_simd(ctx); |
4832 | 0 | if v5 == true { |
4833 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4834 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpunpckhdq, arg0, v7); |
4835 | 0 | // Rule at src/isa/x64/inst.isle line 2826. |
4836 | 0 | return v8; |
4837 | 0 | } |
4838 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4839 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Punpckhdq, arg0, v3); |
4840 | 0 | // Rule at src/isa/x64/inst.isle line 2824. |
4841 | 0 | return v4; |
4842 | 0 | } |
4843 | | |
4844 | | // Generated as internal constructor for term x64_punpcklqdq. |
4845 | 0 | pub fn constructor_x64_punpcklqdq<C: Context>( |
4846 | 0 | ctx: &mut C, |
4847 | 0 | arg0: Xmm, |
4848 | 0 | arg1: &XmmMem, |
4849 | 0 | ) -> Xmm { |
4850 | 0 | let v5 = C::use_avx_simd(ctx); |
4851 | 0 | if v5 == true { |
4852 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4853 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpunpcklqdq, arg0, v7); |
4854 | 0 | // Rule at src/isa/x64/inst.isle line 2834. |
4855 | 0 | return v8; |
4856 | 0 | } |
4857 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4858 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Punpcklqdq, arg0, v3); |
4859 | 0 | // Rule at src/isa/x64/inst.isle line 2832. |
4860 | 0 | return v4; |
4861 | 0 | } |
4862 | | |
4863 | | // Generated as internal constructor for term x64_punpckhqdq. |
4864 | 0 | pub fn constructor_x64_punpckhqdq<C: Context>( |
4865 | 0 | ctx: &mut C, |
4866 | 0 | arg0: Xmm, |
4867 | 0 | arg1: &XmmMem, |
4868 | 0 | ) -> Xmm { |
4869 | 0 | let v5 = C::use_avx_simd(ctx); |
4870 | 0 | if v5 == true { |
4871 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4872 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpunpckhqdq, arg0, v7); |
4873 | 0 | // Rule at src/isa/x64/inst.isle line 2842. |
4874 | 0 | return v8; |
4875 | 0 | } |
4876 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4877 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Punpckhqdq, arg0, v3); |
4878 | 0 | // Rule at src/isa/x64/inst.isle line 2840. |
4879 | 0 | return v4; |
4880 | 0 | } |
4881 | | |
4882 | | // Generated as internal constructor for term x64_unpcklps. |
4883 | 0 | pub fn constructor_x64_unpcklps<C: Context>( |
4884 | 0 | ctx: &mut C, |
4885 | 0 | arg0: Xmm, |
4886 | 0 | arg1: &XmmMem, |
4887 | 0 | ) -> Xmm { |
4888 | 0 | let v5 = C::use_avx_simd(ctx); |
4889 | 0 | if v5 == true { |
4890 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4891 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vunpcklps, arg0, v7); |
4892 | 0 | // Rule at src/isa/x64/inst.isle line 2850. |
4893 | 0 | return v8; |
4894 | 0 | } |
4895 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4896 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Unpcklps, arg0, v3); |
4897 | 0 | // Rule at src/isa/x64/inst.isle line 2848. |
4898 | 0 | return v4; |
4899 | 0 | } |
4900 | | |
4901 | | // Generated as internal constructor for term x64_andnps. |
4902 | 0 | pub fn constructor_x64_andnps<C: Context>( |
4903 | 0 | ctx: &mut C, |
4904 | 0 | arg0: Xmm, |
4905 | 0 | arg1: &XmmMem, |
4906 | 0 | ) -> Xmm { |
4907 | 0 | let v5 = C::use_avx_simd(ctx); |
4908 | 0 | if v5 == true { |
4909 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4910 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vandnps, arg0, v7); |
4911 | 0 | // Rule at src/isa/x64/inst.isle line 2858. |
4912 | 0 | return v8; |
4913 | 0 | } |
4914 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4915 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Andnps, arg0, v3); |
4916 | 0 | // Rule at src/isa/x64/inst.isle line 2856. |
4917 | 0 | return v4; |
4918 | 0 | } |
4919 | | |
4920 | | // Generated as internal constructor for term x64_andnpd. |
4921 | 0 | pub fn constructor_x64_andnpd<C: Context>( |
4922 | 0 | ctx: &mut C, |
4923 | 0 | arg0: Xmm, |
4924 | 0 | arg1: &XmmMem, |
4925 | 0 | ) -> Xmm { |
4926 | 0 | let v5 = C::use_avx_simd(ctx); |
4927 | 0 | if v5 == true { |
4928 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4929 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vandnpd, arg0, v7); |
4930 | 0 | // Rule at src/isa/x64/inst.isle line 2866. |
4931 | 0 | return v8; |
4932 | 0 | } |
4933 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4934 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Andnpd, arg0, v3); |
4935 | 0 | // Rule at src/isa/x64/inst.isle line 2864. |
4936 | 0 | return v4; |
4937 | 0 | } |
4938 | | |
4939 | | // Generated as internal constructor for term x64_pandn. |
4940 | 0 | pub fn constructor_x64_pandn<C: Context>( |
4941 | 0 | ctx: &mut C, |
4942 | 0 | arg0: Xmm, |
4943 | 0 | arg1: &XmmMem, |
4944 | 0 | ) -> Xmm { |
4945 | 0 | let v5 = C::use_avx_simd(ctx); |
4946 | 0 | if v5 == true { |
4947 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4948 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpandn, arg0, v7); |
4949 | 0 | // Rule at src/isa/x64/inst.isle line 2874. |
4950 | 0 | return v8; |
4951 | 0 | } |
4952 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
4953 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pandn, arg0, v3); |
4954 | 0 | // Rule at src/isa/x64/inst.isle line 2872. |
4955 | 0 | return v4; |
4956 | 0 | } |
4957 | | |
4958 | | // Generated as internal constructor for term x64_addss. |
4959 | 0 | pub fn constructor_x64_addss<C: Context>( |
4960 | 0 | ctx: &mut C, |
4961 | 0 | arg0: Xmm, |
4962 | 0 | arg1: &XmmMem, |
4963 | 0 | ) -> Xmm { |
4964 | 0 | let v4 = C::use_avx_simd(ctx); |
4965 | 0 | if v4 == true { |
4966 | 0 | let v6 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4967 | 0 | let v7 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vaddss, arg0, v6); |
4968 | 0 | // Rule at src/isa/x64/inst.isle line 2882. |
4969 | 0 | return v7; |
4970 | 0 | } |
4971 | 0 | let v3 = constructor_xmm_rm_r_unaligned(ctx, &SseOpcode::Addss, arg0, arg1); |
4972 | 0 | // Rule at src/isa/x64/inst.isle line 2880. |
4973 | 0 | return v3; |
4974 | 0 | } |
4975 | | |
4976 | | // Generated as internal constructor for term x64_addsd. |
4977 | 0 | pub fn constructor_x64_addsd<C: Context>( |
4978 | 0 | ctx: &mut C, |
4979 | 0 | arg0: Xmm, |
4980 | 0 | arg1: &XmmMem, |
4981 | 0 | ) -> Xmm { |
4982 | 0 | let v4 = C::use_avx_simd(ctx); |
4983 | 0 | if v4 == true { |
4984 | 0 | let v6 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
4985 | 0 | let v7 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vaddsd, arg0, v6); |
4986 | 0 | // Rule at src/isa/x64/inst.isle line 2890. |
4987 | 0 | return v7; |
4988 | 0 | } |
4989 | 0 | let v3 = constructor_xmm_rm_r_unaligned(ctx, &SseOpcode::Addsd, arg0, arg1); |
4990 | 0 | // Rule at src/isa/x64/inst.isle line 2888. |
4991 | 0 | return v3; |
4992 | 0 | } |
4993 | | |
4994 | | // Generated as internal constructor for term x64_addps. |
4995 | 0 | pub fn constructor_x64_addps<C: Context>( |
4996 | 0 | ctx: &mut C, |
4997 | 0 | arg0: Xmm, |
4998 | 0 | arg1: &XmmMem, |
4999 | 0 | ) -> Xmm { |
5000 | 0 | let v5 = C::use_avx_simd(ctx); |
5001 | 0 | if v5 == true { |
5002 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5003 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vaddps, arg0, v7); |
5004 | 0 | // Rule at src/isa/x64/inst.isle line 2898. |
5005 | 0 | return v8; |
5006 | 0 | } |
5007 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5008 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Addps, arg0, v3); |
5009 | 0 | // Rule at src/isa/x64/inst.isle line 2896. |
5010 | 0 | return v4; |
5011 | 0 | } |
5012 | | |
5013 | | // Generated as internal constructor for term x64_addpd. |
5014 | 0 | pub fn constructor_x64_addpd<C: Context>( |
5015 | 0 | ctx: &mut C, |
5016 | 0 | arg0: Xmm, |
5017 | 0 | arg1: &XmmMem, |
5018 | 0 | ) -> Xmm { |
5019 | 0 | let v5 = C::use_avx_simd(ctx); |
5020 | 0 | if v5 == true { |
5021 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5022 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vaddpd, arg0, v7); |
5023 | 0 | // Rule at src/isa/x64/inst.isle line 2906. |
5024 | 0 | return v8; |
5025 | 0 | } |
5026 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5027 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Addpd, arg0, v3); |
5028 | 0 | // Rule at src/isa/x64/inst.isle line 2904. |
5029 | 0 | return v4; |
5030 | 0 | } |
5031 | | |
5032 | | // Generated as internal constructor for term x64_subss. |
5033 | 0 | pub fn constructor_x64_subss<C: Context>( |
5034 | 0 | ctx: &mut C, |
5035 | 0 | arg0: Xmm, |
5036 | 0 | arg1: &XmmMem, |
5037 | 0 | ) -> Xmm { |
5038 | 0 | let v4 = C::use_avx_simd(ctx); |
5039 | 0 | if v4 == true { |
5040 | 0 | let v6 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5041 | 0 | let v7 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vsubss, arg0, v6); |
5042 | 0 | // Rule at src/isa/x64/inst.isle line 2914. |
5043 | 0 | return v7; |
5044 | 0 | } |
5045 | 0 | let v3 = constructor_xmm_rm_r_unaligned(ctx, &SseOpcode::Subss, arg0, arg1); |
5046 | 0 | // Rule at src/isa/x64/inst.isle line 2912. |
5047 | 0 | return v3; |
5048 | 0 | } |
5049 | | |
5050 | | // Generated as internal constructor for term x64_subsd. |
5051 | 0 | pub fn constructor_x64_subsd<C: Context>( |
5052 | 0 | ctx: &mut C, |
5053 | 0 | arg0: Xmm, |
5054 | 0 | arg1: &XmmMem, |
5055 | 0 | ) -> Xmm { |
5056 | 0 | let v4 = C::use_avx_simd(ctx); |
5057 | 0 | if v4 == true { |
5058 | 0 | let v6 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5059 | 0 | let v7 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vsubsd, arg0, v6); |
5060 | 0 | // Rule at src/isa/x64/inst.isle line 2922. |
5061 | 0 | return v7; |
5062 | 0 | } |
5063 | 0 | let v3 = constructor_xmm_rm_r_unaligned(ctx, &SseOpcode::Subsd, arg0, arg1); |
5064 | 0 | // Rule at src/isa/x64/inst.isle line 2920. |
5065 | 0 | return v3; |
5066 | 0 | } |
5067 | | |
5068 | | // Generated as internal constructor for term x64_subps. |
5069 | 0 | pub fn constructor_x64_subps<C: Context>( |
5070 | 0 | ctx: &mut C, |
5071 | 0 | arg0: Xmm, |
5072 | 0 | arg1: &XmmMem, |
5073 | 0 | ) -> Xmm { |
5074 | 0 | let v5 = C::use_avx_simd(ctx); |
5075 | 0 | if v5 == true { |
5076 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5077 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vsubps, arg0, v7); |
5078 | 0 | // Rule at src/isa/x64/inst.isle line 2930. |
5079 | 0 | return v8; |
5080 | 0 | } |
5081 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5082 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Subps, arg0, v3); |
5083 | 0 | // Rule at src/isa/x64/inst.isle line 2928. |
5084 | 0 | return v4; |
5085 | 0 | } |
5086 | | |
5087 | | // Generated as internal constructor for term x64_subpd. |
5088 | 0 | pub fn constructor_x64_subpd<C: Context>( |
5089 | 0 | ctx: &mut C, |
5090 | 0 | arg0: Xmm, |
5091 | 0 | arg1: &XmmMem, |
5092 | 0 | ) -> Xmm { |
5093 | 0 | let v5 = C::use_avx_simd(ctx); |
5094 | 0 | if v5 == true { |
5095 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5096 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vsubpd, arg0, v7); |
5097 | 0 | // Rule at src/isa/x64/inst.isle line 2938. |
5098 | 0 | return v8; |
5099 | 0 | } |
5100 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5101 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Subpd, arg0, v3); |
5102 | 0 | // Rule at src/isa/x64/inst.isle line 2936. |
5103 | 0 | return v4; |
5104 | 0 | } |
5105 | | |
5106 | | // Generated as internal constructor for term x64_mulss. |
5107 | 0 | pub fn constructor_x64_mulss<C: Context>( |
5108 | 0 | ctx: &mut C, |
5109 | 0 | arg0: Xmm, |
5110 | 0 | arg1: &XmmMem, |
5111 | 0 | ) -> Xmm { |
5112 | 0 | let v4 = C::use_avx_simd(ctx); |
5113 | 0 | if v4 == true { |
5114 | 0 | let v6 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5115 | 0 | let v7 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vmulss, arg0, v6); |
5116 | 0 | // Rule at src/isa/x64/inst.isle line 2946. |
5117 | 0 | return v7; |
5118 | 0 | } |
5119 | 0 | let v3 = constructor_xmm_rm_r_unaligned(ctx, &SseOpcode::Mulss, arg0, arg1); |
5120 | 0 | // Rule at src/isa/x64/inst.isle line 2944. |
5121 | 0 | return v3; |
5122 | 0 | } |
5123 | | |
5124 | | // Generated as internal constructor for term x64_mulsd. |
5125 | 0 | pub fn constructor_x64_mulsd<C: Context>( |
5126 | 0 | ctx: &mut C, |
5127 | 0 | arg0: Xmm, |
5128 | 0 | arg1: &XmmMem, |
5129 | 0 | ) -> Xmm { |
5130 | 0 | let v4 = C::use_avx_simd(ctx); |
5131 | 0 | if v4 == true { |
5132 | 0 | let v6 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5133 | 0 | let v7 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vmulsd, arg0, v6); |
5134 | 0 | // Rule at src/isa/x64/inst.isle line 2954. |
5135 | 0 | return v7; |
5136 | 0 | } |
5137 | 0 | let v3 = constructor_xmm_rm_r_unaligned(ctx, &SseOpcode::Mulsd, arg0, arg1); |
5138 | 0 | // Rule at src/isa/x64/inst.isle line 2952. |
5139 | 0 | return v3; |
5140 | 0 | } |
5141 | | |
5142 | | // Generated as internal constructor for term x64_mulps. |
5143 | 0 | pub fn constructor_x64_mulps<C: Context>( |
5144 | 0 | ctx: &mut C, |
5145 | 0 | arg0: Xmm, |
5146 | 0 | arg1: &XmmMem, |
5147 | 0 | ) -> Xmm { |
5148 | 0 | let v5 = C::use_avx_simd(ctx); |
5149 | 0 | if v5 == true { |
5150 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5151 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vmulps, arg0, v7); |
5152 | 0 | // Rule at src/isa/x64/inst.isle line 2962. |
5153 | 0 | return v8; |
5154 | 0 | } |
5155 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5156 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Mulps, arg0, v3); |
5157 | 0 | // Rule at src/isa/x64/inst.isle line 2960. |
5158 | 0 | return v4; |
5159 | 0 | } |
5160 | | |
5161 | | // Generated as internal constructor for term x64_mulpd. |
5162 | 0 | pub fn constructor_x64_mulpd<C: Context>( |
5163 | 0 | ctx: &mut C, |
5164 | 0 | arg0: Xmm, |
5165 | 0 | arg1: &XmmMem, |
5166 | 0 | ) -> Xmm { |
5167 | 0 | let v5 = C::use_avx_simd(ctx); |
5168 | 0 | if v5 == true { |
5169 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5170 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vmulpd, arg0, v7); |
5171 | 0 | // Rule at src/isa/x64/inst.isle line 2970. |
5172 | 0 | return v8; |
5173 | 0 | } |
5174 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5175 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Mulpd, arg0, v3); |
5176 | 0 | // Rule at src/isa/x64/inst.isle line 2968. |
5177 | 0 | return v4; |
5178 | 0 | } |
5179 | | |
5180 | | // Generated as internal constructor for term x64_divss. |
5181 | 0 | pub fn constructor_x64_divss<C: Context>( |
5182 | 0 | ctx: &mut C, |
5183 | 0 | arg0: Xmm, |
5184 | 0 | arg1: &XmmMem, |
5185 | 0 | ) -> Xmm { |
5186 | 0 | let v4 = C::use_avx_simd(ctx); |
5187 | 0 | if v4 == true { |
5188 | 0 | let v6 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5189 | 0 | let v7 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vdivss, arg0, v6); |
5190 | 0 | // Rule at src/isa/x64/inst.isle line 2978. |
5191 | 0 | return v7; |
5192 | 0 | } |
5193 | 0 | let v3 = constructor_xmm_rm_r_unaligned(ctx, &SseOpcode::Divss, arg0, arg1); |
5194 | 0 | // Rule at src/isa/x64/inst.isle line 2976. |
5195 | 0 | return v3; |
5196 | 0 | } |
5197 | | |
5198 | | // Generated as internal constructor for term x64_divsd. |
5199 | 0 | pub fn constructor_x64_divsd<C: Context>( |
5200 | 0 | ctx: &mut C, |
5201 | 0 | arg0: Xmm, |
5202 | 0 | arg1: &XmmMem, |
5203 | 0 | ) -> Xmm { |
5204 | 0 | let v4 = C::use_avx_simd(ctx); |
5205 | 0 | if v4 == true { |
5206 | 0 | let v6 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5207 | 0 | let v7 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vdivsd, arg0, v6); |
5208 | 0 | // Rule at src/isa/x64/inst.isle line 2986. |
5209 | 0 | return v7; |
5210 | 0 | } |
5211 | 0 | let v3 = constructor_xmm_rm_r_unaligned(ctx, &SseOpcode::Divsd, arg0, arg1); |
5212 | 0 | // Rule at src/isa/x64/inst.isle line 2984. |
5213 | 0 | return v3; |
5214 | 0 | } |
5215 | | |
5216 | | // Generated as internal constructor for term x64_divps. |
5217 | 0 | pub fn constructor_x64_divps<C: Context>( |
5218 | 0 | ctx: &mut C, |
5219 | 0 | arg0: Xmm, |
5220 | 0 | arg1: &XmmMem, |
5221 | 0 | ) -> Xmm { |
5222 | 0 | let v5 = C::use_avx_simd(ctx); |
5223 | 0 | if v5 == true { |
5224 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5225 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vdivps, arg0, v7); |
5226 | 0 | // Rule at src/isa/x64/inst.isle line 2994. |
5227 | 0 | return v8; |
5228 | 0 | } |
5229 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5230 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Divps, arg0, v3); |
5231 | 0 | // Rule at src/isa/x64/inst.isle line 2992. |
5232 | 0 | return v4; |
5233 | 0 | } |
5234 | | |
5235 | | // Generated as internal constructor for term x64_divpd. |
5236 | 0 | pub fn constructor_x64_divpd<C: Context>( |
5237 | 0 | ctx: &mut C, |
5238 | 0 | arg0: Xmm, |
5239 | 0 | arg1: &XmmMem, |
5240 | 0 | ) -> Xmm { |
5241 | 0 | let v5 = C::use_avx_simd(ctx); |
5242 | 0 | if v5 == true { |
5243 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5244 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vdivpd, arg0, v7); |
5245 | 0 | // Rule at src/isa/x64/inst.isle line 3002. |
5246 | 0 | return v8; |
5247 | 0 | } |
5248 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5249 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Divpd, arg0, v3); |
5250 | 0 | // Rule at src/isa/x64/inst.isle line 3000. |
5251 | 0 | return v4; |
5252 | 0 | } |
5253 | | |
5254 | | // Generated as internal constructor for term xmm_rm_r_blend. |
5255 | 0 | pub fn constructor_xmm_rm_r_blend<C: Context>( |
5256 | 0 | ctx: &mut C, |
5257 | 0 | arg0: &SseOpcode, |
5258 | 0 | arg1: Xmm, |
5259 | 0 | arg2: &XmmMemAligned, |
5260 | 0 | arg3: Xmm, |
5261 | 0 | ) -> Xmm { |
5262 | 0 | let v4 = C::temp_writable_xmm(ctx); |
5263 | 0 | let v5 = MInst::XmmRmRBlend { |
5264 | 0 | op: arg0.clone(), |
5265 | 0 | src1: arg1, |
5266 | 0 | src2: arg2.clone(), |
5267 | 0 | mask: arg3, |
5268 | 0 | dst: v4, |
5269 | 0 | }; |
5270 | 0 | let v6 = C::emit(ctx, &v5); |
5271 | 0 | let v7 = C::writable_xmm_to_xmm(ctx, v4); |
5272 | 0 | // Rule at src/isa/x64/inst.isle line 3008. |
5273 | 0 | return v7; |
5274 | 0 | } |
5275 | | |
5276 | | // Generated as internal constructor for term xmm_rmr_blend_vex. |
5277 | 0 | pub fn constructor_xmm_rmr_blend_vex<C: Context>( |
5278 | 0 | ctx: &mut C, |
5279 | 0 | arg0: &AvxOpcode, |
5280 | 0 | arg1: Xmm, |
5281 | 0 | arg2: &XmmMem, |
5282 | 0 | arg3: Xmm, |
5283 | 0 | ) -> Xmm { |
5284 | 0 | let v4 = C::temp_writable_xmm(ctx); |
5285 | 0 | let v5 = MInst::XmmRmRBlendVex { |
5286 | 0 | op: arg0.clone(), |
5287 | 0 | src1: arg1, |
5288 | 0 | src2: arg2.clone(), |
5289 | 0 | mask: arg3, |
5290 | 0 | dst: v4, |
5291 | 0 | }; |
5292 | 0 | let v6 = C::emit(ctx, &v5); |
5293 | 0 | let v7 = C::writable_xmm_to_xmm(ctx, v4); |
5294 | 0 | // Rule at src/isa/x64/inst.isle line 3015. |
5295 | 0 | return v7; |
5296 | 0 | } |
5297 | | |
5298 | | // Generated as internal constructor for term xmm_unary_rm_r_vex. |
5299 | 0 | pub fn constructor_xmm_unary_rm_r_vex<C: Context>( |
5300 | 0 | ctx: &mut C, |
5301 | 0 | arg0: &AvxOpcode, |
5302 | 0 | arg1: &XmmMem, |
5303 | 0 | ) -> Xmm { |
5304 | 0 | let v2 = C::temp_writable_xmm(ctx); |
5305 | 0 | let v3 = MInst::XmmUnaryRmRVex { |
5306 | 0 | op: arg0.clone(), |
5307 | 0 | src: arg1.clone(), |
5308 | 0 | dst: v2, |
5309 | 0 | }; |
5310 | 0 | let v4 = C::emit(ctx, &v3); |
5311 | 0 | let v5 = C::writable_xmm_to_xmm(ctx, v2); |
5312 | 0 | // Rule at src/isa/x64/inst.isle line 3022. |
5313 | 0 | return v5; |
5314 | 0 | } |
5315 | | |
5316 | | // Generated as internal constructor for term xmm_unary_rm_r_imm_vex. |
5317 | 0 | pub fn constructor_xmm_unary_rm_r_imm_vex<C: Context>( |
5318 | 0 | ctx: &mut C, |
5319 | 0 | arg0: &AvxOpcode, |
5320 | 0 | arg1: &XmmMem, |
5321 | 0 | arg2: u8, |
5322 | 0 | ) -> Xmm { |
5323 | 0 | let v3 = C::temp_writable_xmm(ctx); |
5324 | 0 | let v4 = MInst::XmmUnaryRmRImmVex { |
5325 | 0 | op: arg0.clone(), |
5326 | 0 | src: arg1.clone(), |
5327 | 0 | dst: v3, |
5328 | 0 | imm: arg2, |
5329 | 0 | }; |
5330 | 0 | let v5 = C::emit(ctx, &v4); |
5331 | 0 | let v6 = C::writable_xmm_to_xmm(ctx, v3); |
5332 | 0 | // Rule at src/isa/x64/inst.isle line 3029. |
5333 | 0 | return v6; |
5334 | 0 | } |
5335 | | |
5336 | | // Generated as internal constructor for term x64_blend. |
5337 | 0 | pub fn constructor_x64_blend<C: Context>( |
5338 | 0 | ctx: &mut C, |
5339 | 0 | arg0: Type, |
5340 | 0 | arg1: Xmm, |
5341 | 0 | arg2: &XmmMem, |
5342 | 0 | arg3: Xmm, |
5343 | 0 | ) -> Xmm { |
5344 | 0 | match arg0 { |
5345 | | F32X4 => { |
5346 | 0 | let v4 = constructor_x64_blendvps(ctx, arg3, arg2, arg1); |
5347 | 0 | // Rule at src/isa/x64/inst.isle line 3036. |
5348 | 0 | return v4; |
5349 | | } |
5350 | | F64X2 => { |
5351 | 0 | let v5 = constructor_x64_blendvpd(ctx, arg3, arg2, arg1); |
5352 | 0 | // Rule at src/isa/x64/inst.isle line 3037. |
5353 | 0 | return v5; |
5354 | | } |
5355 | 0 | _ => {} |
5356 | 0 | } |
5357 | 0 | let v6 = C::multi_lane(ctx, arg0); |
5358 | 0 | if let Some(v7) = v6 { |
5359 | 0 | let v10 = constructor_x64_pblendvb(ctx, arg3, arg2, arg1); |
5360 | 0 | // Rule at src/isa/x64/inst.isle line 3038. |
5361 | 0 | return v10; |
5362 | 0 | } |
5363 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "x64_blend", "src/isa/x64/inst.isle line 3035") |
5364 | 0 | } |
5365 | | |
5366 | | // Generated as internal constructor for term x64_blendvpd. |
5367 | 0 | pub fn constructor_x64_blendvpd<C: Context>( |
5368 | 0 | ctx: &mut C, |
5369 | 0 | arg0: Xmm, |
5370 | 0 | arg1: &XmmMem, |
5371 | 0 | arg2: Xmm, |
5372 | 0 | ) -> Xmm { |
5373 | 0 | let v6 = C::use_avx_simd(ctx); |
5374 | 0 | if v6 == true { |
5375 | 0 | let v8 = constructor_xmm_rmr_blend_vex(ctx, &AvxOpcode::Vblendvpd, arg0, arg1, arg2); |
5376 | 0 | // Rule at src/isa/x64/inst.isle line 3044. |
5377 | 0 | return v8; |
5378 | 0 | } |
5379 | 0 | let v4 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5380 | 0 | let v5 = constructor_xmm_rm_r_blend(ctx, &SseOpcode::Blendvpd, arg0, v4, arg2); |
5381 | 0 | // Rule at src/isa/x64/inst.isle line 3042. |
5382 | 0 | return v5; |
5383 | 0 | } |
5384 | | |
5385 | | // Generated as internal constructor for term x64_blendvps. |
5386 | 0 | pub fn constructor_x64_blendvps<C: Context>( |
5387 | 0 | ctx: &mut C, |
5388 | 0 | arg0: Xmm, |
5389 | 0 | arg1: &XmmMem, |
5390 | 0 | arg2: Xmm, |
5391 | 0 | ) -> Xmm { |
5392 | 0 | let v6 = C::use_avx_simd(ctx); |
5393 | 0 | if v6 == true { |
5394 | 0 | let v8 = constructor_xmm_rmr_blend_vex(ctx, &AvxOpcode::Vblendvps, arg0, arg1, arg2); |
5395 | 0 | // Rule at src/isa/x64/inst.isle line 3052. |
5396 | 0 | return v8; |
5397 | 0 | } |
5398 | 0 | let v4 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5399 | 0 | let v5 = constructor_xmm_rm_r_blend(ctx, &SseOpcode::Blendvps, arg0, v4, arg2); |
5400 | 0 | // Rule at src/isa/x64/inst.isle line 3050. |
5401 | 0 | return v5; |
5402 | 0 | } |
5403 | | |
5404 | | // Generated as internal constructor for term x64_pblendvb. |
5405 | 0 | pub fn constructor_x64_pblendvb<C: Context>( |
5406 | 0 | ctx: &mut C, |
5407 | 0 | arg0: Xmm, |
5408 | 0 | arg1: &XmmMem, |
5409 | 0 | arg2: Xmm, |
5410 | 0 | ) -> Xmm { |
5411 | 0 | let v6 = C::use_avx_simd(ctx); |
5412 | 0 | if v6 == true { |
5413 | 0 | let v8 = constructor_xmm_rmr_blend_vex(ctx, &AvxOpcode::Vpblendvb, arg0, arg1, arg2); |
5414 | 0 | // Rule at src/isa/x64/inst.isle line 3060. |
5415 | 0 | return v8; |
5416 | 0 | } |
5417 | 0 | let v4 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5418 | 0 | let v5 = constructor_xmm_rm_r_blend(ctx, &SseOpcode::Pblendvb, arg0, v4, arg2); |
5419 | 0 | // Rule at src/isa/x64/inst.isle line 3058. |
5420 | 0 | return v5; |
5421 | 0 | } |
5422 | | |
5423 | | // Generated as internal constructor for term x64_pblendw. |
5424 | 0 | pub fn constructor_x64_pblendw<C: Context>( |
5425 | 0 | ctx: &mut C, |
5426 | 0 | arg0: Xmm, |
5427 | 0 | arg1: &XmmMem, |
5428 | 0 | arg2: u8, |
5429 | 0 | ) -> Xmm { |
5430 | 0 | let v8 = C::use_avx_simd(ctx); |
5431 | 0 | if v8 == true { |
5432 | 0 | let v10 = constructor_xmm_rmr_imm_vex(ctx, &AvxOpcode::Vpblendw, arg0, arg1, arg2); |
5433 | 0 | // Rule at src/isa/x64/inst.isle line 3068. |
5434 | 0 | return v10; |
5435 | 0 | } |
5436 | 0 | let v4 = C::xmm_to_reg(ctx, arg0); |
5437 | 0 | let v5 = &C::xmm_mem_to_reg_mem(ctx, arg1); |
5438 | 0 | let v7 = constructor_xmm_rm_r_imm(ctx, &SseOpcode::Pblendw, v4, v5, arg2, &OperandSize::Size32); |
5439 | 0 | // Rule at src/isa/x64/inst.isle line 3066. |
5440 | 0 | return v7; |
5441 | 0 | } |
5442 | | |
5443 | | // Generated as internal constructor for term x64_movsd_regmove. |
5444 | 0 | pub fn constructor_x64_movsd_regmove<C: Context>( |
5445 | 0 | ctx: &mut C, |
5446 | 0 | arg0: Xmm, |
5447 | 0 | arg1: Xmm, |
5448 | 0 | ) -> Xmm { |
5449 | 0 | let v5 = C::use_avx_simd(ctx); |
5450 | 0 | if v5 == true { |
5451 | 0 | let v7 = &C::xmm_to_xmm_mem_imm(ctx, arg1); |
5452 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vmovsd, arg0, v7); |
5453 | 0 | // Rule at src/isa/x64/inst.isle line 3083. |
5454 | 0 | return v8; |
5455 | 0 | } |
5456 | 0 | let v3 = &C::xmm_to_xmm_mem(ctx, arg1); |
5457 | 0 | let v4 = constructor_xmm_rm_r_unaligned(ctx, &SseOpcode::Movsd, arg0, v3); |
5458 | 0 | // Rule at src/isa/x64/inst.isle line 3081. |
5459 | 0 | return v4; |
5460 | 0 | } |
5461 | | |
5462 | | // Generated as internal constructor for term x64_movlhps. |
5463 | 0 | pub fn constructor_x64_movlhps<C: Context>( |
5464 | 0 | ctx: &mut C, |
5465 | 0 | arg0: Xmm, |
5466 | 0 | arg1: &XmmMem, |
5467 | 0 | ) -> Xmm { |
5468 | 0 | let v5 = C::use_avx_simd(ctx); |
5469 | 0 | if v5 == true { |
5470 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5471 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vmovlhps, arg0, v7); |
5472 | 0 | // Rule at src/isa/x64/inst.isle line 3091. |
5473 | 0 | return v8; |
5474 | 0 | } |
5475 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5476 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Movlhps, arg0, v3); |
5477 | 0 | // Rule at src/isa/x64/inst.isle line 3089. |
5478 | 0 | return v4; |
5479 | 0 | } |
5480 | | |
5481 | | // Generated as internal constructor for term x64_pmaxs. |
5482 | 0 | pub fn constructor_x64_pmaxs<C: Context>( |
5483 | 0 | ctx: &mut C, |
5484 | 0 | arg0: Type, |
5485 | 0 | arg1: Xmm, |
5486 | 0 | arg2: &XmmMem, |
5487 | 0 | ) -> Xmm { |
5488 | 0 | match arg0 { |
5489 | | I8X16 => { |
5490 | 0 | let v3 = constructor_x64_pmaxsb(ctx, arg1, arg2); |
5491 | 0 | // Rule at src/isa/x64/inst.isle line 3097. |
5492 | 0 | return v3; |
5493 | | } |
5494 | | I16X8 => { |
5495 | 0 | let v4 = constructor_x64_pmaxsw(ctx, arg1, arg2); |
5496 | 0 | // Rule at src/isa/x64/inst.isle line 3098. |
5497 | 0 | return v4; |
5498 | | } |
5499 | | I32X4 => { |
5500 | 0 | let v5 = constructor_x64_pmaxsd(ctx, arg1, arg2); |
5501 | 0 | // Rule at src/isa/x64/inst.isle line 3099. |
5502 | 0 | return v5; |
5503 | | } |
5504 | 0 | _ => {} |
5505 | 0 | } |
5506 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "x64_pmaxs", "src/isa/x64/inst.isle line 3096") |
5507 | 0 | } |
5508 | | |
5509 | | // Generated as internal constructor for term x64_pmaxsb. |
5510 | 0 | pub fn constructor_x64_pmaxsb<C: Context>( |
5511 | 0 | ctx: &mut C, |
5512 | 0 | arg0: Xmm, |
5513 | 0 | arg1: &XmmMem, |
5514 | 0 | ) -> Xmm { |
5515 | 0 | let v5 = C::use_avx_simd(ctx); |
5516 | 0 | if v5 == true { |
5517 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5518 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpmaxsb, arg0, v7); |
5519 | 0 | // Rule at src/isa/x64/inst.isle line 3103. |
5520 | 0 | return v8; |
5521 | 0 | } |
5522 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5523 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pmaxsb, arg0, v3); |
5524 | 0 | // Rule at src/isa/x64/inst.isle line 3102. |
5525 | 0 | return v4; |
5526 | 0 | } |
5527 | | |
5528 | | // Generated as internal constructor for term x64_pmaxsw. |
5529 | 0 | pub fn constructor_x64_pmaxsw<C: Context>( |
5530 | 0 | ctx: &mut C, |
5531 | 0 | arg0: Xmm, |
5532 | 0 | arg1: &XmmMem, |
5533 | 0 | ) -> Xmm { |
5534 | 0 | let v5 = C::use_avx_simd(ctx); |
5535 | 0 | if v5 == true { |
5536 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5537 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpmaxsw, arg0, v7); |
5538 | 0 | // Rule at src/isa/x64/inst.isle line 3108. |
5539 | 0 | return v8; |
5540 | 0 | } |
5541 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5542 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pmaxsw, arg0, v3); |
5543 | 0 | // Rule at src/isa/x64/inst.isle line 3107. |
5544 | 0 | return v4; |
5545 | 0 | } |
5546 | | |
5547 | | // Generated as internal constructor for term x64_pmaxsd. |
5548 | 0 | pub fn constructor_x64_pmaxsd<C: Context>( |
5549 | 0 | ctx: &mut C, |
5550 | 0 | arg0: Xmm, |
5551 | 0 | arg1: &XmmMem, |
5552 | 0 | ) -> Xmm { |
5553 | 0 | let v5 = C::use_avx_simd(ctx); |
5554 | 0 | if v5 == true { |
5555 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5556 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpmaxsd, arg0, v7); |
5557 | 0 | // Rule at src/isa/x64/inst.isle line 3113. |
5558 | 0 | return v8; |
5559 | 0 | } |
5560 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5561 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pmaxsd, arg0, v3); |
5562 | 0 | // Rule at src/isa/x64/inst.isle line 3112. |
5563 | 0 | return v4; |
5564 | 0 | } |
5565 | | |
5566 | | // Generated as internal constructor for term x64_pmins. |
5567 | 0 | pub fn constructor_x64_pmins<C: Context>( |
5568 | 0 | ctx: &mut C, |
5569 | 0 | arg0: Type, |
5570 | 0 | arg1: Xmm, |
5571 | 0 | arg2: &XmmMem, |
5572 | 0 | ) -> Xmm { |
5573 | 0 | match arg0 { |
5574 | | I8X16 => { |
5575 | 0 | let v3 = constructor_x64_pminsb(ctx, arg1, arg2); |
5576 | 0 | // Rule at src/isa/x64/inst.isle line 3119. |
5577 | 0 | return v3; |
5578 | | } |
5579 | | I16X8 => { |
5580 | 0 | let v4 = constructor_x64_pminsw(ctx, arg1, arg2); |
5581 | 0 | // Rule at src/isa/x64/inst.isle line 3120. |
5582 | 0 | return v4; |
5583 | | } |
5584 | | I32X4 => { |
5585 | 0 | let v5 = constructor_x64_pminsd(ctx, arg1, arg2); |
5586 | 0 | // Rule at src/isa/x64/inst.isle line 3121. |
5587 | 0 | return v5; |
5588 | | } |
5589 | 0 | _ => {} |
5590 | 0 | } |
5591 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "x64_pmins", "src/isa/x64/inst.isle line 3118") |
5592 | 0 | } |
5593 | | |
5594 | | // Generated as internal constructor for term x64_pminsb. |
5595 | 0 | pub fn constructor_x64_pminsb<C: Context>( |
5596 | 0 | ctx: &mut C, |
5597 | 0 | arg0: Xmm, |
5598 | 0 | arg1: &XmmMem, |
5599 | 0 | ) -> Xmm { |
5600 | 0 | let v5 = C::use_avx_simd(ctx); |
5601 | 0 | if v5 == true { |
5602 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5603 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpminsb, arg0, v7); |
5604 | 0 | // Rule at src/isa/x64/inst.isle line 3125. |
5605 | 0 | return v8; |
5606 | 0 | } |
5607 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5608 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pminsb, arg0, v3); |
5609 | 0 | // Rule at src/isa/x64/inst.isle line 3124. |
5610 | 0 | return v4; |
5611 | 0 | } |
5612 | | |
5613 | | // Generated as internal constructor for term x64_pminsw. |
5614 | 0 | pub fn constructor_x64_pminsw<C: Context>( |
5615 | 0 | ctx: &mut C, |
5616 | 0 | arg0: Xmm, |
5617 | 0 | arg1: &XmmMem, |
5618 | 0 | ) -> Xmm { |
5619 | 0 | let v5 = C::use_avx_simd(ctx); |
5620 | 0 | if v5 == true { |
5621 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5622 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpminsw, arg0, v7); |
5623 | 0 | // Rule at src/isa/x64/inst.isle line 3130. |
5624 | 0 | return v8; |
5625 | 0 | } |
5626 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5627 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pminsw, arg0, v3); |
5628 | 0 | // Rule at src/isa/x64/inst.isle line 3129. |
5629 | 0 | return v4; |
5630 | 0 | } |
5631 | | |
5632 | | // Generated as internal constructor for term x64_pminsd. |
5633 | 0 | pub fn constructor_x64_pminsd<C: Context>( |
5634 | 0 | ctx: &mut C, |
5635 | 0 | arg0: Xmm, |
5636 | 0 | arg1: &XmmMem, |
5637 | 0 | ) -> Xmm { |
5638 | 0 | let v5 = C::use_avx_simd(ctx); |
5639 | 0 | if v5 == true { |
5640 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5641 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpminsd, arg0, v7); |
5642 | 0 | // Rule at src/isa/x64/inst.isle line 3135. |
5643 | 0 | return v8; |
5644 | 0 | } |
5645 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5646 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pminsd, arg0, v3); |
5647 | 0 | // Rule at src/isa/x64/inst.isle line 3134. |
5648 | 0 | return v4; |
5649 | 0 | } |
5650 | | |
5651 | | // Generated as internal constructor for term x64_pmaxu. |
5652 | 0 | pub fn constructor_x64_pmaxu<C: Context>( |
5653 | 0 | ctx: &mut C, |
5654 | 0 | arg0: Type, |
5655 | 0 | arg1: Xmm, |
5656 | 0 | arg2: &XmmMem, |
5657 | 0 | ) -> Xmm { |
5658 | 0 | match arg0 { |
5659 | | I8X16 => { |
5660 | 0 | let v3 = constructor_x64_pmaxub(ctx, arg1, arg2); |
5661 | 0 | // Rule at src/isa/x64/inst.isle line 3141. |
5662 | 0 | return v3; |
5663 | | } |
5664 | | I16X8 => { |
5665 | 0 | let v4 = constructor_x64_pmaxuw(ctx, arg1, arg2); |
5666 | 0 | // Rule at src/isa/x64/inst.isle line 3142. |
5667 | 0 | return v4; |
5668 | | } |
5669 | | I32X4 => { |
5670 | 0 | let v5 = constructor_x64_pmaxud(ctx, arg1, arg2); |
5671 | 0 | // Rule at src/isa/x64/inst.isle line 3143. |
5672 | 0 | return v5; |
5673 | | } |
5674 | 0 | _ => {} |
5675 | 0 | } |
5676 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "x64_pmaxu", "src/isa/x64/inst.isle line 3140") |
5677 | 0 | } |
5678 | | |
5679 | | // Generated as internal constructor for term x64_pmaxub. |
5680 | 0 | pub fn constructor_x64_pmaxub<C: Context>( |
5681 | 0 | ctx: &mut C, |
5682 | 0 | arg0: Xmm, |
5683 | 0 | arg1: &XmmMem, |
5684 | 0 | ) -> Xmm { |
5685 | 0 | let v5 = C::use_avx_simd(ctx); |
5686 | 0 | if v5 == true { |
5687 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5688 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpmaxub, arg0, v7); |
5689 | 0 | // Rule at src/isa/x64/inst.isle line 3147. |
5690 | 0 | return v8; |
5691 | 0 | } |
5692 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5693 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pmaxub, arg0, v3); |
5694 | 0 | // Rule at src/isa/x64/inst.isle line 3146. |
5695 | 0 | return v4; |
5696 | 0 | } |
5697 | | |
5698 | | // Generated as internal constructor for term x64_pmaxuw. |
5699 | 0 | pub fn constructor_x64_pmaxuw<C: Context>( |
5700 | 0 | ctx: &mut C, |
5701 | 0 | arg0: Xmm, |
5702 | 0 | arg1: &XmmMem, |
5703 | 0 | ) -> Xmm { |
5704 | 0 | let v5 = C::use_avx_simd(ctx); |
5705 | 0 | if v5 == true { |
5706 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5707 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpmaxuw, arg0, v7); |
5708 | 0 | // Rule at src/isa/x64/inst.isle line 3152. |
5709 | 0 | return v8; |
5710 | 0 | } |
5711 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5712 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pmaxuw, arg0, v3); |
5713 | 0 | // Rule at src/isa/x64/inst.isle line 3151. |
5714 | 0 | return v4; |
5715 | 0 | } |
5716 | | |
5717 | | // Generated as internal constructor for term x64_pmaxud. |
5718 | 0 | pub fn constructor_x64_pmaxud<C: Context>( |
5719 | 0 | ctx: &mut C, |
5720 | 0 | arg0: Xmm, |
5721 | 0 | arg1: &XmmMem, |
5722 | 0 | ) -> Xmm { |
5723 | 0 | let v5 = C::use_avx_simd(ctx); |
5724 | 0 | if v5 == true { |
5725 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5726 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpmaxud, arg0, v7); |
5727 | 0 | // Rule at src/isa/x64/inst.isle line 3157. |
5728 | 0 | return v8; |
5729 | 0 | } |
5730 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5731 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pmaxud, arg0, v3); |
5732 | 0 | // Rule at src/isa/x64/inst.isle line 3156. |
5733 | 0 | return v4; |
5734 | 0 | } |
5735 | | |
5736 | | // Generated as internal constructor for term x64_pminu. |
5737 | 0 | pub fn constructor_x64_pminu<C: Context>( |
5738 | 0 | ctx: &mut C, |
5739 | 0 | arg0: Type, |
5740 | 0 | arg1: Xmm, |
5741 | 0 | arg2: &XmmMem, |
5742 | 0 | ) -> Xmm { |
5743 | 0 | match arg0 { |
5744 | | I8X16 => { |
5745 | 0 | let v3 = constructor_x64_pminub(ctx, arg1, arg2); |
5746 | 0 | // Rule at src/isa/x64/inst.isle line 3163. |
5747 | 0 | return v3; |
5748 | | } |
5749 | | I16X8 => { |
5750 | 0 | let v4 = constructor_x64_pminuw(ctx, arg1, arg2); |
5751 | 0 | // Rule at src/isa/x64/inst.isle line 3164. |
5752 | 0 | return v4; |
5753 | | } |
5754 | | I32X4 => { |
5755 | 0 | let v5 = constructor_x64_pminud(ctx, arg1, arg2); |
5756 | 0 | // Rule at src/isa/x64/inst.isle line 3165. |
5757 | 0 | return v5; |
5758 | | } |
5759 | 0 | _ => {} |
5760 | 0 | } |
5761 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "x64_pminu", "src/isa/x64/inst.isle line 3162") |
5762 | 0 | } |
5763 | | |
5764 | | // Generated as internal constructor for term x64_pminub. |
5765 | 0 | pub fn constructor_x64_pminub<C: Context>( |
5766 | 0 | ctx: &mut C, |
5767 | 0 | arg0: Xmm, |
5768 | 0 | arg1: &XmmMem, |
5769 | 0 | ) -> Xmm { |
5770 | 0 | let v5 = C::use_avx_simd(ctx); |
5771 | 0 | if v5 == true { |
5772 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5773 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpminub, arg0, v7); |
5774 | 0 | // Rule at src/isa/x64/inst.isle line 3169. |
5775 | 0 | return v8; |
5776 | 0 | } |
5777 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5778 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pminub, arg0, v3); |
5779 | 0 | // Rule at src/isa/x64/inst.isle line 3168. |
5780 | 0 | return v4; |
5781 | 0 | } |
5782 | | |
5783 | | // Generated as internal constructor for term x64_pminuw. |
5784 | 0 | pub fn constructor_x64_pminuw<C: Context>( |
5785 | 0 | ctx: &mut C, |
5786 | 0 | arg0: Xmm, |
5787 | 0 | arg1: &XmmMem, |
5788 | 0 | ) -> Xmm { |
5789 | 0 | let v5 = C::use_avx_simd(ctx); |
5790 | 0 | if v5 == true { |
5791 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5792 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpminuw, arg0, v7); |
5793 | 0 | // Rule at src/isa/x64/inst.isle line 3174. |
5794 | 0 | return v8; |
5795 | 0 | } |
5796 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5797 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pminuw, arg0, v3); |
5798 | 0 | // Rule at src/isa/x64/inst.isle line 3173. |
5799 | 0 | return v4; |
5800 | 0 | } |
5801 | | |
5802 | | // Generated as internal constructor for term x64_pminud. |
5803 | 0 | pub fn constructor_x64_pminud<C: Context>( |
5804 | 0 | ctx: &mut C, |
5805 | 0 | arg0: Xmm, |
5806 | 0 | arg1: &XmmMem, |
5807 | 0 | ) -> Xmm { |
5808 | 0 | let v5 = C::use_avx_simd(ctx); |
5809 | 0 | if v5 == true { |
5810 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5811 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpminud, arg0, v7); |
5812 | 0 | // Rule at src/isa/x64/inst.isle line 3179. |
5813 | 0 | return v8; |
5814 | 0 | } |
5815 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5816 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pminud, arg0, v3); |
5817 | 0 | // Rule at src/isa/x64/inst.isle line 3178. |
5818 | 0 | return v4; |
5819 | 0 | } |
5820 | | |
5821 | | // Generated as internal constructor for term x64_punpcklbw. |
5822 | 0 | pub fn constructor_x64_punpcklbw<C: Context>( |
5823 | 0 | ctx: &mut C, |
5824 | 0 | arg0: Xmm, |
5825 | 0 | arg1: &XmmMem, |
5826 | 0 | ) -> Xmm { |
5827 | 0 | let v5 = C::use_avx_simd(ctx); |
5828 | 0 | if v5 == true { |
5829 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5830 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpunpcklbw, arg0, v7); |
5831 | 0 | // Rule at src/isa/x64/inst.isle line 3187. |
5832 | 0 | return v8; |
5833 | 0 | } |
5834 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5835 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Punpcklbw, arg0, v3); |
5836 | 0 | // Rule at src/isa/x64/inst.isle line 3185. |
5837 | 0 | return v4; |
5838 | 0 | } |
5839 | | |
5840 | | // Generated as internal constructor for term x64_punpckhbw. |
5841 | 0 | pub fn constructor_x64_punpckhbw<C: Context>( |
5842 | 0 | ctx: &mut C, |
5843 | 0 | arg0: Xmm, |
5844 | 0 | arg1: &XmmMem, |
5845 | 0 | ) -> Xmm { |
5846 | 0 | let v5 = C::use_avx_simd(ctx); |
5847 | 0 | if v5 == true { |
5848 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5849 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpunpckhbw, arg0, v7); |
5850 | 0 | // Rule at src/isa/x64/inst.isle line 3195. |
5851 | 0 | return v8; |
5852 | 0 | } |
5853 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5854 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Punpckhbw, arg0, v3); |
5855 | 0 | // Rule at src/isa/x64/inst.isle line 3193. |
5856 | 0 | return v4; |
5857 | 0 | } |
5858 | | |
5859 | | // Generated as internal constructor for term x64_packsswb. |
5860 | 0 | pub fn constructor_x64_packsswb<C: Context>( |
5861 | 0 | ctx: &mut C, |
5862 | 0 | arg0: Xmm, |
5863 | 0 | arg1: &XmmMem, |
5864 | 0 | ) -> Xmm { |
5865 | 0 | let v5 = C::use_avx_simd(ctx); |
5866 | 0 | if v5 == true { |
5867 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5868 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpacksswb, arg0, v7); |
5869 | 0 | // Rule at src/isa/x64/inst.isle line 3203. |
5870 | 0 | return v8; |
5871 | 0 | } |
5872 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5873 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Packsswb, arg0, v3); |
5874 | 0 | // Rule at src/isa/x64/inst.isle line 3201. |
5875 | 0 | return v4; |
5876 | 0 | } |
5877 | | |
5878 | | // Generated as internal constructor for term x64_packssdw. |
5879 | 0 | pub fn constructor_x64_packssdw<C: Context>( |
5880 | 0 | ctx: &mut C, |
5881 | 0 | arg0: Xmm, |
5882 | 0 | arg1: &XmmMem, |
5883 | 0 | ) -> Xmm { |
5884 | 0 | let v5 = C::use_avx_simd(ctx); |
5885 | 0 | if v5 == true { |
5886 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5887 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpackssdw, arg0, v7); |
5888 | 0 | // Rule at src/isa/x64/inst.isle line 3211. |
5889 | 0 | return v8; |
5890 | 0 | } |
5891 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5892 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Packssdw, arg0, v3); |
5893 | 0 | // Rule at src/isa/x64/inst.isle line 3209. |
5894 | 0 | return v4; |
5895 | 0 | } |
5896 | | |
5897 | | // Generated as internal constructor for term x64_packuswb. |
5898 | 0 | pub fn constructor_x64_packuswb<C: Context>( |
5899 | 0 | ctx: &mut C, |
5900 | 0 | arg0: Xmm, |
5901 | 0 | arg1: &XmmMem, |
5902 | 0 | ) -> Xmm { |
5903 | 0 | let v5 = C::use_avx_simd(ctx); |
5904 | 0 | if v5 == true { |
5905 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5906 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpackuswb, arg0, v7); |
5907 | 0 | // Rule at src/isa/x64/inst.isle line 3219. |
5908 | 0 | return v8; |
5909 | 0 | } |
5910 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5911 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Packuswb, arg0, v3); |
5912 | 0 | // Rule at src/isa/x64/inst.isle line 3217. |
5913 | 0 | return v4; |
5914 | 0 | } |
5915 | | |
5916 | | // Generated as internal constructor for term x64_packusdw. |
5917 | 0 | pub fn constructor_x64_packusdw<C: Context>( |
5918 | 0 | ctx: &mut C, |
5919 | 0 | arg0: Xmm, |
5920 | 0 | arg1: &XmmMem, |
5921 | 0 | ) -> Xmm { |
5922 | 0 | let v5 = C::use_avx_simd(ctx); |
5923 | 0 | if v5 == true { |
5924 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
5925 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpackusdw, arg0, v7); |
5926 | 0 | // Rule at src/isa/x64/inst.isle line 3227. |
5927 | 0 | return v8; |
5928 | 0 | } |
5929 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
5930 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Packusdw, arg0, v3); |
5931 | 0 | // Rule at src/isa/x64/inst.isle line 3225. |
5932 | 0 | return v4; |
5933 | 0 | } |
5934 | | |
5935 | | // Generated as internal constructor for term xmm_rm_r_imm. |
5936 | 0 | pub fn constructor_xmm_rm_r_imm<C: Context>( |
5937 | 0 | ctx: &mut C, |
5938 | 0 | arg0: &SseOpcode, |
5939 | 0 | arg1: Reg, |
5940 | 0 | arg2: &RegMem, |
5941 | 0 | arg3: u8, |
5942 | 0 | arg4: &OperandSize, |
5943 | 0 | ) -> Xmm { |
5944 | 0 | let v5 = C::temp_writable_xmm(ctx); |
5945 | 0 | let v6 = C::writable_xmm_to_reg(ctx, v5); |
5946 | 0 | let v7 = MInst::XmmRmRImm { |
5947 | 0 | op: arg0.clone(), |
5948 | 0 | src1: arg1, |
5949 | 0 | src2: arg2.clone(), |
5950 | 0 | dst: v6, |
5951 | 0 | imm: arg3, |
5952 | 0 | size: arg4.clone(), |
5953 | 0 | }; |
5954 | 0 | let v8 = C::emit(ctx, &v7); |
5955 | 0 | let v9 = C::writable_xmm_to_xmm(ctx, v5); |
5956 | 0 | // Rule at src/isa/x64/inst.isle line 3233. |
5957 | 0 | return v9; |
5958 | 0 | } |
5959 | | |
5960 | | // Generated as internal constructor for term x64_palignr. |
5961 | 0 | pub fn constructor_x64_palignr<C: Context>( |
5962 | 0 | ctx: &mut C, |
5963 | 0 | arg0: Xmm, |
5964 | 0 | arg1: &XmmMem, |
5965 | 0 | arg2: u8, |
5966 | 0 | ) -> Xmm { |
5967 | 0 | let v8 = C::use_avx_simd(ctx); |
5968 | 0 | if v8 == true { |
5969 | 0 | let v10 = constructor_xmm_rmr_imm_vex(ctx, &AvxOpcode::Vpalignr, arg0, arg1, arg2); |
5970 | 0 | // Rule at src/isa/x64/inst.isle line 3251. |
5971 | 0 | return v10; |
5972 | 0 | } |
5973 | 0 | let v4 = C::xmm_to_reg(ctx, arg0); |
5974 | 0 | let v5 = &C::xmm_mem_to_reg_mem(ctx, arg1); |
5975 | 0 | let v7 = constructor_xmm_rm_r_imm(ctx, &SseOpcode::Palignr, v4, v5, arg2, &OperandSize::Size32); |
5976 | 0 | // Rule at src/isa/x64/inst.isle line 3245. |
5977 | 0 | return v7; |
5978 | 0 | } |
5979 | | |
5980 | | // Generated as internal constructor for term x64_cmpp. |
5981 | 0 | pub fn constructor_x64_cmpp<C: Context>( |
5982 | 0 | ctx: &mut C, |
5983 | 0 | arg0: Type, |
5984 | 0 | arg1: Xmm, |
5985 | 0 | arg2: &XmmMem, |
5986 | 0 | arg3: &FcmpImm, |
5987 | 0 | ) -> Xmm { |
5988 | 0 | match arg0 { |
5989 | | F32X4 => { |
5990 | 0 | let v4 = constructor_x64_cmpps(ctx, arg1, arg2, arg3); |
5991 | 0 | // Rule at src/isa/x64/inst.isle line 3257. |
5992 | 0 | return v4; |
5993 | | } |
5994 | | F64X2 => { |
5995 | 0 | let v5 = constructor_x64_cmppd(ctx, arg1, arg2, arg3); |
5996 | 0 | // Rule at src/isa/x64/inst.isle line 3258. |
5997 | 0 | return v5; |
5998 | | } |
5999 | 0 | _ => {} |
6000 | 0 | } |
6001 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "x64_cmpp", "src/isa/x64/inst.isle line 3256") |
6002 | 0 | } |
6003 | | |
6004 | | // Generated as internal constructor for term x64_cmpps. |
6005 | 0 | pub fn constructor_x64_cmpps<C: Context>( |
6006 | 0 | ctx: &mut C, |
6007 | 0 | arg0: Xmm, |
6008 | 0 | arg1: &XmmMem, |
6009 | 0 | arg2: &FcmpImm, |
6010 | 0 | ) -> Xmm { |
6011 | 0 | let v9 = C::use_avx_simd(ctx); |
6012 | 0 | if v9 == true { |
6013 | 0 | let v11 = C::encode_fcmp_imm(ctx, arg2); |
6014 | 0 | let v12 = constructor_xmm_rmr_imm_vex(ctx, &AvxOpcode::Vcmpps, arg0, arg1, v11); |
6015 | 0 | // Rule at src/isa/x64/inst.isle line 3267. |
6016 | 0 | return v12; |
6017 | 0 | } |
6018 | 0 | let v4 = C::xmm_to_reg(ctx, arg0); |
6019 | 0 | let v5 = &C::xmm_mem_to_reg_mem(ctx, arg1); |
6020 | 0 | let v6 = C::encode_fcmp_imm(ctx, arg2); |
6021 | 0 | let v8 = constructor_xmm_rm_r_imm(ctx, &SseOpcode::Cmpps, v4, v5, v6, &OperandSize::Size32); |
6022 | 0 | // Rule at src/isa/x64/inst.isle line 3261. |
6023 | 0 | return v8; |
6024 | 0 | } |
6025 | | |
6026 | | // Generated as internal constructor for term x64_cmppd. |
6027 | 0 | pub fn constructor_x64_cmppd<C: Context>( |
6028 | 0 | ctx: &mut C, |
6029 | 0 | arg0: Xmm, |
6030 | 0 | arg1: &XmmMem, |
6031 | 0 | arg2: &FcmpImm, |
6032 | 0 | ) -> Xmm { |
6033 | 0 | let v9 = C::use_avx_simd(ctx); |
6034 | 0 | if v9 == true { |
6035 | 0 | let v11 = C::encode_fcmp_imm(ctx, arg2); |
6036 | 0 | let v12 = constructor_xmm_rmr_imm_vex(ctx, &AvxOpcode::Vcmppd, arg0, arg1, v11); |
6037 | 0 | // Rule at src/isa/x64/inst.isle line 3284. |
6038 | 0 | return v12; |
6039 | 0 | } |
6040 | 0 | let v4 = C::xmm_to_reg(ctx, arg0); |
6041 | 0 | let v5 = &C::xmm_mem_to_reg_mem(ctx, arg1); |
6042 | 0 | let v6 = C::encode_fcmp_imm(ctx, arg2); |
6043 | 0 | let v8 = constructor_xmm_rm_r_imm(ctx, &SseOpcode::Cmppd, v4, v5, v6, &OperandSize::Size32); |
6044 | 0 | // Rule at src/isa/x64/inst.isle line 3278. |
6045 | 0 | return v8; |
6046 | 0 | } |
6047 | | |
6048 | | // Generated as internal constructor for term x64_pinsrb. |
6049 | 0 | pub fn constructor_x64_pinsrb<C: Context>( |
6050 | 0 | ctx: &mut C, |
6051 | 0 | arg0: Xmm, |
6052 | 0 | arg1: &GprMem, |
6053 | 0 | arg2: u8, |
6054 | 0 | ) -> Xmm { |
6055 | 0 | let v8 = C::use_avx_simd(ctx); |
6056 | 0 | if v8 == true { |
6057 | 0 | let v10 = constructor_xmm_vex_pinsr(ctx, &AvxOpcode::Vpinsrb, arg0, arg1, arg2); |
6058 | 0 | // Rule at src/isa/x64/inst.isle line 3299. |
6059 | 0 | return v10; |
6060 | 0 | } |
6061 | 0 | let v4 = C::xmm_to_reg(ctx, arg0); |
6062 | 0 | let v5 = &C::gpr_mem_to_reg_mem(ctx, arg1); |
6063 | 0 | let v7 = constructor_xmm_rm_r_imm(ctx, &SseOpcode::Pinsrb, v4, v5, arg2, &OperandSize::Size32); |
6064 | 0 | // Rule at src/isa/x64/inst.isle line 3293. |
6065 | 0 | return v7; |
6066 | 0 | } |
6067 | | |
6068 | | // Generated as internal constructor for term x64_pinsrw. |
6069 | 0 | pub fn constructor_x64_pinsrw<C: Context>( |
6070 | 0 | ctx: &mut C, |
6071 | 0 | arg0: Xmm, |
6072 | 0 | arg1: &GprMem, |
6073 | 0 | arg2: u8, |
6074 | 0 | ) -> Xmm { |
6075 | 0 | let v8 = C::use_avx_simd(ctx); |
6076 | 0 | if v8 == true { |
6077 | 0 | let v10 = constructor_xmm_vex_pinsr(ctx, &AvxOpcode::Vpinsrw, arg0, arg1, arg2); |
6078 | 0 | // Rule at src/isa/x64/inst.isle line 3311. |
6079 | 0 | return v10; |
6080 | 0 | } |
6081 | 0 | let v4 = C::xmm_to_reg(ctx, arg0); |
6082 | 0 | let v5 = &C::gpr_mem_to_reg_mem(ctx, arg1); |
6083 | 0 | let v7 = constructor_xmm_rm_r_imm(ctx, &SseOpcode::Pinsrw, v4, v5, arg2, &OperandSize::Size32); |
6084 | 0 | // Rule at src/isa/x64/inst.isle line 3305. |
6085 | 0 | return v7; |
6086 | 0 | } |
6087 | | |
6088 | | // Generated as internal constructor for term x64_pinsrd. |
6089 | 0 | pub fn constructor_x64_pinsrd<C: Context>( |
6090 | 0 | ctx: &mut C, |
6091 | 0 | arg0: Xmm, |
6092 | 0 | arg1: &GprMem, |
6093 | 0 | arg2: u8, |
6094 | 0 | ) -> Xmm { |
6095 | 0 | let v8 = C::use_avx_simd(ctx); |
6096 | 0 | if v8 == true { |
6097 | 0 | let v10 = constructor_xmm_vex_pinsr(ctx, &AvxOpcode::Vpinsrd, arg0, arg1, arg2); |
6098 | 0 | // Rule at src/isa/x64/inst.isle line 3323. |
6099 | 0 | return v10; |
6100 | 0 | } |
6101 | 0 | let v4 = C::xmm_to_reg(ctx, arg0); |
6102 | 0 | let v5 = &C::gpr_mem_to_reg_mem(ctx, arg1); |
6103 | 0 | let v7 = constructor_xmm_rm_r_imm(ctx, &SseOpcode::Pinsrd, v4, v5, arg2, &OperandSize::Size32); |
6104 | 0 | // Rule at src/isa/x64/inst.isle line 3317. |
6105 | 0 | return v7; |
6106 | 0 | } |
6107 | | |
6108 | | // Generated as internal constructor for term x64_pinsrq. |
6109 | 0 | pub fn constructor_x64_pinsrq<C: Context>( |
6110 | 0 | ctx: &mut C, |
6111 | 0 | arg0: Xmm, |
6112 | 0 | arg1: &GprMem, |
6113 | 0 | arg2: u8, |
6114 | 0 | ) -> Xmm { |
6115 | 0 | let v8 = C::use_avx_simd(ctx); |
6116 | 0 | if v8 == true { |
6117 | 0 | let v10 = constructor_xmm_vex_pinsr(ctx, &AvxOpcode::Vpinsrq, arg0, arg1, arg2); |
6118 | 0 | // Rule at src/isa/x64/inst.isle line 3335. |
6119 | 0 | return v10; |
6120 | 0 | } |
6121 | 0 | let v4 = C::xmm_to_reg(ctx, arg0); |
6122 | 0 | let v5 = &C::gpr_mem_to_reg_mem(ctx, arg1); |
6123 | 0 | let v7 = constructor_xmm_rm_r_imm(ctx, &SseOpcode::Pinsrd, v4, v5, arg2, &OperandSize::Size64); |
6124 | 0 | // Rule at src/isa/x64/inst.isle line 3329. |
6125 | 0 | return v7; |
6126 | 0 | } |
6127 | | |
6128 | | // Generated as internal constructor for term xmm_vex_pinsr. |
6129 | 0 | pub fn constructor_xmm_vex_pinsr<C: Context>( |
6130 | 0 | ctx: &mut C, |
6131 | 0 | arg0: &AvxOpcode, |
6132 | 0 | arg1: Xmm, |
6133 | 0 | arg2: &GprMem, |
6134 | 0 | arg3: u8, |
6135 | 0 | ) -> Xmm { |
6136 | 0 | let v4 = C::temp_writable_xmm(ctx); |
6137 | 0 | let v5 = MInst::XmmVexPinsr { |
6138 | 0 | op: arg0.clone(), |
6139 | 0 | src1: arg1, |
6140 | 0 | src2: arg2.clone(), |
6141 | 0 | dst: v4, |
6142 | 0 | imm: arg3, |
6143 | 0 | }; |
6144 | 0 | let v6 = C::emit(ctx, &v5); |
6145 | 0 | let v7 = C::writable_xmm_to_xmm(ctx, v4); |
6146 | 0 | // Rule at src/isa/x64/inst.isle line 3341. |
6147 | 0 | return v7; |
6148 | 0 | } |
6149 | | |
6150 | | // Generated as internal constructor for term xmm_unary_rm_r_imm. |
6151 | 0 | pub fn constructor_xmm_unary_rm_r_imm<C: Context>( |
6152 | 0 | ctx: &mut C, |
6153 | 0 | arg0: &SseOpcode, |
6154 | 0 | arg1: &XmmMemAligned, |
6155 | 0 | arg2: u8, |
6156 | 0 | ) -> Xmm { |
6157 | 0 | let v3 = C::temp_writable_xmm(ctx); |
6158 | 0 | let v4 = MInst::XmmUnaryRmRImm { |
6159 | 0 | op: arg0.clone(), |
6160 | 0 | src: arg1.clone(), |
6161 | 0 | imm: arg2, |
6162 | 0 | dst: v3, |
6163 | 0 | }; |
6164 | 0 | let v5 = C::emit(ctx, &v4); |
6165 | 0 | let v6 = C::writable_xmm_to_xmm(ctx, v3); |
6166 | 0 | // Rule at src/isa/x64/inst.isle line 3348. |
6167 | 0 | return v6; |
6168 | 0 | } |
6169 | | |
6170 | | // Generated as internal constructor for term x64_roundss. |
6171 | 0 | pub fn constructor_x64_roundss<C: Context>( |
6172 | 0 | ctx: &mut C, |
6173 | 0 | arg0: &XmmMem, |
6174 | 0 | arg1: &RoundImm, |
6175 | 0 | ) -> Xmm { |
6176 | 0 | let v6 = C::use_avx_simd(ctx); |
6177 | 0 | if v6 == true { |
6178 | 0 | let v8 = C::encode_round_imm(ctx, arg1); |
6179 | 0 | let v9 = constructor_xmm_unary_rm_r_imm_vex(ctx, &AvxOpcode::Vroundss, arg0, v8); |
6180 | 0 | // Rule at src/isa/x64/inst.isle line 3357. |
6181 | 0 | return v9; |
6182 | 0 | } |
6183 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg0); |
6184 | 0 | let v4 = C::encode_round_imm(ctx, arg1); |
6185 | 0 | let v5 = constructor_xmm_unary_rm_r_imm(ctx, &SseOpcode::Roundss, v3, v4); |
6186 | 0 | // Rule at src/isa/x64/inst.isle line 3355. |
6187 | 0 | return v5; |
6188 | 0 | } |
6189 | | |
6190 | | // Generated as internal constructor for term x64_roundsd. |
6191 | 0 | pub fn constructor_x64_roundsd<C: Context>( |
6192 | 0 | ctx: &mut C, |
6193 | 0 | arg0: &XmmMem, |
6194 | 0 | arg1: &RoundImm, |
6195 | 0 | ) -> Xmm { |
6196 | 0 | let v6 = C::use_avx_simd(ctx); |
6197 | 0 | if v6 == true { |
6198 | 0 | let v8 = C::encode_round_imm(ctx, arg1); |
6199 | 0 | let v9 = constructor_xmm_unary_rm_r_imm_vex(ctx, &AvxOpcode::Vroundsd, arg0, v8); |
6200 | 0 | // Rule at src/isa/x64/inst.isle line 3365. |
6201 | 0 | return v9; |
6202 | 0 | } |
6203 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg0); |
6204 | 0 | let v4 = C::encode_round_imm(ctx, arg1); |
6205 | 0 | let v5 = constructor_xmm_unary_rm_r_imm(ctx, &SseOpcode::Roundsd, v3, v4); |
6206 | 0 | // Rule at src/isa/x64/inst.isle line 3363. |
6207 | 0 | return v5; |
6208 | 0 | } |
6209 | | |
6210 | | // Generated as internal constructor for term x64_roundps. |
6211 | 0 | pub fn constructor_x64_roundps<C: Context>( |
6212 | 0 | ctx: &mut C, |
6213 | 0 | arg0: &XmmMem, |
6214 | 0 | arg1: &RoundImm, |
6215 | 0 | ) -> Xmm { |
6216 | 0 | let v6 = C::use_avx_simd(ctx); |
6217 | 0 | if v6 == true { |
6218 | 0 | let v8 = C::encode_round_imm(ctx, arg1); |
6219 | 0 | let v9 = constructor_xmm_unary_rm_r_imm_vex(ctx, &AvxOpcode::Vroundps, arg0, v8); |
6220 | 0 | // Rule at src/isa/x64/inst.isle line 3373. |
6221 | 0 | return v9; |
6222 | 0 | } |
6223 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg0); |
6224 | 0 | let v4 = C::encode_round_imm(ctx, arg1); |
6225 | 0 | let v5 = constructor_xmm_unary_rm_r_imm(ctx, &SseOpcode::Roundps, v3, v4); |
6226 | 0 | // Rule at src/isa/x64/inst.isle line 3371. |
6227 | 0 | return v5; |
6228 | 0 | } |
6229 | | |
6230 | | // Generated as internal constructor for term x64_roundpd. |
6231 | 0 | pub fn constructor_x64_roundpd<C: Context>( |
6232 | 0 | ctx: &mut C, |
6233 | 0 | arg0: &XmmMem, |
6234 | 0 | arg1: &RoundImm, |
6235 | 0 | ) -> Xmm { |
6236 | 0 | let v6 = C::use_avx_simd(ctx); |
6237 | 0 | if v6 == true { |
6238 | 0 | let v8 = C::encode_round_imm(ctx, arg1); |
6239 | 0 | let v9 = constructor_xmm_unary_rm_r_imm_vex(ctx, &AvxOpcode::Vroundpd, arg0, v8); |
6240 | 0 | // Rule at src/isa/x64/inst.isle line 3381. |
6241 | 0 | return v9; |
6242 | 0 | } |
6243 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg0); |
6244 | 0 | let v4 = C::encode_round_imm(ctx, arg1); |
6245 | 0 | let v5 = constructor_xmm_unary_rm_r_imm(ctx, &SseOpcode::Roundpd, v3, v4); |
6246 | 0 | // Rule at src/isa/x64/inst.isle line 3379. |
6247 | 0 | return v5; |
6248 | 0 | } |
6249 | | |
6250 | | // Generated as internal constructor for term x64_pmaddwd. |
6251 | 0 | pub fn constructor_x64_pmaddwd<C: Context>( |
6252 | 0 | ctx: &mut C, |
6253 | 0 | arg0: Xmm, |
6254 | 0 | arg1: &XmmMem, |
6255 | 0 | ) -> Xmm { |
6256 | 0 | let v5 = C::use_avx_simd(ctx); |
6257 | 0 | if v5 == true { |
6258 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
6259 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpmaddwd, arg0, v7); |
6260 | 0 | // Rule at src/isa/x64/inst.isle line 3389. |
6261 | 0 | return v8; |
6262 | 0 | } |
6263 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
6264 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pmaddwd, arg0, v3); |
6265 | 0 | // Rule at src/isa/x64/inst.isle line 3387. |
6266 | 0 | return v4; |
6267 | 0 | } |
6268 | | |
6269 | | // Generated as internal constructor for term x64_pmaddubsw. |
6270 | 0 | pub fn constructor_x64_pmaddubsw<C: Context>( |
6271 | 0 | ctx: &mut C, |
6272 | 0 | arg0: Xmm, |
6273 | 0 | arg1: &XmmMem, |
6274 | 0 | ) -> Xmm { |
6275 | 0 | let v5 = C::use_avx_simd(ctx); |
6276 | 0 | if v5 == true { |
6277 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
6278 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpmaddubsw, arg0, v7); |
6279 | 0 | // Rule at src/isa/x64/inst.isle line 3396. |
6280 | 0 | return v8; |
6281 | 0 | } |
6282 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
6283 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pmaddubsw, arg0, v3); |
6284 | 0 | // Rule at src/isa/x64/inst.isle line 3394. |
6285 | 0 | return v4; |
6286 | 0 | } |
6287 | | |
6288 | | // Generated as internal constructor for term x64_insertps. |
6289 | 0 | pub fn constructor_x64_insertps<C: Context>( |
6290 | 0 | ctx: &mut C, |
6291 | 0 | arg0: Xmm, |
6292 | 0 | arg1: &XmmMem, |
6293 | 0 | arg2: u8, |
6294 | 0 | ) -> Xmm { |
6295 | 0 | let v8 = C::use_avx_simd(ctx); |
6296 | 0 | if v8 == true { |
6297 | 0 | let v10 = constructor_xmm_rmr_imm_vex(ctx, &AvxOpcode::Vinsertps, arg0, arg1, arg2); |
6298 | 0 | // Rule at src/isa/x64/inst.isle line 3408. |
6299 | 0 | return v10; |
6300 | 0 | } |
6301 | 0 | let v4 = C::xmm_to_reg(ctx, arg0); |
6302 | 0 | let v5 = &C::xmm_mem_to_reg_mem(ctx, arg1); |
6303 | 0 | let v7 = constructor_xmm_rm_r_imm(ctx, &SseOpcode::Insertps, v4, v5, arg2, &OperandSize::Size32); |
6304 | 0 | // Rule at src/isa/x64/inst.isle line 3402. |
6305 | 0 | return v7; |
6306 | 0 | } |
6307 | | |
6308 | | // Generated as internal constructor for term x64_pshufd. |
6309 | 0 | pub fn constructor_x64_pshufd<C: Context>( |
6310 | 0 | ctx: &mut C, |
6311 | 0 | arg0: &XmmMem, |
6312 | 0 | arg1: u8, |
6313 | 0 | ) -> Xmm { |
6314 | 0 | let v5 = C::use_avx_simd(ctx); |
6315 | 0 | if v5 == true { |
6316 | 0 | let v7 = constructor_xmm_unary_rm_r_imm_vex(ctx, &AvxOpcode::Vpshufd, arg0, arg1); |
6317 | 0 | // Rule at src/isa/x64/inst.isle line 3416. |
6318 | 0 | return v7; |
6319 | 0 | } |
6320 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg0); |
6321 | 0 | let v4 = constructor_xmm_unary_rm_r_imm(ctx, &SseOpcode::Pshufd, v3, arg1); |
6322 | 0 | // Rule at src/isa/x64/inst.isle line 3414. |
6323 | 0 | return v4; |
6324 | 0 | } |
6325 | | |
6326 | | // Generated as internal constructor for term x64_pshufb. |
6327 | 0 | pub fn constructor_x64_pshufb<C: Context>( |
6328 | 0 | ctx: &mut C, |
6329 | 0 | arg0: Xmm, |
6330 | 0 | arg1: &XmmMem, |
6331 | 0 | ) -> Xmm { |
6332 | 0 | let v5 = C::use_avx_simd(ctx); |
6333 | 0 | if v5 == true { |
6334 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
6335 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpshufb, arg0, v7); |
6336 | 0 | // Rule at src/isa/x64/inst.isle line 3424. |
6337 | 0 | return v8; |
6338 | 0 | } |
6339 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
6340 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pshufb, arg0, v3); |
6341 | 0 | // Rule at src/isa/x64/inst.isle line 3422. |
6342 | 0 | return v4; |
6343 | 0 | } |
6344 | | |
6345 | | // Generated as internal constructor for term x64_pshuflw. |
6346 | 0 | pub fn constructor_x64_pshuflw<C: Context>( |
6347 | 0 | ctx: &mut C, |
6348 | 0 | arg0: &XmmMem, |
6349 | 0 | arg1: u8, |
6350 | 0 | ) -> Xmm { |
6351 | 0 | let v5 = C::use_avx_simd(ctx); |
6352 | 0 | if v5 == true { |
6353 | 0 | let v7 = constructor_xmm_unary_rm_r_imm_vex(ctx, &AvxOpcode::Vpshuflw, arg0, arg1); |
6354 | 0 | // Rule at src/isa/x64/inst.isle line 3432. |
6355 | 0 | return v7; |
6356 | 0 | } |
6357 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg0); |
6358 | 0 | let v4 = constructor_xmm_unary_rm_r_imm(ctx, &SseOpcode::Pshuflw, v3, arg1); |
6359 | 0 | // Rule at src/isa/x64/inst.isle line 3430. |
6360 | 0 | return v4; |
6361 | 0 | } |
6362 | | |
6363 | | // Generated as internal constructor for term x64_pshufhw. |
6364 | 0 | pub fn constructor_x64_pshufhw<C: Context>( |
6365 | 0 | ctx: &mut C, |
6366 | 0 | arg0: &XmmMem, |
6367 | 0 | arg1: u8, |
6368 | 0 | ) -> Xmm { |
6369 | 0 | let v5 = C::use_avx_simd(ctx); |
6370 | 0 | if v5 == true { |
6371 | 0 | let v7 = constructor_xmm_unary_rm_r_imm_vex(ctx, &AvxOpcode::Vpshufhw, arg0, arg1); |
6372 | 0 | // Rule at src/isa/x64/inst.isle line 3440. |
6373 | 0 | return v7; |
6374 | 0 | } |
6375 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg0); |
6376 | 0 | let v4 = constructor_xmm_unary_rm_r_imm(ctx, &SseOpcode::Pshufhw, v3, arg1); |
6377 | 0 | // Rule at src/isa/x64/inst.isle line 3438. |
6378 | 0 | return v4; |
6379 | 0 | } |
6380 | | |
6381 | | // Generated as internal constructor for term x64_shufps. |
6382 | 0 | pub fn constructor_x64_shufps<C: Context>( |
6383 | 0 | ctx: &mut C, |
6384 | 0 | arg0: Xmm, |
6385 | 0 | arg1: &XmmMem, |
6386 | 0 | arg2: u8, |
6387 | 0 | ) -> Xmm { |
6388 | 0 | let v8 = C::use_avx_simd(ctx); |
6389 | 0 | if v8 == true { |
6390 | 0 | let v10 = constructor_xmm_rmr_imm_vex(ctx, &AvxOpcode::Vshufps, arg0, arg1, arg2); |
6391 | 0 | // Rule at src/isa/x64/inst.isle line 3452. |
6392 | 0 | return v10; |
6393 | 0 | } |
6394 | 0 | let v4 = C::xmm_to_reg(ctx, arg0); |
6395 | 0 | let v5 = &C::xmm_mem_to_reg_mem(ctx, arg1); |
6396 | 0 | let v7 = constructor_xmm_rm_r_imm(ctx, &SseOpcode::Shufps, v4, v5, arg2, &OperandSize::Size32); |
6397 | 0 | // Rule at src/isa/x64/inst.isle line 3446. |
6398 | 0 | return v7; |
6399 | 0 | } |
6400 | | |
6401 | | // Generated as internal constructor for term xmm_unary_rm_r. |
6402 | 0 | pub fn constructor_xmm_unary_rm_r<C: Context>( |
6403 | 0 | ctx: &mut C, |
6404 | 0 | arg0: &SseOpcode, |
6405 | 0 | arg1: &XmmMemAligned, |
6406 | 0 | ) -> Xmm { |
6407 | 0 | let v2 = C::temp_writable_xmm(ctx); |
6408 | 0 | let v3 = MInst::XmmUnaryRmR { |
6409 | 0 | op: arg0.clone(), |
6410 | 0 | src: arg1.clone(), |
6411 | 0 | dst: v2, |
6412 | 0 | }; |
6413 | 0 | let v4 = C::emit(ctx, &v3); |
6414 | 0 | let v5 = C::writable_xmm_to_xmm(ctx, v2); |
6415 | 0 | // Rule at src/isa/x64/inst.isle line 3458. |
6416 | 0 | return v5; |
6417 | 0 | } |
6418 | | |
6419 | | // Generated as internal constructor for term xmm_unary_rm_r_unaligned. |
6420 | 0 | pub fn constructor_xmm_unary_rm_r_unaligned<C: Context>( |
6421 | 0 | ctx: &mut C, |
6422 | 0 | arg0: &SseOpcode, |
6423 | 0 | arg1: &XmmMem, |
6424 | 0 | ) -> Xmm { |
6425 | 0 | let v2 = C::temp_writable_xmm(ctx); |
6426 | 0 | let v3 = MInst::XmmUnaryRmRUnaligned { |
6427 | 0 | op: arg0.clone(), |
6428 | 0 | src: arg1.clone(), |
6429 | 0 | dst: v2, |
6430 | 0 | }; |
6431 | 0 | let v4 = C::emit(ctx, &v3); |
6432 | 0 | let v5 = C::writable_xmm_to_xmm(ctx, v2); |
6433 | 0 | // Rule at src/isa/x64/inst.isle line 3465. |
6434 | 0 | return v5; |
6435 | 0 | } |
6436 | | |
6437 | | // Generated as internal constructor for term x64_pabsb. |
6438 | 0 | pub fn constructor_x64_pabsb<C: Context>( |
6439 | 0 | ctx: &mut C, |
6440 | 0 | arg0: &XmmMem, |
6441 | 0 | ) -> Xmm { |
6442 | 0 | let v4 = C::use_avx_simd(ctx); |
6443 | 0 | if v4 == true { |
6444 | 0 | let v6 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vpabsb, arg0); |
6445 | 0 | // Rule at src/isa/x64/inst.isle line 3474. |
6446 | 0 | return v6; |
6447 | 0 | } |
6448 | 0 | let v2 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg0); |
6449 | 0 | let v3 = constructor_xmm_unary_rm_r(ctx, &SseOpcode::Pabsb, v2); |
6450 | 0 | // Rule at src/isa/x64/inst.isle line 3472. |
6451 | 0 | return v3; |
6452 | 0 | } |
6453 | | |
6454 | | // Generated as internal constructor for term x64_pabsw. |
6455 | 0 | pub fn constructor_x64_pabsw<C: Context>( |
6456 | 0 | ctx: &mut C, |
6457 | 0 | arg0: &XmmMem, |
6458 | 0 | ) -> Xmm { |
6459 | 0 | let v4 = C::use_avx_simd(ctx); |
6460 | 0 | if v4 == true { |
6461 | 0 | let v6 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vpabsw, arg0); |
6462 | 0 | // Rule at src/isa/x64/inst.isle line 3482. |
6463 | 0 | return v6; |
6464 | 0 | } |
6465 | 0 | let v2 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg0); |
6466 | 0 | let v3 = constructor_xmm_unary_rm_r(ctx, &SseOpcode::Pabsw, v2); |
6467 | 0 | // Rule at src/isa/x64/inst.isle line 3480. |
6468 | 0 | return v3; |
6469 | 0 | } |
6470 | | |
6471 | | // Generated as internal constructor for term x64_pabsd. |
6472 | 0 | pub fn constructor_x64_pabsd<C: Context>( |
6473 | 0 | ctx: &mut C, |
6474 | 0 | arg0: &XmmMem, |
6475 | 0 | ) -> Xmm { |
6476 | 0 | let v4 = C::use_avx_simd(ctx); |
6477 | 0 | if v4 == true { |
6478 | 0 | let v6 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vpabsd, arg0); |
6479 | 0 | // Rule at src/isa/x64/inst.isle line 3490. |
6480 | 0 | return v6; |
6481 | 0 | } |
6482 | 0 | let v2 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg0); |
6483 | 0 | let v3 = constructor_xmm_unary_rm_r(ctx, &SseOpcode::Pabsd, v2); |
6484 | 0 | // Rule at src/isa/x64/inst.isle line 3488. |
6485 | 0 | return v3; |
6486 | 0 | } |
6487 | | |
6488 | | // Generated as internal constructor for term xmm_unary_rm_r_evex. |
6489 | 0 | pub fn constructor_xmm_unary_rm_r_evex<C: Context>( |
6490 | 0 | ctx: &mut C, |
6491 | 0 | arg0: &Avx512Opcode, |
6492 | 0 | arg1: &XmmMem, |
6493 | 0 | ) -> Xmm { |
6494 | 0 | let v2 = C::temp_writable_xmm(ctx); |
6495 | 0 | let v3 = MInst::XmmUnaryRmREvex { |
6496 | 0 | op: arg0.clone(), |
6497 | 0 | src: arg1.clone(), |
6498 | 0 | dst: v2, |
6499 | 0 | }; |
6500 | 0 | let v4 = C::emit(ctx, &v3); |
6501 | 0 | let v5 = C::writable_xmm_to_xmm(ctx, v2); |
6502 | 0 | // Rule at src/isa/x64/inst.isle line 3496. |
6503 | 0 | return v5; |
6504 | 0 | } |
6505 | | |
6506 | | // Generated as internal constructor for term x64_vcvtudq2ps. |
6507 | 0 | pub fn constructor_x64_vcvtudq2ps<C: Context>( |
6508 | 0 | ctx: &mut C, |
6509 | 0 | arg0: &XmmMem, |
6510 | 0 | ) -> Xmm { |
6511 | 0 | let v2 = constructor_xmm_unary_rm_r_evex(ctx, &Avx512Opcode::Vcvtudq2ps, arg0); |
6512 | 0 | // Rule at src/isa/x64/inst.isle line 3503. |
6513 | 0 | return v2; |
6514 | 0 | } |
6515 | | |
6516 | | // Generated as internal constructor for term x64_vpabsq. |
6517 | 0 | pub fn constructor_x64_vpabsq<C: Context>( |
6518 | 0 | ctx: &mut C, |
6519 | 0 | arg0: &XmmMem, |
6520 | 0 | ) -> Xmm { |
6521 | 0 | let v2 = constructor_xmm_unary_rm_r_evex(ctx, &Avx512Opcode::Vpabsq, arg0); |
6522 | 0 | // Rule at src/isa/x64/inst.isle line 3508. |
6523 | 0 | return v2; |
6524 | 0 | } |
6525 | | |
6526 | | // Generated as internal constructor for term x64_vpopcntb. |
6527 | 0 | pub fn constructor_x64_vpopcntb<C: Context>( |
6528 | 0 | ctx: &mut C, |
6529 | 0 | arg0: &XmmMem, |
6530 | 0 | ) -> Xmm { |
6531 | 0 | let v2 = constructor_xmm_unary_rm_r_evex(ctx, &Avx512Opcode::Vpopcntb, arg0); |
6532 | 0 | // Rule at src/isa/x64/inst.isle line 3513. |
6533 | 0 | return v2; |
6534 | 0 | } |
6535 | | |
6536 | | // Generated as internal constructor for term xmm_rm_r_evex. |
6537 | 0 | pub fn constructor_xmm_rm_r_evex<C: Context>( |
6538 | 0 | ctx: &mut C, |
6539 | 0 | arg0: &Avx512Opcode, |
6540 | 0 | arg1: &XmmMem, |
6541 | 0 | arg2: Xmm, |
6542 | 0 | ) -> Xmm { |
6543 | 0 | let v3 = C::temp_writable_xmm(ctx); |
6544 | 0 | let v4 = MInst::XmmRmREvex { |
6545 | 0 | op: arg0.clone(), |
6546 | 0 | src1: arg1.clone(), |
6547 | 0 | src2: arg2, |
6548 | 0 | dst: v3, |
6549 | 0 | }; |
6550 | 0 | let v5 = C::emit(ctx, &v4); |
6551 | 0 | let v6 = C::writable_xmm_to_xmm(ctx, v3); |
6552 | 0 | // Rule at src/isa/x64/inst.isle line 3518. |
6553 | 0 | return v6; |
6554 | 0 | } |
6555 | | |
6556 | | // Generated as internal constructor for term x64_vpmullq. |
6557 | 0 | pub fn constructor_x64_vpmullq<C: Context>( |
6558 | 0 | ctx: &mut C, |
6559 | 0 | arg0: &XmmMem, |
6560 | 0 | arg1: Xmm, |
6561 | 0 | ) -> Xmm { |
6562 | 0 | let v3 = constructor_xmm_rm_r_evex(ctx, &Avx512Opcode::Vpmullq, arg0, arg1); |
6563 | 0 | // Rule at src/isa/x64/inst.isle line 3530. |
6564 | 0 | return v3; |
6565 | 0 | } |
6566 | | |
6567 | | // Generated as internal constructor for term x64_vpermi2b. |
6568 | 0 | pub fn constructor_x64_vpermi2b<C: Context>( |
6569 | 0 | ctx: &mut C, |
6570 | 0 | arg0: Xmm, |
6571 | 0 | arg1: Xmm, |
6572 | 0 | arg2: Xmm, |
6573 | 0 | ) -> Xmm { |
6574 | 0 | let v3 = C::temp_writable_xmm(ctx); |
6575 | 0 | let v5 = &C::xmm_to_xmm_mem(ctx, arg0); |
6576 | 0 | let v6 = MInst::XmmRmREvex3 { |
6577 | 0 | op: Avx512Opcode::Vpermi2b, |
6578 | 0 | src1: v5.clone(), |
6579 | 0 | src2: arg1, |
6580 | 0 | src3: arg2, |
6581 | 0 | dst: v3, |
6582 | 0 | }; |
6583 | 0 | let v7 = C::emit(ctx, &v6); |
6584 | 0 | let v8 = C::writable_xmm_to_xmm(ctx, v3); |
6585 | 0 | // Rule at src/isa/x64/inst.isle line 3539. |
6586 | 0 | return v8; |
6587 | 0 | } |
6588 | | |
6589 | | // Generated as internal constructor for term mul_hi. |
6590 | 0 | pub fn constructor_mul_hi<C: Context>( |
6591 | 0 | ctx: &mut C, |
6592 | 0 | arg0: Type, |
6593 | 0 | arg1: bool, |
6594 | 0 | arg2: Gpr, |
6595 | 0 | arg3: &GprMem, |
6596 | 0 | ) -> ValueRegs { |
6597 | 0 | let v4 = C::temp_writable_gpr(ctx); |
6598 | 0 | let v5 = C::temp_writable_gpr(ctx); |
6599 | 0 | let v6 = &C::raw_operand_size_of_type(ctx, arg0); |
6600 | 0 | let v7 = MInst::MulHi { |
6601 | 0 | size: v6.clone(), |
6602 | 0 | signed: arg1, |
6603 | 0 | src1: arg2, |
6604 | 0 | src2: arg3.clone(), |
6605 | 0 | dst_lo: v4, |
6606 | 0 | dst_hi: v5, |
6607 | 0 | }; |
6608 | 0 | let v8 = C::emit(ctx, &v7); |
6609 | 0 | let v9 = C::writable_gpr_to_gpr(ctx, v4); |
6610 | 0 | let v10 = C::writable_gpr_to_gpr(ctx, v5); |
6611 | 0 | let v11 = constructor_value_gprs(ctx, v9, v10); |
6612 | 0 | // Rule at src/isa/x64/inst.isle line 3552. |
6613 | 0 | return v11; |
6614 | 0 | } |
6615 | | |
6616 | | // Generated as internal constructor for term mulhi_u. |
6617 | 0 | pub fn constructor_mulhi_u<C: Context>( |
6618 | 0 | ctx: &mut C, |
6619 | 0 | arg0: Type, |
6620 | 0 | arg1: Gpr, |
6621 | 0 | arg2: &GprMem, |
6622 | 0 | ) -> ValueRegs { |
6623 | 0 | let v4 = constructor_mul_hi(ctx, arg0, false, arg1, arg2); |
6624 | 0 | // Rule at src/isa/x64/inst.isle line 3567. |
6625 | 0 | return v4; |
6626 | 0 | } |
6627 | | |
6628 | | // Generated as internal constructor for term xmm_rmi_xmm. |
6629 | 0 | pub fn constructor_xmm_rmi_xmm<C: Context>( |
6630 | 0 | ctx: &mut C, |
6631 | 0 | arg0: &SseOpcode, |
6632 | 0 | arg1: Xmm, |
6633 | 0 | arg2: &XmmMemAlignedImm, |
6634 | 0 | ) -> Xmm { |
6635 | 0 | let v3 = C::temp_writable_xmm(ctx); |
6636 | 0 | let v4 = MInst::XmmRmiReg { |
6637 | 0 | opcode: arg0.clone(), |
6638 | 0 | src1: arg1, |
6639 | 0 | src2: arg2.clone(), |
6640 | 0 | dst: v3, |
6641 | 0 | }; |
6642 | 0 | let v5 = C::emit(ctx, &v4); |
6643 | 0 | let v6 = C::writable_xmm_to_xmm(ctx, v3); |
6644 | 0 | // Rule at src/isa/x64/inst.isle line 3572. |
6645 | 0 | return v6; |
6646 | 0 | } |
6647 | | |
6648 | | // Generated as internal constructor for term x64_psllw. |
6649 | 0 | pub fn constructor_x64_psllw<C: Context>( |
6650 | 0 | ctx: &mut C, |
6651 | 0 | arg0: Xmm, |
6652 | 0 | arg1: &XmmMemImm, |
6653 | 0 | ) -> Xmm { |
6654 | 0 | let v5 = C::use_avx_simd(ctx); |
6655 | 0 | if v5 == true { |
6656 | 0 | let v7 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpsllw, arg0, arg1); |
6657 | 0 | // Rule at src/isa/x64/inst.isle line 3584. |
6658 | 0 | return v7; |
6659 | 0 | } |
6660 | 0 | let v3 = &C::xmm_mem_imm_to_xmm_mem_aligned_imm(ctx, arg1); |
6661 | 0 | let v4 = constructor_xmm_rmi_xmm(ctx, &SseOpcode::Psllw, arg0, v3); |
6662 | 0 | // Rule at src/isa/x64/inst.isle line 3582. |
6663 | 0 | return v4; |
6664 | 0 | } |
6665 | | |
6666 | | // Generated as internal constructor for term x64_pslld. |
6667 | 0 | pub fn constructor_x64_pslld<C: Context>( |
6668 | 0 | ctx: &mut C, |
6669 | 0 | arg0: Xmm, |
6670 | 0 | arg1: &XmmMemImm, |
6671 | 0 | ) -> Xmm { |
6672 | 0 | let v5 = C::use_avx_simd(ctx); |
6673 | 0 | if v5 == true { |
6674 | 0 | let v7 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpslld, arg0, arg1); |
6675 | 0 | // Rule at src/isa/x64/inst.isle line 3592. |
6676 | 0 | return v7; |
6677 | 0 | } |
6678 | 0 | let v3 = &C::xmm_mem_imm_to_xmm_mem_aligned_imm(ctx, arg1); |
6679 | 0 | let v4 = constructor_xmm_rmi_xmm(ctx, &SseOpcode::Pslld, arg0, v3); |
6680 | 0 | // Rule at src/isa/x64/inst.isle line 3590. |
6681 | 0 | return v4; |
6682 | 0 | } |
6683 | | |
6684 | | // Generated as internal constructor for term x64_psllq. |
6685 | 0 | pub fn constructor_x64_psllq<C: Context>( |
6686 | 0 | ctx: &mut C, |
6687 | 0 | arg0: Xmm, |
6688 | 0 | arg1: &XmmMemImm, |
6689 | 0 | ) -> Xmm { |
6690 | 0 | let v5 = C::use_avx_simd(ctx); |
6691 | 0 | if v5 == true { |
6692 | 0 | let v7 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpsllq, arg0, arg1); |
6693 | 0 | // Rule at src/isa/x64/inst.isle line 3600. |
6694 | 0 | return v7; |
6695 | 0 | } |
6696 | 0 | let v3 = &C::xmm_mem_imm_to_xmm_mem_aligned_imm(ctx, arg1); |
6697 | 0 | let v4 = constructor_xmm_rmi_xmm(ctx, &SseOpcode::Psllq, arg0, v3); |
6698 | 0 | // Rule at src/isa/x64/inst.isle line 3598. |
6699 | 0 | return v4; |
6700 | 0 | } |
6701 | | |
6702 | | // Generated as internal constructor for term x64_psrlw. |
6703 | 0 | pub fn constructor_x64_psrlw<C: Context>( |
6704 | 0 | ctx: &mut C, |
6705 | 0 | arg0: Xmm, |
6706 | 0 | arg1: &XmmMemImm, |
6707 | 0 | ) -> Xmm { |
6708 | 0 | let v5 = C::use_avx_simd(ctx); |
6709 | 0 | if v5 == true { |
6710 | 0 | let v7 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpsrlw, arg0, arg1); |
6711 | 0 | // Rule at src/isa/x64/inst.isle line 3608. |
6712 | 0 | return v7; |
6713 | 0 | } |
6714 | 0 | let v3 = &C::xmm_mem_imm_to_xmm_mem_aligned_imm(ctx, arg1); |
6715 | 0 | let v4 = constructor_xmm_rmi_xmm(ctx, &SseOpcode::Psrlw, arg0, v3); |
6716 | 0 | // Rule at src/isa/x64/inst.isle line 3606. |
6717 | 0 | return v4; |
6718 | 0 | } |
6719 | | |
6720 | | // Generated as internal constructor for term x64_psrld. |
6721 | 0 | pub fn constructor_x64_psrld<C: Context>( |
6722 | 0 | ctx: &mut C, |
6723 | 0 | arg0: Xmm, |
6724 | 0 | arg1: &XmmMemImm, |
6725 | 0 | ) -> Xmm { |
6726 | 0 | let v5 = C::use_avx_simd(ctx); |
6727 | 0 | if v5 == true { |
6728 | 0 | let v7 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpsrld, arg0, arg1); |
6729 | 0 | // Rule at src/isa/x64/inst.isle line 3616. |
6730 | 0 | return v7; |
6731 | 0 | } |
6732 | 0 | let v3 = &C::xmm_mem_imm_to_xmm_mem_aligned_imm(ctx, arg1); |
6733 | 0 | let v4 = constructor_xmm_rmi_xmm(ctx, &SseOpcode::Psrld, arg0, v3); |
6734 | 0 | // Rule at src/isa/x64/inst.isle line 3614. |
6735 | 0 | return v4; |
6736 | 0 | } |
6737 | | |
6738 | | // Generated as internal constructor for term x64_psrlq. |
6739 | 0 | pub fn constructor_x64_psrlq<C: Context>( |
6740 | 0 | ctx: &mut C, |
6741 | 0 | arg0: Xmm, |
6742 | 0 | arg1: &XmmMemImm, |
6743 | 0 | ) -> Xmm { |
6744 | 0 | let v5 = C::use_avx_simd(ctx); |
6745 | 0 | if v5 == true { |
6746 | 0 | let v7 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpsrlq, arg0, arg1); |
6747 | 0 | // Rule at src/isa/x64/inst.isle line 3624. |
6748 | 0 | return v7; |
6749 | 0 | } |
6750 | 0 | let v3 = &C::xmm_mem_imm_to_xmm_mem_aligned_imm(ctx, arg1); |
6751 | 0 | let v4 = constructor_xmm_rmi_xmm(ctx, &SseOpcode::Psrlq, arg0, v3); |
6752 | 0 | // Rule at src/isa/x64/inst.isle line 3622. |
6753 | 0 | return v4; |
6754 | 0 | } |
6755 | | |
6756 | | // Generated as internal constructor for term x64_psraw. |
6757 | 0 | pub fn constructor_x64_psraw<C: Context>( |
6758 | 0 | ctx: &mut C, |
6759 | 0 | arg0: Xmm, |
6760 | 0 | arg1: &XmmMemImm, |
6761 | 0 | ) -> Xmm { |
6762 | 0 | let v5 = C::use_avx_simd(ctx); |
6763 | 0 | if v5 == true { |
6764 | 0 | let v7 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpsraw, arg0, arg1); |
6765 | 0 | // Rule at src/isa/x64/inst.isle line 3632. |
6766 | 0 | return v7; |
6767 | 0 | } |
6768 | 0 | let v3 = &C::xmm_mem_imm_to_xmm_mem_aligned_imm(ctx, arg1); |
6769 | 0 | let v4 = constructor_xmm_rmi_xmm(ctx, &SseOpcode::Psraw, arg0, v3); |
6770 | 0 | // Rule at src/isa/x64/inst.isle line 3630. |
6771 | 0 | return v4; |
6772 | 0 | } |
6773 | | |
6774 | | // Generated as internal constructor for term x64_psrad. |
6775 | 0 | pub fn constructor_x64_psrad<C: Context>( |
6776 | 0 | ctx: &mut C, |
6777 | 0 | arg0: Xmm, |
6778 | 0 | arg1: &XmmMemImm, |
6779 | 0 | ) -> Xmm { |
6780 | 0 | let v5 = C::use_avx_simd(ctx); |
6781 | 0 | if v5 == true { |
6782 | 0 | let v7 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpsrad, arg0, arg1); |
6783 | 0 | // Rule at src/isa/x64/inst.isle line 3640. |
6784 | 0 | return v7; |
6785 | 0 | } |
6786 | 0 | let v3 = &C::xmm_mem_imm_to_xmm_mem_aligned_imm(ctx, arg1); |
6787 | 0 | let v4 = constructor_xmm_rmi_xmm(ctx, &SseOpcode::Psrad, arg0, v3); |
6788 | 0 | // Rule at src/isa/x64/inst.isle line 3638. |
6789 | 0 | return v4; |
6790 | 0 | } |
6791 | | |
6792 | | // Generated as internal constructor for term x64_pextrb. |
6793 | 0 | pub fn constructor_x64_pextrb<C: Context>( |
6794 | 0 | ctx: &mut C, |
6795 | 0 | arg0: Xmm, |
6796 | 0 | arg1: u8, |
6797 | 0 | ) -> Gpr { |
6798 | 0 | let v4 = C::use_avx_simd(ctx); |
6799 | 0 | if v4 == true { |
6800 | 0 | let v6 = constructor_xmm_to_gpr_imm_vex(ctx, &AvxOpcode::Vpextrb, arg0, arg1); |
6801 | 0 | // Rule at src/isa/x64/inst.isle line 3648. |
6802 | 0 | return v6; |
6803 | 0 | } |
6804 | 0 | let v3 = constructor_xmm_to_gpr_imm(ctx, &SseOpcode::Pextrb, arg0, arg1); |
6805 | 0 | // Rule at src/isa/x64/inst.isle line 3646. |
6806 | 0 | return v3; |
6807 | 0 | } |
6808 | | |
6809 | | // Generated as internal constructor for term x64_pextrb_store. |
6810 | 0 | pub fn constructor_x64_pextrb_store<C: Context>( |
6811 | 0 | ctx: &mut C, |
6812 | 0 | arg0: &SyntheticAmode, |
6813 | 0 | arg1: Xmm, |
6814 | 0 | arg2: u8, |
6815 | 0 | ) -> SideEffectNoResult { |
6816 | 0 | let v5 = C::use_avx_simd(ctx); |
6817 | 0 | if v5 == true { |
6818 | 0 | let v7 = &constructor_xmm_movrm_imm_vex(ctx, &AvxOpcode::Vpextrb, arg0, arg1, arg2); |
6819 | 0 | // Rule at src/isa/x64/inst.isle line 3655. |
6820 | 0 | return v7.clone(); |
6821 | 0 | } |
6822 | 0 | let v4 = &constructor_xmm_movrm_imm(ctx, &SseOpcode::Pextrb, arg0, arg1, arg2); |
6823 | 0 | // Rule at src/isa/x64/inst.isle line 3653. |
6824 | 0 | return v4.clone(); |
6825 | 0 | } |
6826 | | |
6827 | | // Generated as internal constructor for term x64_pextrw. |
6828 | 0 | pub fn constructor_x64_pextrw<C: Context>( |
6829 | 0 | ctx: &mut C, |
6830 | 0 | arg0: Xmm, |
6831 | 0 | arg1: u8, |
6832 | 0 | ) -> Gpr { |
6833 | 0 | let v4 = C::use_avx_simd(ctx); |
6834 | 0 | if v4 == true { |
6835 | 0 | let v6 = constructor_xmm_to_gpr_imm_vex(ctx, &AvxOpcode::Vpextrw, arg0, arg1); |
6836 | 0 | // Rule at src/isa/x64/inst.isle line 3663. |
6837 | 0 | return v6; |
6838 | 0 | } |
6839 | 0 | let v3 = constructor_xmm_to_gpr_imm(ctx, &SseOpcode::Pextrw, arg0, arg1); |
6840 | 0 | // Rule at src/isa/x64/inst.isle line 3661. |
6841 | 0 | return v3; |
6842 | 0 | } |
6843 | | |
6844 | | // Generated as internal constructor for term x64_pextrw_store. |
6845 | 0 | pub fn constructor_x64_pextrw_store<C: Context>( |
6846 | 0 | ctx: &mut C, |
6847 | 0 | arg0: &SyntheticAmode, |
6848 | 0 | arg1: Xmm, |
6849 | 0 | arg2: u8, |
6850 | 0 | ) -> SideEffectNoResult { |
6851 | 0 | let v5 = C::use_avx_simd(ctx); |
6852 | 0 | if v5 == true { |
6853 | 0 | let v7 = &constructor_xmm_movrm_imm_vex(ctx, &AvxOpcode::Vpextrw, arg0, arg1, arg2); |
6854 | 0 | // Rule at src/isa/x64/inst.isle line 3670. |
6855 | 0 | return v7.clone(); |
6856 | 0 | } |
6857 | 0 | let v4 = &constructor_xmm_movrm_imm(ctx, &SseOpcode::Pextrw, arg0, arg1, arg2); |
6858 | 0 | // Rule at src/isa/x64/inst.isle line 3668. |
6859 | 0 | return v4.clone(); |
6860 | 0 | } |
6861 | | |
6862 | | // Generated as internal constructor for term x64_pextrd. |
6863 | 0 | pub fn constructor_x64_pextrd<C: Context>( |
6864 | 0 | ctx: &mut C, |
6865 | 0 | arg0: Xmm, |
6866 | 0 | arg1: u8, |
6867 | 0 | ) -> Gpr { |
6868 | 0 | let v4 = C::use_avx_simd(ctx); |
6869 | 0 | if v4 == true { |
6870 | 0 | let v6 = constructor_xmm_to_gpr_imm_vex(ctx, &AvxOpcode::Vpextrd, arg0, arg1); |
6871 | 0 | // Rule at src/isa/x64/inst.isle line 3678. |
6872 | 0 | return v6; |
6873 | 0 | } |
6874 | 0 | let v3 = constructor_xmm_to_gpr_imm(ctx, &SseOpcode::Pextrd, arg0, arg1); |
6875 | 0 | // Rule at src/isa/x64/inst.isle line 3676. |
6876 | 0 | return v3; |
6877 | 0 | } |
6878 | | |
6879 | | // Generated as internal constructor for term x64_pextrd_store. |
6880 | 0 | pub fn constructor_x64_pextrd_store<C: Context>( |
6881 | 0 | ctx: &mut C, |
6882 | 0 | arg0: &SyntheticAmode, |
6883 | 0 | arg1: Xmm, |
6884 | 0 | arg2: u8, |
6885 | 0 | ) -> SideEffectNoResult { |
6886 | 0 | let v5 = C::use_avx_simd(ctx); |
6887 | 0 | if v5 == true { |
6888 | 0 | let v7 = &constructor_xmm_movrm_imm_vex(ctx, &AvxOpcode::Vpextrd, arg0, arg1, arg2); |
6889 | 0 | // Rule at src/isa/x64/inst.isle line 3685. |
6890 | 0 | return v7.clone(); |
6891 | 0 | } |
6892 | 0 | let v4 = &constructor_xmm_movrm_imm(ctx, &SseOpcode::Pextrd, arg0, arg1, arg2); |
6893 | 0 | // Rule at src/isa/x64/inst.isle line 3683. |
6894 | 0 | return v4.clone(); |
6895 | 0 | } |
6896 | | |
6897 | | // Generated as internal constructor for term x64_pextrq. |
6898 | 0 | pub fn constructor_x64_pextrq<C: Context>( |
6899 | 0 | ctx: &mut C, |
6900 | 0 | arg0: Xmm, |
6901 | 0 | arg1: u8, |
6902 | 0 | ) -> Gpr { |
6903 | 0 | let v4 = C::use_avx_simd(ctx); |
6904 | 0 | if v4 == true { |
6905 | 0 | let v6 = constructor_xmm_to_gpr_imm_vex(ctx, &AvxOpcode::Vpextrq, arg0, arg1); |
6906 | 0 | // Rule at src/isa/x64/inst.isle line 3693. |
6907 | 0 | return v6; |
6908 | 0 | } |
6909 | 0 | let v3 = constructor_xmm_to_gpr_imm(ctx, &SseOpcode::Pextrq, arg0, arg1); |
6910 | 0 | // Rule at src/isa/x64/inst.isle line 3691. |
6911 | 0 | return v3; |
6912 | 0 | } |
6913 | | |
6914 | | // Generated as internal constructor for term x64_pextrq_store. |
6915 | 0 | pub fn constructor_x64_pextrq_store<C: Context>( |
6916 | 0 | ctx: &mut C, |
6917 | 0 | arg0: &SyntheticAmode, |
6918 | 0 | arg1: Xmm, |
6919 | 0 | arg2: u8, |
6920 | 0 | ) -> SideEffectNoResult { |
6921 | 0 | let v5 = C::use_avx_simd(ctx); |
6922 | 0 | if v5 == true { |
6923 | 0 | let v7 = &constructor_xmm_movrm_imm_vex(ctx, &AvxOpcode::Vpextrq, arg0, arg1, arg2); |
6924 | 0 | // Rule at src/isa/x64/inst.isle line 3700. |
6925 | 0 | return v7.clone(); |
6926 | 0 | } |
6927 | 0 | let v4 = &constructor_xmm_movrm_imm(ctx, &SseOpcode::Pextrq, arg0, arg1, arg2); |
6928 | 0 | // Rule at src/isa/x64/inst.isle line 3698. |
6929 | 0 | return v4.clone(); |
6930 | 0 | } |
6931 | | |
6932 | | // Generated as internal constructor for term xmm_to_gpr. |
6933 | 0 | pub fn constructor_xmm_to_gpr<C: Context>( |
6934 | 0 | ctx: &mut C, |
6935 | 0 | arg0: &SseOpcode, |
6936 | 0 | arg1: Xmm, |
6937 | 0 | arg2: &OperandSize, |
6938 | 0 | ) -> Gpr { |
6939 | 0 | let v3 = C::temp_writable_gpr(ctx); |
6940 | 0 | let v4 = MInst::XmmToGpr { |
6941 | 0 | op: arg0.clone(), |
6942 | 0 | src: arg1, |
6943 | 0 | dst: v3, |
6944 | 0 | dst_size: arg2.clone(), |
6945 | 0 | }; |
6946 | 0 | let v5 = C::emit(ctx, &v4); |
6947 | 0 | let v6 = C::writable_gpr_to_gpr(ctx, v3); |
6948 | 0 | // Rule at src/isa/x64/inst.isle line 3706. |
6949 | 0 | return v6; |
6950 | 0 | } |
6951 | | |
6952 | | // Generated as internal constructor for term xmm_to_gpr_imm. |
6953 | 0 | pub fn constructor_xmm_to_gpr_imm<C: Context>( |
6954 | 0 | ctx: &mut C, |
6955 | 0 | arg0: &SseOpcode, |
6956 | 0 | arg1: Xmm, |
6957 | 0 | arg2: u8, |
6958 | 0 | ) -> Gpr { |
6959 | 0 | let v3 = C::temp_writable_gpr(ctx); |
6960 | 0 | let v4 = MInst::XmmToGprImm { |
6961 | 0 | op: arg0.clone(), |
6962 | 0 | src: arg1, |
6963 | 0 | dst: v3, |
6964 | 0 | imm: arg2, |
6965 | 0 | }; |
6966 | 0 | let v5 = C::emit(ctx, &v4); |
6967 | 0 | let v6 = C::writable_gpr_to_gpr(ctx, v3); |
6968 | 0 | // Rule at src/isa/x64/inst.isle line 3713. |
6969 | 0 | return v6; |
6970 | 0 | } |
6971 | | |
6972 | | // Generated as internal constructor for term xmm_to_gpr_imm_vex. |
6973 | 0 | pub fn constructor_xmm_to_gpr_imm_vex<C: Context>( |
6974 | 0 | ctx: &mut C, |
6975 | 0 | arg0: &AvxOpcode, |
6976 | 0 | arg1: Xmm, |
6977 | 0 | arg2: u8, |
6978 | 0 | ) -> Gpr { |
6979 | 0 | let v3 = C::temp_writable_gpr(ctx); |
6980 | 0 | let v4 = MInst::XmmToGprImmVex { |
6981 | 0 | op: arg0.clone(), |
6982 | 0 | src: arg1, |
6983 | 0 | dst: v3, |
6984 | 0 | imm: arg2, |
6985 | 0 | }; |
6986 | 0 | let v5 = C::emit(ctx, &v4); |
6987 | 0 | let v6 = C::writable_gpr_to_gpr(ctx, v3); |
6988 | 0 | // Rule at src/isa/x64/inst.isle line 3720. |
6989 | 0 | return v6; |
6990 | 0 | } |
6991 | | |
6992 | | // Generated as internal constructor for term xmm_to_gpr_vex. |
6993 | 0 | pub fn constructor_xmm_to_gpr_vex<C: Context>( |
6994 | 0 | ctx: &mut C, |
6995 | 0 | arg0: &AvxOpcode, |
6996 | 0 | arg1: Xmm, |
6997 | 0 | arg2: &OperandSize, |
6998 | 0 | ) -> Gpr { |
6999 | 0 | let v3 = C::temp_writable_gpr(ctx); |
7000 | 0 | let v4 = MInst::XmmToGprVex { |
7001 | 0 | op: arg0.clone(), |
7002 | 0 | src: arg1, |
7003 | 0 | dst: v3, |
7004 | 0 | dst_size: arg2.clone(), |
7005 | 0 | }; |
7006 | 0 | let v5 = C::emit(ctx, &v4); |
7007 | 0 | let v6 = C::writable_gpr_to_gpr(ctx, v3); |
7008 | 0 | // Rule at src/isa/x64/inst.isle line 3727. |
7009 | 0 | return v6; |
7010 | 0 | } |
7011 | | |
7012 | | // Generated as internal constructor for term gpr_to_xmm_vex. |
7013 | 0 | pub fn constructor_gpr_to_xmm_vex<C: Context>( |
7014 | 0 | ctx: &mut C, |
7015 | 0 | arg0: &AvxOpcode, |
7016 | 0 | arg1: &GprMem, |
7017 | 0 | arg2: &OperandSize, |
7018 | 0 | ) -> Xmm { |
7019 | 0 | let v3 = C::temp_writable_xmm(ctx); |
7020 | 0 | let v4 = MInst::GprToXmmVex { |
7021 | 0 | op: arg0.clone(), |
7022 | 0 | src: arg1.clone(), |
7023 | 0 | dst: v3, |
7024 | 0 | src_size: arg2.clone(), |
7025 | 0 | }; |
7026 | 0 | let v5 = C::emit(ctx, &v4); |
7027 | 0 | let v6 = C::writable_xmm_to_xmm(ctx, v3); |
7028 | 0 | // Rule at src/isa/x64/inst.isle line 3734. |
7029 | 0 | return v6; |
7030 | 0 | } |
7031 | | |
7032 | | // Generated as internal constructor for term x64_pmovmskb. |
7033 | 0 | pub fn constructor_x64_pmovmskb<C: Context>( |
7034 | 0 | ctx: &mut C, |
7035 | 0 | arg0: &OperandSize, |
7036 | 0 | arg1: Xmm, |
7037 | 0 | ) -> Gpr { |
7038 | 0 | let v4 = C::use_avx_simd(ctx); |
7039 | 0 | if v4 == true { |
7040 | 0 | let v6 = constructor_xmm_to_gpr_vex(ctx, &AvxOpcode::Vpmovmskb, arg1, arg0); |
7041 | 0 | // Rule at src/isa/x64/inst.isle line 3744. |
7042 | 0 | return v6; |
7043 | 0 | } |
7044 | 0 | let v3 = constructor_xmm_to_gpr(ctx, &SseOpcode::Pmovmskb, arg1, arg0); |
7045 | 0 | // Rule at src/isa/x64/inst.isle line 3742. |
7046 | 0 | return v3; |
7047 | 0 | } |
7048 | | |
7049 | | // Generated as internal constructor for term x64_movmskps. |
7050 | 0 | pub fn constructor_x64_movmskps<C: Context>( |
7051 | 0 | ctx: &mut C, |
7052 | 0 | arg0: &OperandSize, |
7053 | 0 | arg1: Xmm, |
7054 | 0 | ) -> Gpr { |
7055 | 0 | let v4 = C::use_avx_simd(ctx); |
7056 | 0 | if v4 == true { |
7057 | 0 | let v6 = constructor_xmm_to_gpr_vex(ctx, &AvxOpcode::Vmovmskps, arg1, arg0); |
7058 | 0 | // Rule at src/isa/x64/inst.isle line 3752. |
7059 | 0 | return v6; |
7060 | 0 | } |
7061 | 0 | let v3 = constructor_xmm_to_gpr(ctx, &SseOpcode::Movmskps, arg1, arg0); |
7062 | 0 | // Rule at src/isa/x64/inst.isle line 3750. |
7063 | 0 | return v3; |
7064 | 0 | } |
7065 | | |
7066 | | // Generated as internal constructor for term x64_movmskpd. |
7067 | 0 | pub fn constructor_x64_movmskpd<C: Context>( |
7068 | 0 | ctx: &mut C, |
7069 | 0 | arg0: &OperandSize, |
7070 | 0 | arg1: Xmm, |
7071 | 0 | ) -> Gpr { |
7072 | 0 | let v4 = C::use_avx_simd(ctx); |
7073 | 0 | if v4 == true { |
7074 | 0 | let v6 = constructor_xmm_to_gpr_vex(ctx, &AvxOpcode::Vmovmskpd, arg1, arg0); |
7075 | 0 | // Rule at src/isa/x64/inst.isle line 3760. |
7076 | 0 | return v6; |
7077 | 0 | } |
7078 | 0 | let v3 = constructor_xmm_to_gpr(ctx, &SseOpcode::Movmskpd, arg1, arg0); |
7079 | 0 | // Rule at src/isa/x64/inst.isle line 3758. |
7080 | 0 | return v3; |
7081 | 0 | } |
7082 | | |
7083 | | // Generated as internal constructor for term gpr_to_xmm. |
7084 | 0 | pub fn constructor_gpr_to_xmm<C: Context>( |
7085 | 0 | ctx: &mut C, |
7086 | 0 | arg0: &SseOpcode, |
7087 | 0 | arg1: &GprMem, |
7088 | 0 | arg2: &OperandSize, |
7089 | 0 | ) -> Xmm { |
7090 | 0 | let v3 = C::temp_writable_xmm(ctx); |
7091 | 0 | let v4 = MInst::GprToXmm { |
7092 | 0 | op: arg0.clone(), |
7093 | 0 | src: arg1.clone(), |
7094 | 0 | dst: v3, |
7095 | 0 | src_size: arg2.clone(), |
7096 | 0 | }; |
7097 | 0 | let v5 = C::emit(ctx, &v4); |
7098 | 0 | let v6 = C::writable_xmm_to_xmm(ctx, v3); |
7099 | 0 | // Rule at src/isa/x64/inst.isle line 3766. |
7100 | 0 | return v6; |
7101 | 0 | } |
7102 | | |
7103 | | // Generated as internal constructor for term x64_not. |
7104 | 487 | pub fn constructor_x64_not<C: Context>( |
7105 | 487 | ctx: &mut C, |
7106 | 487 | arg0: Type, |
7107 | 487 | arg1: Gpr, |
7108 | 487 | ) -> Gpr { |
7109 | 487 | let v2 = C::temp_writable_gpr(ctx); |
7110 | 487 | let v3 = &C::operand_size_of_type_32_64(ctx, arg0); |
7111 | 487 | let v4 = MInst::Not { |
7112 | 487 | size: v3.clone(), |
7113 | 487 | src: arg1, |
7114 | 487 | dst: v2, |
7115 | 487 | }; |
7116 | 487 | let v5 = C::emit(ctx, &v4); |
7117 | 487 | let v6 = C::writable_gpr_to_gpr(ctx, v2); |
7118 | 487 | // Rule at src/isa/x64/inst.isle line 3773. |
7119 | 487 | return v6; |
7120 | 487 | } |
7121 | | |
7122 | | // Generated as internal constructor for term x64_neg. |
7123 | 817 | pub fn constructor_x64_neg<C: Context>( |
7124 | 817 | ctx: &mut C, |
7125 | 817 | arg0: Type, |
7126 | 817 | arg1: Gpr, |
7127 | 817 | ) -> Gpr { |
7128 | 817 | let v2 = C::temp_writable_gpr(ctx); |
7129 | 817 | let v3 = &C::raw_operand_size_of_type(ctx, arg0); |
7130 | 817 | let v4 = MInst::Neg { |
7131 | 817 | size: v3.clone(), |
7132 | 817 | src: arg1, |
7133 | 817 | dst: v2, |
7134 | 817 | }; |
7135 | 817 | let v5 = C::emit(ctx, &v4); |
7136 | 817 | let v6 = C::writable_gpr_to_gpr(ctx, v2); |
7137 | 817 | // Rule at src/isa/x64/inst.isle line 3781. |
7138 | 817 | return v6; |
7139 | 817 | } |
7140 | | |
7141 | | // Generated as internal constructor for term x64_neg_paired. |
7142 | 0 | pub fn constructor_x64_neg_paired<C: Context>( |
7143 | 0 | ctx: &mut C, |
7144 | 0 | arg0: Type, |
7145 | 0 | arg1: Gpr, |
7146 | 0 | ) -> ProducesFlags { |
7147 | 0 | let v2 = C::temp_writable_gpr(ctx); |
7148 | 0 | let v3 = &C::raw_operand_size_of_type(ctx, arg0); |
7149 | 0 | let v5 = constructor_writable_gpr_to_r_reg(ctx, v2); |
7150 | 0 | let v4 = MInst::Neg { |
7151 | 0 | size: v3.clone(), |
7152 | 0 | src: arg1, |
7153 | 0 | dst: v2, |
7154 | 0 | }; |
7155 | 0 | let v6 = ProducesFlags::ProducesFlagsReturnsResultWithConsumer { |
7156 | 0 | inst: v4, |
7157 | 0 | result: v5, |
7158 | 0 | }; |
7159 | 0 | // Rule at src/isa/x64/inst.isle line 3789. |
7160 | 0 | return v6; |
7161 | 0 | } |
7162 | | |
7163 | | // Generated as internal constructor for term x64_lea. |
7164 | 484k | pub fn constructor_x64_lea<C: Context>( |
7165 | 484k | ctx: &mut C, |
7166 | 484k | arg0: Type, |
7167 | 484k | arg1: &SyntheticAmode, |
7168 | 484k | ) -> Gpr { |
7169 | 484k | let v2 = C::temp_writable_gpr(ctx); |
7170 | 484k | let v3 = &C::operand_size_of_type_32_64(ctx, arg0); |
7171 | 484k | let v4 = MInst::LoadEffectiveAddress { |
7172 | 484k | addr: arg1.clone(), |
7173 | 484k | dst: v2, |
7174 | 484k | size: v3.clone(), |
7175 | 484k | }; |
7176 | 484k | let v5 = C::emit(ctx, &v4); |
7177 | 484k | let v6 = C::writable_gpr_to_gpr(ctx, v2); |
7178 | 484k | // Rule at src/isa/x64/inst.isle line 3796. |
7179 | 484k | return v6; |
7180 | 484k | } |
7181 | | |
7182 | | // Generated as internal constructor for term x64_ud2. |
7183 | 87.0k | pub fn constructor_x64_ud2<C: Context>( |
7184 | 87.0k | ctx: &mut C, |
7185 | 87.0k | arg0: &TrapCode, |
7186 | 87.0k | ) -> SideEffectNoResult { |
7187 | 87.0k | let v1 = MInst::Ud2 { |
7188 | 87.0k | trap_code: arg0.clone(), |
7189 | 87.0k | }; |
7190 | 87.0k | let v2 = SideEffectNoResult::Inst { |
7191 | 87.0k | inst: v1, |
7192 | 87.0k | }; |
7193 | 87.0k | // Rule at src/isa/x64/inst.isle line 3803. |
7194 | 87.0k | return v2; |
7195 | 87.0k | } |
7196 | | |
7197 | | // Generated as internal constructor for term x64_hlt. |
7198 | 0 | pub fn constructor_x64_hlt<C: Context>( |
7199 | 0 | ctx: &mut C, |
7200 | 0 | ) -> SideEffectNoResult { |
7201 | 0 | let v1 = SideEffectNoResult::Inst { |
7202 | 0 | inst: MInst::Hlt, |
7203 | 0 | }; |
7204 | 0 | // Rule at src/isa/x64/inst.isle line 3808. |
7205 | 0 | return v1; |
7206 | 0 | } |
7207 | | |
7208 | | // Generated as internal constructor for term x64_lzcnt. |
7209 | 80 | pub fn constructor_x64_lzcnt<C: Context>( |
7210 | 80 | ctx: &mut C, |
7211 | 80 | arg0: Type, |
7212 | 80 | arg1: Gpr, |
7213 | 80 | ) -> Gpr { |
7214 | 80 | let v2 = C::temp_writable_gpr(ctx); |
7215 | 80 | let v3 = &C::operand_size_of_type_32_64(ctx, arg0); |
7216 | 80 | let v5 = &C::gpr_to_gpr_mem(ctx, arg1); |
7217 | 80 | let v6 = MInst::UnaryRmR { |
7218 | 80 | size: v3.clone(), |
7219 | 80 | op: UnaryRmROpcode::Lzcnt, |
7220 | 80 | src: v5.clone(), |
7221 | 80 | dst: v2, |
7222 | 80 | }; |
7223 | 80 | let v7 = C::emit(ctx, &v6); |
7224 | 80 | let v8 = C::writable_gpr_to_gpr(ctx, v2); |
7225 | 80 | // Rule at src/isa/x64/inst.isle line 3813. |
7226 | 80 | return v8; |
7227 | 80 | } |
7228 | | |
7229 | | // Generated as internal constructor for term x64_tzcnt. |
7230 | 88 | pub fn constructor_x64_tzcnt<C: Context>( |
7231 | 88 | ctx: &mut C, |
7232 | 88 | arg0: Type, |
7233 | 88 | arg1: Gpr, |
7234 | 88 | ) -> Gpr { |
7235 | 88 | let v2 = C::temp_writable_gpr(ctx); |
7236 | 88 | let v3 = &C::operand_size_of_type_32_64(ctx, arg0); |
7237 | 88 | let v5 = &C::gpr_to_gpr_mem(ctx, arg1); |
7238 | 88 | let v6 = MInst::UnaryRmR { |
7239 | 88 | size: v3.clone(), |
7240 | 88 | op: UnaryRmROpcode::Tzcnt, |
7241 | 88 | src: v5.clone(), |
7242 | 88 | dst: v2, |
7243 | 88 | }; |
7244 | 88 | let v7 = C::emit(ctx, &v6); |
7245 | 88 | let v8 = C::writable_gpr_to_gpr(ctx, v2); |
7246 | 88 | // Rule at src/isa/x64/inst.isle line 3821. |
7247 | 88 | return v8; |
7248 | 88 | } |
7249 | | |
7250 | | // Generated as internal constructor for term x64_bsr. |
7251 | 0 | pub fn constructor_x64_bsr<C: Context>( |
7252 | 0 | ctx: &mut C, |
7253 | 0 | arg0: Type, |
7254 | 0 | arg1: Gpr, |
7255 | 0 | ) -> ProducesFlags { |
7256 | 0 | let v2 = C::temp_writable_gpr(ctx); |
7257 | 0 | let v3 = &C::operand_size_of_type_32_64(ctx, arg0); |
7258 | 0 | let v5 = &C::gpr_to_gpr_mem(ctx, arg1); |
7259 | 0 | let v7 = constructor_writable_gpr_to_r_reg(ctx, v2); |
7260 | 0 | let v6 = MInst::UnaryRmR { |
7261 | 0 | size: v3.clone(), |
7262 | 0 | op: UnaryRmROpcode::Bsr, |
7263 | 0 | src: v5.clone(), |
7264 | 0 | dst: v2, |
7265 | 0 | }; |
7266 | 0 | let v8 = ProducesFlags::ProducesFlagsReturnsReg { |
7267 | 0 | inst: v6, |
7268 | 0 | result: v7, |
7269 | 0 | }; |
7270 | 0 | // Rule at src/isa/x64/inst.isle line 3829. |
7271 | 0 | return v8; |
7272 | 0 | } |
7273 | | |
7274 | | // Generated as internal constructor for term bsr_or_else. |
7275 | 0 | pub fn constructor_bsr_or_else<C: Context>( |
7276 | 0 | ctx: &mut C, |
7277 | 0 | arg0: Type, |
7278 | 0 | arg1: Gpr, |
7279 | 0 | arg2: Gpr, |
7280 | 0 | ) -> Gpr { |
7281 | 0 | let v3 = &constructor_x64_bsr(ctx, arg0, arg1); |
7282 | 0 | let v4 = constructor_produces_flags_get_reg(ctx, v3); |
7283 | 0 | let v5 = C::gpr_new(ctx, v4); |
7284 | 0 | let v7 = &C::gpr_to_gpr_mem(ctx, arg2); |
7285 | 0 | let v8 = &constructor_cmove(ctx, arg0, &CC::Z, v7, v5); |
7286 | 0 | let v9 = &constructor_produces_flags_ignore(ctx, v3); |
7287 | 0 | let v10 = constructor_with_flags_reg(ctx, v9, v8); |
7288 | 0 | let v11 = C::gpr_new(ctx, v10); |
7289 | 0 | // Rule at src/isa/x64/inst.isle line 3838. |
7290 | 0 | return v11; |
7291 | 0 | } |
7292 | | |
7293 | | // Generated as internal constructor for term x64_bsf. |
7294 | 0 | pub fn constructor_x64_bsf<C: Context>( |
7295 | 0 | ctx: &mut C, |
7296 | 0 | arg0: Type, |
7297 | 0 | arg1: Gpr, |
7298 | 0 | ) -> ProducesFlags { |
7299 | 0 | let v2 = C::temp_writable_gpr(ctx); |
7300 | 0 | let v3 = &C::operand_size_of_type_32_64(ctx, arg0); |
7301 | 0 | let v5 = &C::gpr_to_gpr_mem(ctx, arg1); |
7302 | 0 | let v7 = constructor_writable_gpr_to_r_reg(ctx, v2); |
7303 | 0 | let v6 = MInst::UnaryRmR { |
7304 | 0 | size: v3.clone(), |
7305 | 0 | op: UnaryRmROpcode::Bsf, |
7306 | 0 | src: v5.clone(), |
7307 | 0 | dst: v2, |
7308 | 0 | }; |
7309 | 0 | let v8 = ProducesFlags::ProducesFlagsReturnsReg { |
7310 | 0 | inst: v6, |
7311 | 0 | result: v7, |
7312 | 0 | }; |
7313 | 0 | // Rule at src/isa/x64/inst.isle line 3849. |
7314 | 0 | return v8; |
7315 | 0 | } |
7316 | | |
7317 | | // Generated as internal constructor for term bsf_or_else. |
7318 | 0 | pub fn constructor_bsf_or_else<C: Context>( |
7319 | 0 | ctx: &mut C, |
7320 | 0 | arg0: Type, |
7321 | 0 | arg1: Gpr, |
7322 | 0 | arg2: Gpr, |
7323 | 0 | ) -> Gpr { |
7324 | 0 | let v3 = &constructor_x64_bsf(ctx, arg0, arg1); |
7325 | 0 | let v4 = constructor_produces_flags_get_reg(ctx, v3); |
7326 | 0 | let v5 = C::gpr_new(ctx, v4); |
7327 | 0 | let v7 = &C::gpr_to_gpr_mem(ctx, arg2); |
7328 | 0 | let v8 = &constructor_cmove(ctx, arg0, &CC::Z, v7, v5); |
7329 | 0 | let v9 = &constructor_produces_flags_ignore(ctx, v3); |
7330 | 0 | let v10 = constructor_with_flags_reg(ctx, v9, v8); |
7331 | 0 | let v11 = C::gpr_new(ctx, v10); |
7332 | 0 | // Rule at src/isa/x64/inst.isle line 3858. |
7333 | 0 | return v11; |
7334 | 0 | } |
7335 | | |
7336 | | // Generated as internal constructor for term x64_popcnt. |
7337 | 64 | pub fn constructor_x64_popcnt<C: Context>( |
7338 | 64 | ctx: &mut C, |
7339 | 64 | arg0: Type, |
7340 | 64 | arg1: Gpr, |
7341 | 64 | ) -> Gpr { |
7342 | 64 | let v2 = C::temp_writable_gpr(ctx); |
7343 | 64 | let v3 = &C::operand_size_of_type_32_64(ctx, arg0); |
7344 | 64 | let v5 = &C::gpr_to_gpr_mem(ctx, arg1); |
7345 | 64 | let v6 = MInst::UnaryRmR { |
7346 | 64 | size: v3.clone(), |
7347 | 64 | op: UnaryRmROpcode::Popcnt, |
7348 | 64 | src: v5.clone(), |
7349 | 64 | dst: v2, |
7350 | 64 | }; |
7351 | 64 | let v7 = C::emit(ctx, &v6); |
7352 | 64 | let v8 = C::writable_gpr_to_gpr(ctx, v2); |
7353 | 64 | // Rule at src/isa/x64/inst.isle line 3869. |
7354 | 64 | return v8; |
7355 | 64 | } |
7356 | | |
7357 | | // Generated as internal constructor for term xmm_min_max_seq. |
7358 | 0 | pub fn constructor_xmm_min_max_seq<C: Context>( |
7359 | 0 | ctx: &mut C, |
7360 | 0 | arg0: Type, |
7361 | 0 | arg1: bool, |
7362 | 0 | arg2: Xmm, |
7363 | 0 | arg3: Xmm, |
7364 | 0 | ) -> Xmm { |
7365 | 0 | let v4 = C::temp_writable_xmm(ctx); |
7366 | 0 | let v5 = &C::operand_size_of_type_32_64(ctx, arg0); |
7367 | 0 | let v6 = MInst::XmmMinMaxSeq { |
7368 | 0 | size: v5.clone(), |
7369 | 0 | is_min: arg1, |
7370 | 0 | lhs: arg2, |
7371 | 0 | rhs: arg3, |
7372 | 0 | dst: v4, |
7373 | 0 | }; |
7374 | 0 | let v7 = C::emit(ctx, &v6); |
7375 | 0 | let v8 = C::writable_xmm_to_xmm(ctx, v4); |
7376 | 0 | // Rule at src/isa/x64/inst.isle line 3877. |
7377 | 0 | return v8; |
7378 | 0 | } |
7379 | | |
7380 | | // Generated as internal constructor for term x64_minss. |
7381 | 0 | pub fn constructor_x64_minss<C: Context>( |
7382 | 0 | ctx: &mut C, |
7383 | 0 | arg0: Xmm, |
7384 | 0 | arg1: &XmmMem, |
7385 | 0 | ) -> Xmm { |
7386 | 0 | let v4 = C::use_avx_simd(ctx); |
7387 | 0 | if v4 == true { |
7388 | 0 | let v6 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
7389 | 0 | let v7 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vminss, arg0, v6); |
7390 | 0 | // Rule at src/isa/x64/inst.isle line 3887. |
7391 | 0 | return v7; |
7392 | 0 | } |
7393 | 0 | let v3 = constructor_xmm_rm_r_unaligned(ctx, &SseOpcode::Minss, arg0, arg1); |
7394 | 0 | // Rule at src/isa/x64/inst.isle line 3885. |
7395 | 0 | return v3; |
7396 | 0 | } |
7397 | | |
7398 | | // Generated as internal constructor for term x64_minsd. |
7399 | 0 | pub fn constructor_x64_minsd<C: Context>( |
7400 | 0 | ctx: &mut C, |
7401 | 0 | arg0: Xmm, |
7402 | 0 | arg1: &XmmMem, |
7403 | 0 | ) -> Xmm { |
7404 | 0 | let v4 = C::use_avx_simd(ctx); |
7405 | 0 | if v4 == true { |
7406 | 0 | let v6 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
7407 | 0 | let v7 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vminsd, arg0, v6); |
7408 | 0 | // Rule at src/isa/x64/inst.isle line 3895. |
7409 | 0 | return v7; |
7410 | 0 | } |
7411 | 0 | let v3 = constructor_xmm_rm_r_unaligned(ctx, &SseOpcode::Minsd, arg0, arg1); |
7412 | 0 | // Rule at src/isa/x64/inst.isle line 3893. |
7413 | 0 | return v3; |
7414 | 0 | } |
7415 | | |
7416 | | // Generated as internal constructor for term x64_minps. |
7417 | 0 | pub fn constructor_x64_minps<C: Context>( |
7418 | 0 | ctx: &mut C, |
7419 | 0 | arg0: Xmm, |
7420 | 0 | arg1: &XmmMem, |
7421 | 0 | ) -> Xmm { |
7422 | 0 | let v5 = C::use_avx_simd(ctx); |
7423 | 0 | if v5 == true { |
7424 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
7425 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vminps, arg0, v7); |
7426 | 0 | // Rule at src/isa/x64/inst.isle line 3903. |
7427 | 0 | return v8; |
7428 | 0 | } |
7429 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
7430 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Minps, arg0, v3); |
7431 | 0 | // Rule at src/isa/x64/inst.isle line 3901. |
7432 | 0 | return v4; |
7433 | 0 | } |
7434 | | |
7435 | | // Generated as internal constructor for term x64_minpd. |
7436 | 0 | pub fn constructor_x64_minpd<C: Context>( |
7437 | 0 | ctx: &mut C, |
7438 | 0 | arg0: Xmm, |
7439 | 0 | arg1: &XmmMem, |
7440 | 0 | ) -> Xmm { |
7441 | 0 | let v5 = C::use_avx_simd(ctx); |
7442 | 0 | if v5 == true { |
7443 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
7444 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vminpd, arg0, v7); |
7445 | 0 | // Rule at src/isa/x64/inst.isle line 3911. |
7446 | 0 | return v8; |
7447 | 0 | } |
7448 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
7449 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Minpd, arg0, v3); |
7450 | 0 | // Rule at src/isa/x64/inst.isle line 3909. |
7451 | 0 | return v4; |
7452 | 0 | } |
7453 | | |
7454 | | // Generated as internal constructor for term x64_maxss. |
7455 | 0 | pub fn constructor_x64_maxss<C: Context>( |
7456 | 0 | ctx: &mut C, |
7457 | 0 | arg0: Xmm, |
7458 | 0 | arg1: &XmmMem, |
7459 | 0 | ) -> Xmm { |
7460 | 0 | let v4 = C::use_avx_simd(ctx); |
7461 | 0 | if v4 == true { |
7462 | 0 | let v6 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
7463 | 0 | let v7 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vmaxss, arg0, v6); |
7464 | 0 | // Rule at src/isa/x64/inst.isle line 3919. |
7465 | 0 | return v7; |
7466 | 0 | } |
7467 | 0 | let v3 = constructor_xmm_rm_r_unaligned(ctx, &SseOpcode::Maxss, arg0, arg1); |
7468 | 0 | // Rule at src/isa/x64/inst.isle line 3917. |
7469 | 0 | return v3; |
7470 | 0 | } |
7471 | | |
7472 | | // Generated as internal constructor for term x64_maxsd. |
7473 | 0 | pub fn constructor_x64_maxsd<C: Context>( |
7474 | 0 | ctx: &mut C, |
7475 | 0 | arg0: Xmm, |
7476 | 0 | arg1: &XmmMem, |
7477 | 0 | ) -> Xmm { |
7478 | 0 | let v4 = C::use_avx_simd(ctx); |
7479 | 0 | if v4 == true { |
7480 | 0 | let v6 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
7481 | 0 | let v7 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vmaxsd, arg0, v6); |
7482 | 0 | // Rule at src/isa/x64/inst.isle line 3927. |
7483 | 0 | return v7; |
7484 | 0 | } |
7485 | 0 | let v3 = constructor_xmm_rm_r_unaligned(ctx, &SseOpcode::Maxsd, arg0, arg1); |
7486 | 0 | // Rule at src/isa/x64/inst.isle line 3925. |
7487 | 0 | return v3; |
7488 | 0 | } |
7489 | | |
7490 | | // Generated as internal constructor for term x64_maxps. |
7491 | 0 | pub fn constructor_x64_maxps<C: Context>( |
7492 | 0 | ctx: &mut C, |
7493 | 0 | arg0: Xmm, |
7494 | 0 | arg1: &XmmMem, |
7495 | 0 | ) -> Xmm { |
7496 | 0 | let v5 = C::use_avx_simd(ctx); |
7497 | 0 | if v5 == true { |
7498 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
7499 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vmaxps, arg0, v7); |
7500 | 0 | // Rule at src/isa/x64/inst.isle line 3935. |
7501 | 0 | return v8; |
7502 | 0 | } |
7503 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
7504 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Maxps, arg0, v3); |
7505 | 0 | // Rule at src/isa/x64/inst.isle line 3933. |
7506 | 0 | return v4; |
7507 | 0 | } |
7508 | | |
7509 | | // Generated as internal constructor for term x64_maxpd. |
7510 | 0 | pub fn constructor_x64_maxpd<C: Context>( |
7511 | 0 | ctx: &mut C, |
7512 | 0 | arg0: Xmm, |
7513 | 0 | arg1: &XmmMem, |
7514 | 0 | ) -> Xmm { |
7515 | 0 | let v5 = C::use_avx_simd(ctx); |
7516 | 0 | if v5 == true { |
7517 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
7518 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vmaxpd, arg0, v7); |
7519 | 0 | // Rule at src/isa/x64/inst.isle line 3943. |
7520 | 0 | return v8; |
7521 | 0 | } |
7522 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
7523 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Maxpd, arg0, v3); |
7524 | 0 | // Rule at src/isa/x64/inst.isle line 3941. |
7525 | 0 | return v4; |
7526 | 0 | } |
7527 | | |
7528 | | // Generated as internal constructor for term xmm_rmir_vex. |
7529 | 0 | pub fn constructor_xmm_rmir_vex<C: Context>( |
7530 | 0 | ctx: &mut C, |
7531 | 0 | arg0: &AvxOpcode, |
7532 | 0 | arg1: Xmm, |
7533 | 0 | arg2: &XmmMemImm, |
7534 | 0 | ) -> Xmm { |
7535 | 0 | let v3 = C::temp_writable_xmm(ctx); |
7536 | 0 | let v4 = MInst::XmmRmiRVex { |
7537 | 0 | op: arg0.clone(), |
7538 | 0 | src1: arg1, |
7539 | 0 | src2: arg2.clone(), |
7540 | 0 | dst: v3, |
7541 | 0 | }; |
7542 | 0 | let v5 = C::emit(ctx, &v4); |
7543 | 0 | let v6 = C::writable_xmm_to_xmm(ctx, v3); |
7544 | 0 | // Rule at src/isa/x64/inst.isle line 3950. |
7545 | 0 | return v6; |
7546 | 0 | } |
7547 | | |
7548 | | // Generated as internal constructor for term xmm_rmr_imm_vex. |
7549 | 0 | pub fn constructor_xmm_rmr_imm_vex<C: Context>( |
7550 | 0 | ctx: &mut C, |
7551 | 0 | arg0: &AvxOpcode, |
7552 | 0 | arg1: Xmm, |
7553 | 0 | arg2: &XmmMem, |
7554 | 0 | arg3: u8, |
7555 | 0 | ) -> Xmm { |
7556 | 0 | let v4 = C::temp_writable_xmm(ctx); |
7557 | 0 | let v5 = MInst::XmmRmRImmVex { |
7558 | 0 | op: arg0.clone(), |
7559 | 0 | src1: arg1, |
7560 | 0 | src2: arg2.clone(), |
7561 | 0 | dst: v4, |
7562 | 0 | imm: arg3, |
7563 | 0 | }; |
7564 | 0 | let v6 = C::emit(ctx, &v5); |
7565 | 0 | let v7 = C::writable_xmm_to_xmm(ctx, v4); |
7566 | 0 | // Rule at src/isa/x64/inst.isle line 3957. |
7567 | 0 | return v7; |
7568 | 0 | } |
7569 | | |
7570 | | // Generated as internal constructor for term xmm_rmr_vex3. |
7571 | 0 | pub fn constructor_xmm_rmr_vex3<C: Context>( |
7572 | 0 | ctx: &mut C, |
7573 | 0 | arg0: &AvxOpcode, |
7574 | 0 | arg1: Xmm, |
7575 | 0 | arg2: Xmm, |
7576 | 0 | arg3: &XmmMem, |
7577 | 0 | ) -> Xmm { |
7578 | 0 | let v4 = C::temp_writable_xmm(ctx); |
7579 | 0 | let v5 = MInst::XmmRmRVex3 { |
7580 | 0 | op: arg0.clone(), |
7581 | 0 | src1: arg1, |
7582 | 0 | src2: arg2, |
7583 | 0 | src3: arg3.clone(), |
7584 | 0 | dst: v4, |
7585 | 0 | }; |
7586 | 0 | let v6 = C::emit(ctx, &v5); |
7587 | 0 | let v7 = C::writable_xmm_to_xmm(ctx, v4); |
7588 | 0 | // Rule at src/isa/x64/inst.isle line 3964. |
7589 | 0 | return v7; |
7590 | 0 | } |
7591 | | |
7592 | | // Generated as internal constructor for term x64_vfmadd213. |
7593 | 0 | pub fn constructor_x64_vfmadd213<C: Context>( |
7594 | 0 | ctx: &mut C, |
7595 | 0 | arg0: Type, |
7596 | 0 | arg1: Xmm, |
7597 | 0 | arg2: Xmm, |
7598 | 0 | arg3: &XmmMem, |
7599 | 0 | ) -> Xmm { |
7600 | 0 | match arg0 { |
7601 | | F32 => { |
7602 | 0 | let v5 = constructor_xmm_rmr_vex3(ctx, &AvxOpcode::Vfmadd213ss, arg1, arg2, arg3); |
7603 | 0 | // Rule at src/isa/x64/inst.isle line 3971. |
7604 | 0 | return v5; |
7605 | | } |
7606 | | F64 => { |
7607 | 0 | let v7 = constructor_xmm_rmr_vex3(ctx, &AvxOpcode::Vfmadd213sd, arg1, arg2, arg3); |
7608 | 0 | // Rule at src/isa/x64/inst.isle line 3972. |
7609 | 0 | return v7; |
7610 | | } |
7611 | | F32X4 => { |
7612 | 0 | let v9 = constructor_xmm_rmr_vex3(ctx, &AvxOpcode::Vfmadd213ps, arg1, arg2, arg3); |
7613 | 0 | // Rule at src/isa/x64/inst.isle line 3973. |
7614 | 0 | return v9; |
7615 | | } |
7616 | | F64X2 => { |
7617 | 0 | let v11 = constructor_xmm_rmr_vex3(ctx, &AvxOpcode::Vfmadd213pd, arg1, arg2, arg3); |
7618 | 0 | // Rule at src/isa/x64/inst.isle line 3974. |
7619 | 0 | return v11; |
7620 | | } |
7621 | 0 | _ => {} |
7622 | 0 | } |
7623 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "x64_vfmadd213", "src/isa/x64/inst.isle line 3970") |
7624 | 0 | } |
7625 | | |
7626 | | // Generated as internal constructor for term x64_vfmadd132. |
7627 | 0 | pub fn constructor_x64_vfmadd132<C: Context>( |
7628 | 0 | ctx: &mut C, |
7629 | 0 | arg0: Type, |
7630 | 0 | arg1: Xmm, |
7631 | 0 | arg2: Xmm, |
7632 | 0 | arg3: &XmmMem, |
7633 | 0 | ) -> Xmm { |
7634 | 0 | match arg0 { |
7635 | | F32 => { |
7636 | 0 | let v5 = constructor_xmm_rmr_vex3(ctx, &AvxOpcode::Vfmadd132ss, arg1, arg2, arg3); |
7637 | 0 | // Rule at src/isa/x64/inst.isle line 3978. |
7638 | 0 | return v5; |
7639 | | } |
7640 | | F64 => { |
7641 | 0 | let v7 = constructor_xmm_rmr_vex3(ctx, &AvxOpcode::Vfmadd132sd, arg1, arg2, arg3); |
7642 | 0 | // Rule at src/isa/x64/inst.isle line 3979. |
7643 | 0 | return v7; |
7644 | | } |
7645 | | F32X4 => { |
7646 | 0 | let v9 = constructor_xmm_rmr_vex3(ctx, &AvxOpcode::Vfmadd132ps, arg1, arg2, arg3); |
7647 | 0 | // Rule at src/isa/x64/inst.isle line 3980. |
7648 | 0 | return v9; |
7649 | | } |
7650 | | F64X2 => { |
7651 | 0 | let v11 = constructor_xmm_rmr_vex3(ctx, &AvxOpcode::Vfmadd132pd, arg1, arg2, arg3); |
7652 | 0 | // Rule at src/isa/x64/inst.isle line 3981. |
7653 | 0 | return v11; |
7654 | | } |
7655 | 0 | _ => {} |
7656 | 0 | } |
7657 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "x64_vfmadd132", "src/isa/x64/inst.isle line 3977") |
7658 | 0 | } |
7659 | | |
7660 | | // Generated as internal constructor for term x64_vfnmadd213. |
7661 | 0 | pub fn constructor_x64_vfnmadd213<C: Context>( |
7662 | 0 | ctx: &mut C, |
7663 | 0 | arg0: Type, |
7664 | 0 | arg1: Xmm, |
7665 | 0 | arg2: Xmm, |
7666 | 0 | arg3: &XmmMem, |
7667 | 0 | ) -> Xmm { |
7668 | 0 | match arg0 { |
7669 | | F32 => { |
7670 | 0 | let v5 = constructor_xmm_rmr_vex3(ctx, &AvxOpcode::Vfnmadd213ss, arg1, arg2, arg3); |
7671 | 0 | // Rule at src/isa/x64/inst.isle line 3985. |
7672 | 0 | return v5; |
7673 | | } |
7674 | | F64 => { |
7675 | 0 | let v7 = constructor_xmm_rmr_vex3(ctx, &AvxOpcode::Vfnmadd213sd, arg1, arg2, arg3); |
7676 | 0 | // Rule at src/isa/x64/inst.isle line 3986. |
7677 | 0 | return v7; |
7678 | | } |
7679 | | F32X4 => { |
7680 | 0 | let v9 = constructor_xmm_rmr_vex3(ctx, &AvxOpcode::Vfnmadd213ps, arg1, arg2, arg3); |
7681 | 0 | // Rule at src/isa/x64/inst.isle line 3987. |
7682 | 0 | return v9; |
7683 | | } |
7684 | | F64X2 => { |
7685 | 0 | let v11 = constructor_xmm_rmr_vex3(ctx, &AvxOpcode::Vfnmadd213pd, arg1, arg2, arg3); |
7686 | 0 | // Rule at src/isa/x64/inst.isle line 3988. |
7687 | 0 | return v11; |
7688 | | } |
7689 | 0 | _ => {} |
7690 | 0 | } |
7691 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "x64_vfnmadd213", "src/isa/x64/inst.isle line 3984") |
7692 | 0 | } |
7693 | | |
7694 | | // Generated as internal constructor for term x64_vfnmadd132. |
7695 | 0 | pub fn constructor_x64_vfnmadd132<C: Context>( |
7696 | 0 | ctx: &mut C, |
7697 | 0 | arg0: Type, |
7698 | 0 | arg1: Xmm, |
7699 | 0 | arg2: Xmm, |
7700 | 0 | arg3: &XmmMem, |
7701 | 0 | ) -> Xmm { |
7702 | 0 | match arg0 { |
7703 | | F32 => { |
7704 | 0 | let v5 = constructor_xmm_rmr_vex3(ctx, &AvxOpcode::Vfnmadd132ss, arg1, arg2, arg3); |
7705 | 0 | // Rule at src/isa/x64/inst.isle line 3992. |
7706 | 0 | return v5; |
7707 | | } |
7708 | | F64 => { |
7709 | 0 | let v7 = constructor_xmm_rmr_vex3(ctx, &AvxOpcode::Vfnmadd132sd, arg1, arg2, arg3); |
7710 | 0 | // Rule at src/isa/x64/inst.isle line 3993. |
7711 | 0 | return v7; |
7712 | | } |
7713 | | F32X4 => { |
7714 | 0 | let v9 = constructor_xmm_rmr_vex3(ctx, &AvxOpcode::Vfnmadd132ps, arg1, arg2, arg3); |
7715 | 0 | // Rule at src/isa/x64/inst.isle line 3994. |
7716 | 0 | return v9; |
7717 | | } |
7718 | | F64X2 => { |
7719 | 0 | let v11 = constructor_xmm_rmr_vex3(ctx, &AvxOpcode::Vfnmadd132pd, arg1, arg2, arg3); |
7720 | 0 | // Rule at src/isa/x64/inst.isle line 3995. |
7721 | 0 | return v11; |
7722 | | } |
7723 | 0 | _ => {} |
7724 | 0 | } |
7725 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "x64_vfnmadd132", "src/isa/x64/inst.isle line 3991") |
7726 | 0 | } |
7727 | | |
7728 | | // Generated as internal constructor for term x64_sqrtss. |
7729 | 0 | pub fn constructor_x64_sqrtss<C: Context>( |
7730 | 0 | ctx: &mut C, |
7731 | 0 | arg0: &XmmMem, |
7732 | 0 | ) -> Xmm { |
7733 | 0 | let v3 = C::use_avx_simd(ctx); |
7734 | 0 | if v3 == true { |
7735 | 0 | let v5 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vsqrtss, arg0); |
7736 | 0 | // Rule at src/isa/x64/inst.isle line 4000. |
7737 | 0 | return v5; |
7738 | 0 | } |
7739 | 0 | let v2 = constructor_xmm_unary_rm_r_unaligned(ctx, &SseOpcode::Sqrtss, arg0); |
7740 | 0 | // Rule at src/isa/x64/inst.isle line 3999. |
7741 | 0 | return v2; |
7742 | 0 | } |
7743 | | |
7744 | | // Generated as internal constructor for term x64_sqrtsd. |
7745 | 0 | pub fn constructor_x64_sqrtsd<C: Context>( |
7746 | 0 | ctx: &mut C, |
7747 | 0 | arg0: &XmmMem, |
7748 | 0 | ) -> Xmm { |
7749 | 0 | let v3 = C::use_avx_simd(ctx); |
7750 | 0 | if v3 == true { |
7751 | 0 | let v5 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vsqrtsd, arg0); |
7752 | 0 | // Rule at src/isa/x64/inst.isle line 4007. |
7753 | 0 | return v5; |
7754 | 0 | } |
7755 | 0 | let v2 = constructor_xmm_unary_rm_r_unaligned(ctx, &SseOpcode::Sqrtsd, arg0); |
7756 | 0 | // Rule at src/isa/x64/inst.isle line 4006. |
7757 | 0 | return v2; |
7758 | 0 | } |
7759 | | |
7760 | | // Generated as internal constructor for term x64_sqrtps. |
7761 | 0 | pub fn constructor_x64_sqrtps<C: Context>( |
7762 | 0 | ctx: &mut C, |
7763 | 0 | arg0: &XmmMem, |
7764 | 0 | ) -> Xmm { |
7765 | 0 | let v4 = C::use_avx_simd(ctx); |
7766 | 0 | if v4 == true { |
7767 | 0 | let v6 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vsqrtps, arg0); |
7768 | 0 | // Rule at src/isa/x64/inst.isle line 4014. |
7769 | 0 | return v6; |
7770 | 0 | } |
7771 | 0 | let v2 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg0); |
7772 | 0 | let v3 = constructor_xmm_unary_rm_r(ctx, &SseOpcode::Sqrtps, v2); |
7773 | 0 | // Rule at src/isa/x64/inst.isle line 4013. |
7774 | 0 | return v3; |
7775 | 0 | } |
7776 | | |
7777 | | // Generated as internal constructor for term x64_sqrtpd. |
7778 | 0 | pub fn constructor_x64_sqrtpd<C: Context>( |
7779 | 0 | ctx: &mut C, |
7780 | 0 | arg0: &XmmMem, |
7781 | 0 | ) -> Xmm { |
7782 | 0 | let v4 = C::use_avx_simd(ctx); |
7783 | 0 | if v4 == true { |
7784 | 0 | let v6 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vsqrtpd, arg0); |
7785 | 0 | // Rule at src/isa/x64/inst.isle line 4021. |
7786 | 0 | return v6; |
7787 | 0 | } |
7788 | 0 | let v2 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg0); |
7789 | 0 | let v3 = constructor_xmm_unary_rm_r(ctx, &SseOpcode::Sqrtpd, v2); |
7790 | 0 | // Rule at src/isa/x64/inst.isle line 4020. |
7791 | 0 | return v3; |
7792 | 0 | } |
7793 | | |
7794 | | // Generated as internal constructor for term x64_cvtss2sd. |
7795 | 0 | pub fn constructor_x64_cvtss2sd<C: Context>( |
7796 | 0 | ctx: &mut C, |
7797 | 0 | arg0: &XmmMem, |
7798 | 0 | ) -> Xmm { |
7799 | 0 | let v3 = C::use_avx_simd(ctx); |
7800 | 0 | if v3 == true { |
7801 | 0 | let v5 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vcvtss2sd, arg0); |
7802 | 0 | // Rule at src/isa/x64/inst.isle line 4028. |
7803 | 0 | return v5; |
7804 | 0 | } |
7805 | 0 | let v2 = constructor_xmm_unary_rm_r_unaligned(ctx, &SseOpcode::Cvtss2sd, arg0); |
7806 | 0 | // Rule at src/isa/x64/inst.isle line 4027. |
7807 | 0 | return v2; |
7808 | 0 | } |
7809 | | |
7810 | | // Generated as internal constructor for term x64_cvtsd2ss. |
7811 | 0 | pub fn constructor_x64_cvtsd2ss<C: Context>( |
7812 | 0 | ctx: &mut C, |
7813 | 0 | arg0: &XmmMem, |
7814 | 0 | ) -> Xmm { |
7815 | 0 | let v3 = C::use_avx_simd(ctx); |
7816 | 0 | if v3 == true { |
7817 | 0 | let v5 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vcvtsd2ss, arg0); |
7818 | 0 | // Rule at src/isa/x64/inst.isle line 4035. |
7819 | 0 | return v5; |
7820 | 0 | } |
7821 | 0 | let v2 = constructor_xmm_unary_rm_r_unaligned(ctx, &SseOpcode::Cvtsd2ss, arg0); |
7822 | 0 | // Rule at src/isa/x64/inst.isle line 4034. |
7823 | 0 | return v2; |
7824 | 0 | } |
7825 | | |
7826 | | // Generated as internal constructor for term x64_cvtdq2ps. |
7827 | 0 | pub fn constructor_x64_cvtdq2ps<C: Context>( |
7828 | 0 | ctx: &mut C, |
7829 | 0 | arg0: &XmmMem, |
7830 | 0 | ) -> Xmm { |
7831 | 0 | let v4 = C::use_avx_simd(ctx); |
7832 | 0 | if v4 == true { |
7833 | 0 | let v6 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vcvtdq2ps, arg0); |
7834 | 0 | // Rule at src/isa/x64/inst.isle line 4042. |
7835 | 0 | return v6; |
7836 | 0 | } |
7837 | 0 | let v2 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg0); |
7838 | 0 | let v3 = constructor_xmm_unary_rm_r(ctx, &SseOpcode::Cvtdq2ps, v2); |
7839 | 0 | // Rule at src/isa/x64/inst.isle line 4041. |
7840 | 0 | return v3; |
7841 | 0 | } |
7842 | | |
7843 | | // Generated as internal constructor for term x64_cvtps2pd. |
7844 | 0 | pub fn constructor_x64_cvtps2pd<C: Context>( |
7845 | 0 | ctx: &mut C, |
7846 | 0 | arg0: &XmmMem, |
7847 | 0 | ) -> Xmm { |
7848 | 0 | let v4 = C::use_avx_simd(ctx); |
7849 | 0 | if v4 == true { |
7850 | 0 | let v6 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vcvtps2pd, arg0); |
7851 | 0 | // Rule at src/isa/x64/inst.isle line 4049. |
7852 | 0 | return v6; |
7853 | 0 | } |
7854 | 0 | let v2 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg0); |
7855 | 0 | let v3 = constructor_xmm_unary_rm_r(ctx, &SseOpcode::Cvtps2pd, v2); |
7856 | 0 | // Rule at src/isa/x64/inst.isle line 4048. |
7857 | 0 | return v3; |
7858 | 0 | } |
7859 | | |
7860 | | // Generated as internal constructor for term x64_cvtpd2ps. |
7861 | 0 | pub fn constructor_x64_cvtpd2ps<C: Context>( |
7862 | 0 | ctx: &mut C, |
7863 | 0 | arg0: &XmmMem, |
7864 | 0 | ) -> Xmm { |
7865 | 0 | let v4 = C::use_avx_simd(ctx); |
7866 | 0 | if v4 == true { |
7867 | 0 | let v6 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vcvtpd2ps, arg0); |
7868 | 0 | // Rule at src/isa/x64/inst.isle line 4056. |
7869 | 0 | return v6; |
7870 | 0 | } |
7871 | 0 | let v2 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg0); |
7872 | 0 | let v3 = constructor_xmm_unary_rm_r(ctx, &SseOpcode::Cvtpd2ps, v2); |
7873 | 0 | // Rule at src/isa/x64/inst.isle line 4055. |
7874 | 0 | return v3; |
7875 | 0 | } |
7876 | | |
7877 | | // Generated as internal constructor for term x64_cvtdq2pd. |
7878 | 0 | pub fn constructor_x64_cvtdq2pd<C: Context>( |
7879 | 0 | ctx: &mut C, |
7880 | 0 | arg0: &XmmMem, |
7881 | 0 | ) -> Xmm { |
7882 | 0 | let v4 = C::use_avx_simd(ctx); |
7883 | 0 | if v4 == true { |
7884 | 0 | let v6 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vcvtdq2pd, arg0); |
7885 | 0 | // Rule at src/isa/x64/inst.isle line 4063. |
7886 | 0 | return v6; |
7887 | 0 | } |
7888 | 0 | let v2 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg0); |
7889 | 0 | let v3 = constructor_xmm_unary_rm_r(ctx, &SseOpcode::Cvtdq2pd, v2); |
7890 | 0 | // Rule at src/isa/x64/inst.isle line 4062. |
7891 | 0 | return v3; |
7892 | 0 | } |
7893 | | |
7894 | | // Generated as internal constructor for term x64_cvtsi2ss. |
7895 | 0 | pub fn constructor_x64_cvtsi2ss<C: Context>( |
7896 | 0 | ctx: &mut C, |
7897 | 0 | arg0: Type, |
7898 | 0 | arg1: &GprMem, |
7899 | 0 | ) -> Xmm { |
7900 | 0 | let v5 = C::use_avx_simd(ctx); |
7901 | 0 | if v5 == true { |
7902 | 0 | let v3 = &C::raw_operand_size_of_type(ctx, arg0); |
7903 | 0 | let v7 = constructor_gpr_to_xmm_vex(ctx, &AvxOpcode::Vcvtsi2ss, arg1, v3); |
7904 | 0 | // Rule at src/isa/x64/inst.isle line 4071. |
7905 | 0 | return v7; |
7906 | 0 | } |
7907 | 0 | let v3 = &C::raw_operand_size_of_type(ctx, arg0); |
7908 | 0 | let v4 = constructor_gpr_to_xmm(ctx, &SseOpcode::Cvtsi2ss, arg1, v3); |
7909 | 0 | // Rule at src/isa/x64/inst.isle line 4069. |
7910 | 0 | return v4; |
7911 | 0 | } |
7912 | | |
7913 | | // Generated as internal constructor for term x64_cvtsi2sd. |
7914 | 0 | pub fn constructor_x64_cvtsi2sd<C: Context>( |
7915 | 0 | ctx: &mut C, |
7916 | 0 | arg0: Type, |
7917 | 0 | arg1: &GprMem, |
7918 | 0 | ) -> Xmm { |
7919 | 0 | let v5 = C::use_avx_simd(ctx); |
7920 | 0 | if v5 == true { |
7921 | 0 | let v3 = &C::raw_operand_size_of_type(ctx, arg0); |
7922 | 0 | let v7 = constructor_gpr_to_xmm_vex(ctx, &AvxOpcode::Vcvtsi2sd, arg1, v3); |
7923 | 0 | // Rule at src/isa/x64/inst.isle line 4079. |
7924 | 0 | return v7; |
7925 | 0 | } |
7926 | 0 | let v3 = &C::raw_operand_size_of_type(ctx, arg0); |
7927 | 0 | let v4 = constructor_gpr_to_xmm(ctx, &SseOpcode::Cvtsi2sd, arg1, v3); |
7928 | 0 | // Rule at src/isa/x64/inst.isle line 4077. |
7929 | 0 | return v4; |
7930 | 0 | } |
7931 | | |
7932 | | // Generated as internal constructor for term x64_cvttps2dq. |
7933 | 0 | pub fn constructor_x64_cvttps2dq<C: Context>( |
7934 | 0 | ctx: &mut C, |
7935 | 0 | arg0: &XmmMem, |
7936 | 0 | ) -> Xmm { |
7937 | 0 | let v4 = C::use_avx_simd(ctx); |
7938 | 0 | if v4 == true { |
7939 | 0 | let v6 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vcvttps2dq, arg0); |
7940 | 0 | // Rule at src/isa/x64/inst.isle line 4087. |
7941 | 0 | return v6; |
7942 | 0 | } |
7943 | 0 | let v2 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg0); |
7944 | 0 | let v3 = constructor_xmm_unary_rm_r(ctx, &SseOpcode::Cvttps2dq, v2); |
7945 | 0 | // Rule at src/isa/x64/inst.isle line 4085. |
7946 | 0 | return v3; |
7947 | 0 | } |
7948 | | |
7949 | | // Generated as internal constructor for term x64_cvttpd2dq. |
7950 | 0 | pub fn constructor_x64_cvttpd2dq<C: Context>( |
7951 | 0 | ctx: &mut C, |
7952 | 0 | arg0: &XmmMem, |
7953 | 0 | ) -> Xmm { |
7954 | 0 | let v4 = C::use_avx_simd(ctx); |
7955 | 0 | if v4 == true { |
7956 | 0 | let v6 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vcvttpd2dq, arg0); |
7957 | 0 | // Rule at src/isa/x64/inst.isle line 4095. |
7958 | 0 | return v6; |
7959 | 0 | } |
7960 | 0 | let v2 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg0); |
7961 | 0 | let v3 = constructor_xmm_unary_rm_r(ctx, &SseOpcode::Cvttpd2dq, v2); |
7962 | 0 | // Rule at src/isa/x64/inst.isle line 4093. |
7963 | 0 | return v3; |
7964 | 0 | } |
7965 | | |
7966 | | // Generated as internal constructor for term cvt_u64_to_float_seq. |
7967 | 0 | pub fn constructor_cvt_u64_to_float_seq<C: Context>( |
7968 | 0 | ctx: &mut C, |
7969 | 0 | arg0: Type, |
7970 | 0 | arg1: Gpr, |
7971 | 0 | ) -> Xmm { |
7972 | 0 | let v2 = &C::raw_operand_size_of_type(ctx, arg0); |
7973 | 0 | let v3 = C::temp_writable_xmm(ctx); |
7974 | 0 | let v4 = C::temp_writable_gpr(ctx); |
7975 | 0 | let v5 = C::temp_writable_gpr(ctx); |
7976 | 0 | let v6 = MInst::CvtUint64ToFloatSeq { |
7977 | 0 | dst_size: v2.clone(), |
7978 | 0 | src: arg1, |
7979 | 0 | dst: v3, |
7980 | 0 | tmp_gpr1: v4, |
7981 | 0 | tmp_gpr2: v5, |
7982 | 0 | }; |
7983 | 0 | let v7 = C::emit(ctx, &v6); |
7984 | 0 | let v8 = C::writable_xmm_to_xmm(ctx, v3); |
7985 | 0 | // Rule at src/isa/x64/inst.isle line 4100. |
7986 | 0 | return v8; |
7987 | 0 | } |
7988 | | |
7989 | | // Generated as internal constructor for term cvt_float_to_uint_seq. |
7990 | 0 | pub fn constructor_cvt_float_to_uint_seq<C: Context>( |
7991 | 0 | ctx: &mut C, |
7992 | 0 | arg0: Type, |
7993 | 0 | arg1: Value, |
7994 | 0 | arg2: bool, |
7995 | 0 | ) -> Gpr { |
7996 | 0 | let v4 = &C::raw_operand_size_of_type(ctx, arg0); |
7997 | 0 | let v2 = C::value_type(ctx, arg1); |
7998 | 0 | let v5 = &C::raw_operand_size_of_type(ctx, v2); |
7999 | 0 | let v6 = C::temp_writable_gpr(ctx); |
8000 | 0 | let v7 = C::temp_writable_xmm(ctx); |
8001 | 0 | let v8 = C::temp_writable_xmm(ctx); |
8002 | 0 | let v9 = C::temp_writable_gpr(ctx); |
8003 | 0 | let v10 = constructor_put_in_xmm(ctx, arg1); |
8004 | 0 | let v11 = MInst::CvtFloatToUintSeq { |
8005 | 0 | dst_size: v4.clone(), |
8006 | 0 | src_size: v5.clone(), |
8007 | 0 | is_saturating: arg2, |
8008 | 0 | src: v10, |
8009 | 0 | dst: v6, |
8010 | 0 | tmp_gpr: v9, |
8011 | 0 | tmp_xmm: v7, |
8012 | 0 | tmp_xmm2: v8, |
8013 | 0 | }; |
8014 | 0 | let v12 = C::emit(ctx, &v11); |
8015 | 0 | let v13 = C::writable_gpr_to_gpr(ctx, v6); |
8016 | 0 | // Rule at src/isa/x64/inst.isle line 4109. |
8017 | 0 | return v13; |
8018 | 0 | } |
8019 | | |
8020 | | // Generated as internal constructor for term cvt_float_to_sint_seq. |
8021 | 0 | pub fn constructor_cvt_float_to_sint_seq<C: Context>( |
8022 | 0 | ctx: &mut C, |
8023 | 0 | arg0: Type, |
8024 | 0 | arg1: Value, |
8025 | 0 | arg2: bool, |
8026 | 0 | ) -> Gpr { |
8027 | 0 | let v4 = &C::raw_operand_size_of_type(ctx, arg0); |
8028 | 0 | let v2 = C::value_type(ctx, arg1); |
8029 | 0 | let v5 = &C::raw_operand_size_of_type(ctx, v2); |
8030 | 0 | let v6 = C::temp_writable_gpr(ctx); |
8031 | 0 | let v7 = C::temp_writable_xmm(ctx); |
8032 | 0 | let v8 = C::temp_writable_gpr(ctx); |
8033 | 0 | let v9 = constructor_put_in_xmm(ctx, arg1); |
8034 | 0 | let v10 = MInst::CvtFloatToSintSeq { |
8035 | 0 | dst_size: v4.clone(), |
8036 | 0 | src_size: v5.clone(), |
8037 | 0 | is_saturating: arg2, |
8038 | 0 | src: v9, |
8039 | 0 | dst: v6, |
8040 | 0 | tmp_gpr: v8, |
8041 | 0 | tmp_xmm: v7, |
8042 | 0 | }; |
8043 | 0 | let v11 = C::emit(ctx, &v10); |
8044 | 0 | let v12 = C::writable_gpr_to_gpr(ctx, v6); |
8045 | 0 | // Rule at src/isa/x64/inst.isle line 4121. |
8046 | 0 | return v12; |
8047 | 0 | } |
8048 | | |
8049 | | // Generated as internal constructor for term x64_pcmpeq. |
8050 | 0 | pub fn constructor_x64_pcmpeq<C: Context>( |
8051 | 0 | ctx: &mut C, |
8052 | 0 | arg0: Type, |
8053 | 0 | arg1: Xmm, |
8054 | 0 | arg2: &XmmMem, |
8055 | 0 | ) -> Xmm { |
8056 | 0 | match arg0 { |
8057 | | I8X16 => { |
8058 | 0 | let v3 = constructor_x64_pcmpeqb(ctx, arg1, arg2); |
8059 | 0 | // Rule at src/isa/x64/inst.isle line 4139. |
8060 | 0 | return v3; |
8061 | | } |
8062 | | I16X8 => { |
8063 | 0 | let v4 = constructor_x64_pcmpeqw(ctx, arg1, arg2); |
8064 | 0 | // Rule at src/isa/x64/inst.isle line 4140. |
8065 | 0 | return v4; |
8066 | | } |
8067 | | I32X4 => { |
8068 | 0 | let v5 = constructor_x64_pcmpeqd(ctx, arg1, arg2); |
8069 | 0 | // Rule at src/isa/x64/inst.isle line 4141. |
8070 | 0 | return v5; |
8071 | | } |
8072 | | I64X2 => { |
8073 | 0 | let v6 = constructor_x64_pcmpeqq(ctx, arg1, arg2); |
8074 | 0 | // Rule at src/isa/x64/inst.isle line 4142. |
8075 | 0 | return v6; |
8076 | | } |
8077 | 0 | _ => {} |
8078 | 0 | } |
8079 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "x64_pcmpeq", "src/isa/x64/inst.isle line 4138") |
8080 | 0 | } |
8081 | | |
8082 | | // Generated as internal constructor for term x64_pcmpeqb. |
8083 | 0 | pub fn constructor_x64_pcmpeqb<C: Context>( |
8084 | 0 | ctx: &mut C, |
8085 | 0 | arg0: Xmm, |
8086 | 0 | arg1: &XmmMem, |
8087 | 0 | ) -> Xmm { |
8088 | 0 | let v5 = C::use_avx_simd(ctx); |
8089 | 0 | if v5 == true { |
8090 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
8091 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpcmpeqb, arg0, v7); |
8092 | 0 | // Rule at src/isa/x64/inst.isle line 4146. |
8093 | 0 | return v8; |
8094 | 0 | } |
8095 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
8096 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pcmpeqb, arg0, v3); |
8097 | 0 | // Rule at src/isa/x64/inst.isle line 4145. |
8098 | 0 | return v4; |
8099 | 0 | } |
8100 | | |
8101 | | // Generated as internal constructor for term x64_pcmpeqw. |
8102 | 0 | pub fn constructor_x64_pcmpeqw<C: Context>( |
8103 | 0 | ctx: &mut C, |
8104 | 0 | arg0: Xmm, |
8105 | 0 | arg1: &XmmMem, |
8106 | 0 | ) -> Xmm { |
8107 | 0 | let v5 = C::use_avx_simd(ctx); |
8108 | 0 | if v5 == true { |
8109 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
8110 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpcmpeqw, arg0, v7); |
8111 | 0 | // Rule at src/isa/x64/inst.isle line 4151. |
8112 | 0 | return v8; |
8113 | 0 | } |
8114 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
8115 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pcmpeqw, arg0, v3); |
8116 | 0 | // Rule at src/isa/x64/inst.isle line 4150. |
8117 | 0 | return v4; |
8118 | 0 | } |
8119 | | |
8120 | | // Generated as internal constructor for term x64_pcmpeqd. |
8121 | 0 | pub fn constructor_x64_pcmpeqd<C: Context>( |
8122 | 0 | ctx: &mut C, |
8123 | 0 | arg0: Xmm, |
8124 | 0 | arg1: &XmmMem, |
8125 | 0 | ) -> Xmm { |
8126 | 0 | let v5 = C::use_avx_simd(ctx); |
8127 | 0 | if v5 == true { |
8128 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
8129 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpcmpeqd, arg0, v7); |
8130 | 0 | // Rule at src/isa/x64/inst.isle line 4156. |
8131 | 0 | return v8; |
8132 | 0 | } |
8133 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
8134 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pcmpeqd, arg0, v3); |
8135 | 0 | // Rule at src/isa/x64/inst.isle line 4155. |
8136 | 0 | return v4; |
8137 | 0 | } |
8138 | | |
8139 | | // Generated as internal constructor for term x64_pcmpeqq. |
8140 | 0 | pub fn constructor_x64_pcmpeqq<C: Context>( |
8141 | 0 | ctx: &mut C, |
8142 | 0 | arg0: Xmm, |
8143 | 0 | arg1: &XmmMem, |
8144 | 0 | ) -> Xmm { |
8145 | 0 | let v5 = C::use_avx_simd(ctx); |
8146 | 0 | if v5 == true { |
8147 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
8148 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpcmpeqq, arg0, v7); |
8149 | 0 | // Rule at src/isa/x64/inst.isle line 4161. |
8150 | 0 | return v8; |
8151 | 0 | } |
8152 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
8153 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pcmpeqq, arg0, v3); |
8154 | 0 | // Rule at src/isa/x64/inst.isle line 4160. |
8155 | 0 | return v4; |
8156 | 0 | } |
8157 | | |
8158 | | // Generated as internal constructor for term x64_pcmpgt. |
8159 | 0 | pub fn constructor_x64_pcmpgt<C: Context>( |
8160 | 0 | ctx: &mut C, |
8161 | 0 | arg0: Type, |
8162 | 0 | arg1: Xmm, |
8163 | 0 | arg2: &XmmMem, |
8164 | 0 | ) -> Xmm { |
8165 | 0 | match arg0 { |
8166 | | I8X16 => { |
8167 | 0 | let v3 = constructor_x64_pcmpgtb(ctx, arg1, arg2); |
8168 | 0 | // Rule at src/isa/x64/inst.isle line 4167. |
8169 | 0 | return v3; |
8170 | | } |
8171 | | I16X8 => { |
8172 | 0 | let v4 = constructor_x64_pcmpgtw(ctx, arg1, arg2); |
8173 | 0 | // Rule at src/isa/x64/inst.isle line 4168. |
8174 | 0 | return v4; |
8175 | | } |
8176 | | I32X4 => { |
8177 | 0 | let v5 = constructor_x64_pcmpgtd(ctx, arg1, arg2); |
8178 | 0 | // Rule at src/isa/x64/inst.isle line 4169. |
8179 | 0 | return v5; |
8180 | | } |
8181 | | I64X2 => { |
8182 | 0 | let v6 = constructor_x64_pcmpgtq(ctx, arg1, arg2); |
8183 | 0 | // Rule at src/isa/x64/inst.isle line 4170. |
8184 | 0 | return v6; |
8185 | | } |
8186 | 0 | _ => {} |
8187 | 0 | } |
8188 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "x64_pcmpgt", "src/isa/x64/inst.isle line 4166") |
8189 | 0 | } |
8190 | | |
8191 | | // Generated as internal constructor for term x64_pcmpgtb. |
8192 | 0 | pub fn constructor_x64_pcmpgtb<C: Context>( |
8193 | 0 | ctx: &mut C, |
8194 | 0 | arg0: Xmm, |
8195 | 0 | arg1: &XmmMem, |
8196 | 0 | ) -> Xmm { |
8197 | 0 | let v5 = C::use_avx_simd(ctx); |
8198 | 0 | if v5 == true { |
8199 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
8200 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpcmpgtb, arg0, v7); |
8201 | 0 | // Rule at src/isa/x64/inst.isle line 4174. |
8202 | 0 | return v8; |
8203 | 0 | } |
8204 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
8205 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pcmpgtb, arg0, v3); |
8206 | 0 | // Rule at src/isa/x64/inst.isle line 4173. |
8207 | 0 | return v4; |
8208 | 0 | } |
8209 | | |
8210 | | // Generated as internal constructor for term x64_pcmpgtw. |
8211 | 0 | pub fn constructor_x64_pcmpgtw<C: Context>( |
8212 | 0 | ctx: &mut C, |
8213 | 0 | arg0: Xmm, |
8214 | 0 | arg1: &XmmMem, |
8215 | 0 | ) -> Xmm { |
8216 | 0 | let v5 = C::use_avx_simd(ctx); |
8217 | 0 | if v5 == true { |
8218 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
8219 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpcmpgtw, arg0, v7); |
8220 | 0 | // Rule at src/isa/x64/inst.isle line 4179. |
8221 | 0 | return v8; |
8222 | 0 | } |
8223 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
8224 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pcmpgtw, arg0, v3); |
8225 | 0 | // Rule at src/isa/x64/inst.isle line 4178. |
8226 | 0 | return v4; |
8227 | 0 | } |
8228 | | |
8229 | | // Generated as internal constructor for term x64_pcmpgtd. |
8230 | 0 | pub fn constructor_x64_pcmpgtd<C: Context>( |
8231 | 0 | ctx: &mut C, |
8232 | 0 | arg0: Xmm, |
8233 | 0 | arg1: &XmmMem, |
8234 | 0 | ) -> Xmm { |
8235 | 0 | let v5 = C::use_avx_simd(ctx); |
8236 | 0 | if v5 == true { |
8237 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
8238 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpcmpgtd, arg0, v7); |
8239 | 0 | // Rule at src/isa/x64/inst.isle line 4184. |
8240 | 0 | return v8; |
8241 | 0 | } |
8242 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
8243 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pcmpgtd, arg0, v3); |
8244 | 0 | // Rule at src/isa/x64/inst.isle line 4183. |
8245 | 0 | return v4; |
8246 | 0 | } |
8247 | | |
8248 | | // Generated as internal constructor for term x64_pcmpgtq. |
8249 | 0 | pub fn constructor_x64_pcmpgtq<C: Context>( |
8250 | 0 | ctx: &mut C, |
8251 | 0 | arg0: Xmm, |
8252 | 0 | arg1: &XmmMem, |
8253 | 0 | ) -> Xmm { |
8254 | 0 | let v5 = C::use_avx_simd(ctx); |
8255 | 0 | if v5 == true { |
8256 | 0 | let v7 = &C::xmm_mem_to_xmm_mem_imm(ctx, arg1); |
8257 | 0 | let v8 = constructor_xmm_rmir_vex(ctx, &AvxOpcode::Vpcmpgtq, arg0, v7); |
8258 | 0 | // Rule at src/isa/x64/inst.isle line 4189. |
8259 | 0 | return v8; |
8260 | 0 | } |
8261 | 0 | let v3 = &C::xmm_mem_to_xmm_mem_aligned(ctx, arg1); |
8262 | 0 | let v4 = constructor_xmm_rm_r(ctx, &SseOpcode::Pcmpgtq, arg0, v3); |
8263 | 0 | // Rule at src/isa/x64/inst.isle line 4188. |
8264 | 0 | return v4; |
8265 | 0 | } |
8266 | | |
8267 | | // Generated as internal constructor for term alu_rm. |
8268 | 1.44k | pub fn constructor_alu_rm<C: Context>( |
8269 | 1.44k | ctx: &mut C, |
8270 | 1.44k | arg0: Type, |
8271 | 1.44k | arg1: &AluRmiROpcode, |
8272 | 1.44k | arg2: &Amode, |
8273 | 1.44k | arg3: Gpr, |
8274 | 1.44k | ) -> SideEffectNoResult { |
8275 | 1.44k | let v4 = &C::operand_size_of_type_32_64(ctx, arg0); |
8276 | 1.44k | let v5 = &C::amode_to_synthetic_amode(ctx, arg2); |
8277 | 1.44k | let v6 = MInst::AluRM { |
8278 | 1.44k | size: v4.clone(), |
8279 | 1.44k | op: arg1.clone(), |
8280 | 1.44k | src1_dst: v5.clone(), |
8281 | 1.44k | src2: arg3, |
8282 | 1.44k | }; |
8283 | 1.44k | let v7 = SideEffectNoResult::Inst { |
8284 | 1.44k | inst: v6, |
8285 | 1.44k | }; |
8286 | 1.44k | // Rule at src/isa/x64/inst.isle line 4195. |
8287 | 1.44k | return v7; |
8288 | 1.44k | } |
8289 | | |
8290 | | // Generated as internal constructor for term x64_add_mem. |
8291 | 1.44k | pub fn constructor_x64_add_mem<C: Context>( |
8292 | 1.44k | ctx: &mut C, |
8293 | 1.44k | arg0: Type, |
8294 | 1.44k | arg1: &Amode, |
8295 | 1.44k | arg2: Gpr, |
8296 | 1.44k | ) -> SideEffectNoResult { |
8297 | 1.44k | let v4 = &constructor_alu_rm(ctx, arg0, &AluRmiROpcode::Add, arg1, arg2); |
8298 | 1.44k | // Rule at src/isa/x64/inst.isle line 4200. |
8299 | 1.44k | return v4.clone(); |
8300 | 1.44k | } |
8301 | | |
8302 | | // Generated as internal constructor for term x64_sub_mem. |
8303 | 5 | pub fn constructor_x64_sub_mem<C: Context>( |
8304 | 5 | ctx: &mut C, |
8305 | 5 | arg0: Type, |
8306 | 5 | arg1: &Amode, |
8307 | 5 | arg2: Gpr, |
8308 | 5 | ) -> SideEffectNoResult { |
8309 | 5 | let v4 = &constructor_alu_rm(ctx, arg0, &AluRmiROpcode::Sub, arg1, arg2); |
8310 | 5 | // Rule at src/isa/x64/inst.isle line 4204. |
8311 | 5 | return v4.clone(); |
8312 | 5 | } |
8313 | | |
8314 | | // Generated as internal constructor for term x64_and_mem. |
8315 | 0 | pub fn constructor_x64_and_mem<C: Context>( |
8316 | 0 | ctx: &mut C, |
8317 | 0 | arg0: Type, |
8318 | 0 | arg1: &Amode, |
8319 | 0 | arg2: Gpr, |
8320 | 0 | ) -> SideEffectNoResult { |
8321 | 0 | let v4 = &constructor_alu_rm(ctx, arg0, &AluRmiROpcode::And, arg1, arg2); |
8322 | 0 | // Rule at src/isa/x64/inst.isle line 4208. |
8323 | 0 | return v4.clone(); |
8324 | 0 | } |
8325 | | |
8326 | | // Generated as internal constructor for term x64_or_mem. |
8327 | 0 | pub fn constructor_x64_or_mem<C: Context>( |
8328 | 0 | ctx: &mut C, |
8329 | 0 | arg0: Type, |
8330 | 0 | arg1: &Amode, |
8331 | 0 | arg2: Gpr, |
8332 | 0 | ) -> SideEffectNoResult { |
8333 | 0 | let v4 = &constructor_alu_rm(ctx, arg0, &AluRmiROpcode::Or, arg1, arg2); |
8334 | 0 | // Rule at src/isa/x64/inst.isle line 4212. |
8335 | 0 | return v4.clone(); |
8336 | 0 | } |
8337 | | |
8338 | | // Generated as internal constructor for term x64_xor_mem. |
8339 | 0 | pub fn constructor_x64_xor_mem<C: Context>( |
8340 | 0 | ctx: &mut C, |
8341 | 0 | arg0: Type, |
8342 | 0 | arg1: &Amode, |
8343 | 0 | arg2: Gpr, |
8344 | 0 | ) -> SideEffectNoResult { |
8345 | 0 | let v4 = &constructor_alu_rm(ctx, arg0, &AluRmiROpcode::Xor, arg1, arg2); |
8346 | 0 | // Rule at src/isa/x64/inst.isle line 4216. |
8347 | 0 | return v4.clone(); |
8348 | 0 | } |
8349 | | |
8350 | | // Generated as internal constructor for term trap_if. |
8351 | 0 | pub fn constructor_trap_if<C: Context>( |
8352 | 0 | ctx: &mut C, |
8353 | 0 | arg0: &CC, |
8354 | 0 | arg1: &TrapCode, |
8355 | 0 | ) -> ConsumesFlags { |
8356 | 0 | let v2 = MInst::TrapIf { |
8357 | 0 | cc: arg0.clone(), |
8358 | 0 | trap_code: arg1.clone(), |
8359 | 0 | }; |
8360 | 0 | let v3 = ConsumesFlags::ConsumesFlagsSideEffect { |
8361 | 0 | inst: v2, |
8362 | 0 | }; |
8363 | 0 | // Rule at src/isa/x64/inst.isle line 4221. |
8364 | 0 | return v3; |
8365 | 0 | } |
8366 | | |
8367 | | // Generated as internal constructor for term trap_if_and. |
8368 | 0 | pub fn constructor_trap_if_and<C: Context>( |
8369 | 0 | ctx: &mut C, |
8370 | 0 | arg0: &CC, |
8371 | 0 | arg1: &CC, |
8372 | 0 | arg2: &TrapCode, |
8373 | 0 | ) -> ConsumesFlags { |
8374 | 0 | let v3 = MInst::TrapIfAnd { |
8375 | 0 | cc1: arg0.clone(), |
8376 | 0 | cc2: arg1.clone(), |
8377 | 0 | trap_code: arg2.clone(), |
8378 | 0 | }; |
8379 | 0 | let v4 = ConsumesFlags::ConsumesFlagsSideEffect { |
8380 | 0 | inst: v3, |
8381 | 0 | }; |
8382 | 0 | // Rule at src/isa/x64/inst.isle line 4226. |
8383 | 0 | return v4; |
8384 | 0 | } |
8385 | | |
8386 | | // Generated as internal constructor for term trap_if_or. |
8387 | 0 | pub fn constructor_trap_if_or<C: Context>( |
8388 | 0 | ctx: &mut C, |
8389 | 0 | arg0: &CC, |
8390 | 0 | arg1: &CC, |
8391 | 0 | arg2: &TrapCode, |
8392 | 0 | ) -> ConsumesFlags { |
8393 | 0 | let v3 = MInst::TrapIfOr { |
8394 | 0 | cc1: arg0.clone(), |
8395 | 0 | cc2: arg1.clone(), |
8396 | 0 | trap_code: arg2.clone(), |
8397 | 0 | }; |
8398 | 0 | let v4 = ConsumesFlags::ConsumesFlagsSideEffect { |
8399 | 0 | inst: v3, |
8400 | 0 | }; |
8401 | 0 | // Rule at src/isa/x64/inst.isle line 4231. |
8402 | 0 | return v4; |
8403 | 0 | } |
8404 | | |
8405 | | // Generated as internal constructor for term trap_if_icmp. |
8406 | 0 | pub fn constructor_trap_if_icmp<C: Context>( |
8407 | 0 | ctx: &mut C, |
8408 | 0 | arg0: &IcmpCondResult, |
8409 | 0 | arg1: &TrapCode, |
8410 | 0 | ) -> SideEffectNoResult { |
8411 | 0 | if let &IcmpCondResult::Condition { |
8412 | 0 | producer: ref v1, |
8413 | 0 | cc: ref v2, |
8414 | 0 | } = arg0 { |
8415 | 0 | let v4 = &constructor_trap_if(ctx, v2, arg1); |
8416 | 0 | let v5 = &constructor_with_flags_side_effect(ctx, v1, v4); |
8417 | 0 | // Rule at src/isa/x64/inst.isle line 4235. |
8418 | 0 | return v5.clone(); |
8419 | 0 | } |
8420 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "trap_if_icmp", "src/isa/x64/inst.isle line 4234") |
8421 | 0 | } |
8422 | | |
8423 | | // Generated as internal constructor for term trap_if_fcmp. |
8424 | 0 | pub fn constructor_trap_if_fcmp<C: Context>( |
8425 | 0 | ctx: &mut C, |
8426 | 0 | arg0: &FcmpCondResult, |
8427 | 0 | arg1: &TrapCode, |
8428 | 0 | ) -> SideEffectNoResult { |
8429 | 0 | match arg0 { |
8430 | | &FcmpCondResult::Condition { |
8431 | 0 | producer: ref v1, |
8432 | 0 | cc: ref v2, |
8433 | 0 | } => { |
8434 | 0 | let v4 = &constructor_trap_if(ctx, v2, arg1); |
8435 | 0 | let v5 = &constructor_with_flags_side_effect(ctx, v1, v4); |
8436 | 0 | // Rule at src/isa/x64/inst.isle line 4239. |
8437 | 0 | return v5.clone(); |
8438 | | } |
8439 | | &FcmpCondResult::AndCondition { |
8440 | 0 | producer: ref v6, |
8441 | 0 | cc1: ref v7, |
8442 | 0 | cc2: ref v8, |
8443 | 0 | } => { |
8444 | 0 | let v9 = &constructor_trap_if_and(ctx, v7, v8, arg1); |
8445 | 0 | let v10 = &constructor_with_flags_side_effect(ctx, v6, v9); |
8446 | 0 | // Rule at src/isa/x64/inst.isle line 4241. |
8447 | 0 | return v10.clone(); |
8448 | | } |
8449 | | &FcmpCondResult::OrCondition { |
8450 | 0 | producer: ref v11, |
8451 | 0 | cc1: ref v12, |
8452 | 0 | cc2: ref v13, |
8453 | 0 | } => { |
8454 | 0 | let v14 = &constructor_trap_if_or(ctx, v12, v13, arg1); |
8455 | 0 | let v15 = &constructor_with_flags_side_effect(ctx, v11, v14); |
8456 | 0 | // Rule at src/isa/x64/inst.isle line 4243. |
8457 | 0 | return v15.clone(); |
8458 | | } |
8459 | 0 | _ => {} |
8460 | 0 | } |
8461 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "trap_if_fcmp", "src/isa/x64/inst.isle line 4238") |
8462 | 0 | } |
8463 | | |
8464 | | // Generated as internal constructor for term x64_movddup. |
8465 | 0 | pub fn constructor_x64_movddup<C: Context>( |
8466 | 0 | ctx: &mut C, |
8467 | 0 | arg0: &XmmMem, |
8468 | 0 | ) -> Xmm { |
8469 | 0 | let v3 = C::use_avx_simd(ctx); |
8470 | 0 | if v3 == true { |
8471 | 0 | let v5 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vmovddup, arg0); |
8472 | 0 | // Rule at src/isa/x64/inst.isle line 4250. |
8473 | 0 | return v5; |
8474 | 0 | } |
8475 | 0 | let v2 = constructor_xmm_unary_rm_r_unaligned(ctx, &SseOpcode::Movddup, arg0); |
8476 | 0 | // Rule at src/isa/x64/inst.isle line 4248. |
8477 | 0 | return v2; |
8478 | 0 | } |
8479 | | |
8480 | | // Generated as internal constructor for term x64_vpbroadcastb. |
8481 | 0 | pub fn constructor_x64_vpbroadcastb<C: Context>( |
8482 | 0 | ctx: &mut C, |
8483 | 0 | arg0: &XmmMem, |
8484 | 0 | ) -> Xmm { |
8485 | 0 | let v2 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vpbroadcastb, arg0); |
8486 | 0 | // Rule at src/isa/x64/inst.isle line 4256. |
8487 | 0 | return v2; |
8488 | 0 | } |
8489 | | |
8490 | | // Generated as internal constructor for term x64_vpbroadcastw. |
8491 | 0 | pub fn constructor_x64_vpbroadcastw<C: Context>( |
8492 | 0 | ctx: &mut C, |
8493 | 0 | arg0: &XmmMem, |
8494 | 0 | ) -> Xmm { |
8495 | 0 | let v2 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vpbroadcastw, arg0); |
8496 | 0 | // Rule at src/isa/x64/inst.isle line 4261. |
8497 | 0 | return v2; |
8498 | 0 | } |
8499 | | |
8500 | | // Generated as internal constructor for term x64_vpbroadcastd. |
8501 | 0 | pub fn constructor_x64_vpbroadcastd<C: Context>( |
8502 | 0 | ctx: &mut C, |
8503 | 0 | arg0: &XmmMem, |
8504 | 0 | ) -> Xmm { |
8505 | 0 | let v2 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vpbroadcastd, arg0); |
8506 | 0 | // Rule at src/isa/x64/inst.isle line 4266. |
8507 | 0 | return v2; |
8508 | 0 | } |
8509 | | |
8510 | | // Generated as internal constructor for term x64_vbroadcastss. |
8511 | 0 | pub fn constructor_x64_vbroadcastss<C: Context>( |
8512 | 0 | ctx: &mut C, |
8513 | 0 | arg0: &XmmMem, |
8514 | 0 | ) -> Xmm { |
8515 | 0 | let v2 = constructor_xmm_unary_rm_r_vex(ctx, &AvxOpcode::Vbroadcastss, arg0); |
8516 | 0 | // Rule at src/isa/x64/inst.isle line 4271. |
8517 | 0 | return v2; |
8518 | 0 | } |
8519 | | |
8520 | | // Generated as internal constructor for term jmp_known. |
8521 | 155k | pub fn constructor_jmp_known<C: Context>( |
8522 | 155k | ctx: &mut C, |
8523 | 155k | arg0: MachLabel, |
8524 | 155k | ) -> SideEffectNoResult { |
8525 | 155k | let v1 = MInst::JmpKnown { |
8526 | 155k | dst: arg0, |
8527 | 155k | }; |
8528 | 155k | let v2 = SideEffectNoResult::Inst { |
8529 | 155k | inst: v1, |
8530 | 155k | }; |
8531 | 155k | // Rule at src/isa/x64/inst.isle line 4278. |
8532 | 155k | return v2; |
8533 | 155k | } |
8534 | | |
8535 | | // Generated as internal constructor for term jmp_if. |
8536 | 0 | pub fn constructor_jmp_if<C: Context>( |
8537 | 0 | ctx: &mut C, |
8538 | 0 | arg0: &CC, |
8539 | 0 | arg1: MachLabel, |
8540 | 0 | ) -> ConsumesFlags { |
8541 | 0 | let v2 = MInst::JmpIf { |
8542 | 0 | cc: arg0.clone(), |
8543 | 0 | taken: arg1, |
8544 | 0 | }; |
8545 | 0 | let v3 = ConsumesFlags::ConsumesFlagsSideEffect { |
8546 | 0 | inst: v2, |
8547 | 0 | }; |
8548 | 0 | // Rule at src/isa/x64/inst.isle line 4282. |
8549 | 0 | return v3; |
8550 | 0 | } |
8551 | | |
8552 | | // Generated as internal constructor for term jmp_cond. |
8553 | 233k | pub fn constructor_jmp_cond<C: Context>( |
8554 | 233k | ctx: &mut C, |
8555 | 233k | arg0: &CC, |
8556 | 233k | arg1: MachLabel, |
8557 | 233k | arg2: MachLabel, |
8558 | 233k | ) -> ConsumesFlags { |
8559 | 233k | let v3 = MInst::JmpCond { |
8560 | 233k | cc: arg0.clone(), |
8561 | 233k | taken: arg1, |
8562 | 233k | not_taken: arg2, |
8563 | 233k | }; |
8564 | 233k | let v4 = ConsumesFlags::ConsumesFlagsSideEffect { |
8565 | 233k | inst: v3, |
8566 | 233k | }; |
8567 | 233k | // Rule at src/isa/x64/inst.isle line 4287. |
8568 | 233k | return v4; |
8569 | 233k | } |
8570 | | |
8571 | | // Generated as internal constructor for term jmp_cond_icmp. |
8572 | 163k | pub fn constructor_jmp_cond_icmp<C: Context>( |
8573 | 163k | ctx: &mut C, |
8574 | 163k | arg0: &IcmpCondResult, |
8575 | 163k | arg1: MachLabel, |
8576 | 163k | arg2: MachLabel, |
8577 | 163k | ) -> SideEffectNoResult { |
8578 | 163k | if let &IcmpCondResult::Condition { |
8579 | 163k | producer: ref v1, |
8580 | 163k | cc: ref v2, |
8581 | 163k | } = arg0 { |
8582 | 163k | let v5 = &constructor_jmp_cond(ctx, v2, arg1, arg2); |
8583 | 163k | let v6 = &constructor_with_flags_side_effect(ctx, v1, v5); |
8584 | 163k | // Rule at src/isa/x64/inst.isle line 4292. |
8585 | 163k | return v6.clone(); |
8586 | 163k | } |
8587 | 163k | unreachable!("no rule matched for term {} at {}; should it be partial?", "jmp_cond_icmp", "src/isa/x64/inst.isle line 4291") |
8588 | 163k | } |
8589 | | |
8590 | | // Generated as internal constructor for term jmp_cond_fcmp. |
8591 | 0 | pub fn constructor_jmp_cond_fcmp<C: Context>( |
8592 | 0 | ctx: &mut C, |
8593 | 0 | arg0: &FcmpCondResult, |
8594 | 0 | arg1: MachLabel, |
8595 | 0 | arg2: MachLabel, |
8596 | 0 | ) -> SideEffectNoResult { |
8597 | 0 | match arg0 { |
8598 | | &FcmpCondResult::Condition { |
8599 | 0 | producer: ref v1, |
8600 | 0 | cc: ref v2, |
8601 | 0 | } => { |
8602 | 0 | let v5 = &constructor_jmp_cond(ctx, v2, arg1, arg2); |
8603 | 0 | let v6 = &constructor_with_flags_side_effect(ctx, v1, v5); |
8604 | 0 | // Rule at src/isa/x64/inst.isle line 4297. |
8605 | 0 | return v6.clone(); |
8606 | | } |
8607 | | &FcmpCondResult::AndCondition { |
8608 | 0 | producer: ref v7, |
8609 | 0 | cc1: ref v8, |
8610 | 0 | cc2: ref v9, |
8611 | 0 | } => { |
8612 | 0 | let v10 = &C::cc_invert(ctx, v8); |
8613 | 0 | let v11 = &constructor_jmp_if(ctx, v10, arg2); |
8614 | 0 | let v12 = &C::cc_invert(ctx, v9); |
8615 | 0 | let v13 = &constructor_jmp_cond(ctx, v12, arg2, arg1); |
8616 | 0 | let v14 = &constructor_consumes_flags_concat(ctx, v11, v13); |
8617 | 0 | let v15 = &constructor_with_flags_side_effect(ctx, v7, v14); |
8618 | 0 | // Rule at src/isa/x64/inst.isle line 4299. |
8619 | 0 | return v15.clone(); |
8620 | | } |
8621 | | &FcmpCondResult::OrCondition { |
8622 | 0 | producer: ref v16, |
8623 | 0 | cc1: ref v17, |
8624 | 0 | cc2: ref v18, |
8625 | 0 | } => { |
8626 | 0 | let v19 = &constructor_jmp_if(ctx, v17, arg1); |
8627 | 0 | let v20 = &constructor_jmp_cond(ctx, v18, arg1, arg2); |
8628 | 0 | let v21 = &constructor_consumes_flags_concat(ctx, v19, v20); |
8629 | 0 | let v22 = &constructor_with_flags_side_effect(ctx, v16, v21); |
8630 | 0 | // Rule at src/isa/x64/inst.isle line 4304. |
8631 | 0 | return v22.clone(); |
8632 | | } |
8633 | 0 | _ => {} |
8634 | 0 | } |
8635 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "jmp_cond_fcmp", "src/isa/x64/inst.isle line 4296") |
8636 | 0 | } |
8637 | | |
8638 | | // Generated as internal constructor for term jmp_table_seq. |
8639 | 7.52k | pub fn constructor_jmp_table_seq<C: Context>( |
8640 | 7.52k | ctx: &mut C, |
8641 | 7.52k | arg0: Type, |
8642 | 7.52k | arg1: Gpr, |
8643 | 7.52k | arg2: MachLabel, |
8644 | 7.52k | arg3: &BoxVecMachLabel, |
8645 | 7.52k | ) -> SideEffectNoResult { |
8646 | 7.52k | let v4 = C::temp_writable_gpr(ctx); |
8647 | 7.52k | let v5 = C::temp_writable_gpr(ctx); |
8648 | 7.52k | let v6 = C::gpr_to_reg(ctx, arg1); |
8649 | 7.52k | let v7 = C::writable_gpr_to_reg(ctx, v4); |
8650 | 7.52k | let v8 = C::writable_gpr_to_reg(ctx, v5); |
8651 | 7.52k | let v9 = MInst::JmpTableSeq { |
8652 | 7.52k | idx: v6, |
8653 | 7.52k | tmp1: v7, |
8654 | 7.52k | tmp2: v8, |
8655 | 7.52k | default_target: arg2, |
8656 | 7.52k | targets: arg3.clone(), |
8657 | 7.52k | }; |
8658 | 7.52k | let v10 = SideEffectNoResult::Inst { |
8659 | 7.52k | inst: v9, |
8660 | 7.52k | }; |
8661 | 7.52k | // Rule at src/isa/x64/inst.isle line 4324. |
8662 | 7.52k | return v10; |
8663 | 7.52k | } |
8664 | | |
8665 | | // Generated as internal constructor for term icmp_cond_result. |
8666 | 196k | pub fn constructor_icmp_cond_result<C: Context>( |
8667 | 196k | ctx: &mut C, |
8668 | 196k | arg0: &ProducesFlags, |
8669 | 196k | arg1: &CC, |
8670 | 196k | ) -> IcmpCondResult { |
8671 | 196k | let v2 = IcmpCondResult::Condition { |
8672 | 196k | producer: arg0.clone(), |
8673 | 196k | cc: arg1.clone(), |
8674 | 196k | }; |
8675 | 196k | // Rule at src/isa/x64/inst.isle line 4362. |
8676 | 196k | return v2; |
8677 | 196k | } |
8678 | | |
8679 | | // Generated as internal constructor for term invert_icmp_cond_result. |
8680 | 0 | pub fn constructor_invert_icmp_cond_result<C: Context>( |
8681 | 0 | ctx: &mut C, |
8682 | 0 | arg0: &IcmpCondResult, |
8683 | 0 | ) -> IcmpCondResult { |
8684 | 0 | if let &IcmpCondResult::Condition { |
8685 | 0 | producer: ref v1, |
8686 | 0 | cc: ref v2, |
8687 | 0 | } = arg0 { |
8688 | 0 | let v3 = &C::cc_invert(ctx, v2); |
8689 | 0 | let v4 = &constructor_icmp_cond_result(ctx, v1, v3); |
8690 | 0 | // Rule at src/isa/x64/inst.isle line 4365. |
8691 | 0 | return v4.clone(); |
8692 | 0 | } |
8693 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "invert_icmp_cond_result", "src/isa/x64/inst.isle line 4364") |
8694 | 0 | } |
8695 | | |
8696 | | // Generated as internal constructor for term lower_icmp_bool. |
8697 | 8.49k | pub fn constructor_lower_icmp_bool<C: Context>( |
8698 | 8.49k | ctx: &mut C, |
8699 | 8.49k | arg0: &IcmpCondResult, |
8700 | 8.49k | ) -> ValueRegs { |
8701 | 8.49k | if let &IcmpCondResult::Condition { |
8702 | 8.49k | producer: ref v1, |
8703 | 8.49k | cc: ref v2, |
8704 | 8.49k | } = arg0 { |
8705 | 8.49k | let v3 = &constructor_x64_setcc(ctx, v2); |
8706 | 8.49k | let v4 = constructor_with_flags(ctx, v1, v3); |
8707 | 8.49k | // Rule at src/isa/x64/inst.isle line 4370. |
8708 | 8.49k | return v4; |
8709 | 8.49k | } |
8710 | 8.49k | unreachable!("no rule matched for term {} at {}; should it be partial?", "lower_icmp_bool", "src/isa/x64/inst.isle line 4369") |
8711 | 8.49k | } |
8712 | | |
8713 | | // Generated as internal constructor for term select_icmp. |
8714 | 24.7k | pub fn constructor_select_icmp<C: Context>( |
8715 | 24.7k | ctx: &mut C, |
8716 | 24.7k | arg0: &IcmpCondResult, |
8717 | 24.7k | arg1: Value, |
8718 | 24.7k | arg2: Value, |
8719 | 24.7k | ) -> ValueRegs { |
8720 | 24.7k | if let &IcmpCondResult::Condition { |
8721 | 24.7k | producer: ref v1, |
8722 | 24.7k | cc: ref v2, |
8723 | 24.7k | } = arg0 { |
8724 | 24.7k | let v4 = C::value_type(ctx, arg1); |
8725 | 24.7k | let v5 = &C::type_register_class(ctx, v4); |
8726 | 24.7k | if let Some(v6) = v5 { |
8727 | | if let &RegisterClass::Gpr { |
8728 | 24.7k | single_register: v7, |
8729 | 24.7k | } = v6 { |
8730 | 24.7k | if v7 == true { |
8731 | 24.7k | let v9 = constructor_put_in_gpr(ctx, arg1); |
8732 | 24.7k | let v10 = &C::gpr_to_gpr_mem(ctx, v9); |
8733 | 24.7k | let v11 = constructor_put_in_gpr(ctx, arg2); |
8734 | 24.7k | let v12 = &constructor_cmove(ctx, v4, v2, v10, v11); |
8735 | 24.7k | let v13 = constructor_with_flags(ctx, v1, v12); |
8736 | 24.7k | // Rule at src/isa/x64/inst.isle line 4379. |
8737 | 24.7k | return v13; |
8738 | 0 | } |
8739 | 0 | } |
8740 | 0 | } |
8741 | 0 | let v14 = &constructor_cmove_from_values(ctx, v4, v2, arg1, arg2); |
8742 | 0 | let v15 = constructor_with_flags(ctx, v1, v14); |
8743 | 0 | // Rule at src/isa/x64/inst.isle line 4383. |
8744 | 0 | return v15; |
8745 | | } |
8746 | | unreachable!("no rule matched for term {} at {}; should it be partial?", "select_icmp", "src/isa/x64/inst.isle line 4374") |
8747 | 24.7k | } |
8748 | | |
8749 | | // Generated as internal constructor for term emit_cmp. |
8750 | 196k | pub fn constructor_emit_cmp<C: Context>( |
8751 | 196k | ctx: &mut C, |
8752 | 196k | arg0: &IntCC, |
8753 | 196k | arg1: Value, |
8754 | 196k | arg2: Value, |
8755 | 196k | ) -> IcmpCondResult { |
8756 | 196k | let v2 = C::value_type(ctx, arg1); |
8757 | 196k | if v2 == I128 { |
8758 | 0 | match arg0 { |
8759 | | &IntCC::Equal => { |
8760 | 0 | let v44 = C::put_in_regs(ctx, arg1); |
8761 | 0 | let v46 = constructor_value_regs_get_gpr(ctx, v44, 0x0); |
8762 | 0 | let v47 = C::put_in_regs(ctx, arg1); |
8763 | 0 | let v49 = constructor_value_regs_get_gpr(ctx, v47, 0x1); |
8764 | 0 | let v50 = C::put_in_regs(ctx, arg2); |
8765 | 0 | let v51 = constructor_value_regs_get_gpr(ctx, v50, 0x0); |
8766 | 0 | let v52 = C::put_in_regs(ctx, arg2); |
8767 | 0 | let v53 = constructor_value_regs_get_gpr(ctx, v52, 0x1); |
8768 | 0 | let v55 = &C::gpr_to_gpr_mem_imm(ctx, v51); |
8769 | 0 | let v56 = &constructor_x64_cmp(ctx, &OperandSize::Size64, v55, v46); |
8770 | 0 | let v58 = &constructor_x64_setcc(ctx, &CC::Z); |
8771 | 0 | let v59 = constructor_with_flags_reg(ctx, v56, v58); |
8772 | 0 | let v60 = &C::gpr_to_gpr_mem_imm(ctx, v53); |
8773 | 0 | let v61 = &constructor_x64_cmp(ctx, &OperandSize::Size64, v60, v49); |
8774 | 0 | let v62 = &constructor_x64_setcc(ctx, &CC::Z); |
8775 | 0 | let v63 = constructor_with_flags_reg(ctx, v61, v62); |
8776 | 0 | let v65 = C::gpr_new(ctx, v59); |
8777 | 0 | let v66 = &constructor_reg_to_gpr_mem_imm(ctx, v63); |
8778 | 0 | let v67 = constructor_x64_and(ctx, I64, v65, v66); |
8779 | 0 | let v68 = C::gpr_to_reg(ctx, v67); |
8780 | 0 | let v70 = RegMemImm::Imm { |
8781 | 0 | simm32: 0x1, |
8782 | 0 | }; |
8783 | 0 | let v71 = &C::gpr_mem_imm_new(ctx, &v70); |
8784 | 0 | let v72 = C::gpr_new(ctx, v68); |
8785 | 0 | let v73 = &constructor_x64_test(ctx, &OperandSize::Size64, v71, v72); |
8786 | 0 | let v75 = &constructor_icmp_cond_result(ctx, v73, &CC::NZ); |
8787 | 0 | // Rule at src/isa/x64/inst.isle line 4415. |
8788 | 0 | return v75.clone(); |
8789 | | } |
8790 | | &IntCC::NotEqual => { |
8791 | 0 | let v44 = C::put_in_regs(ctx, arg1); |
8792 | 0 | let v46 = constructor_value_regs_get_gpr(ctx, v44, 0x0); |
8793 | 0 | let v47 = C::put_in_regs(ctx, arg1); |
8794 | 0 | let v49 = constructor_value_regs_get_gpr(ctx, v47, 0x1); |
8795 | 0 | let v50 = C::put_in_regs(ctx, arg2); |
8796 | 0 | let v51 = constructor_value_regs_get_gpr(ctx, v50, 0x0); |
8797 | 0 | let v52 = C::put_in_regs(ctx, arg2); |
8798 | 0 | let v53 = constructor_value_regs_get_gpr(ctx, v52, 0x1); |
8799 | 0 | let v55 = &C::gpr_to_gpr_mem_imm(ctx, v51); |
8800 | 0 | let v56 = &constructor_x64_cmp(ctx, &OperandSize::Size64, v55, v46); |
8801 | 0 | let v76 = &constructor_x64_setcc(ctx, &CC::NZ); |
8802 | 0 | let v77 = constructor_with_flags_reg(ctx, v56, v76); |
8803 | 0 | let v60 = &C::gpr_to_gpr_mem_imm(ctx, v53); |
8804 | 0 | let v61 = &constructor_x64_cmp(ctx, &OperandSize::Size64, v60, v49); |
8805 | 0 | let v78 = &constructor_x64_setcc(ctx, &CC::NZ); |
8806 | 0 | let v79 = constructor_with_flags_reg(ctx, v61, v78); |
8807 | 0 | let v80 = C::gpr_new(ctx, v77); |
8808 | 0 | let v81 = &constructor_reg_to_gpr_mem_imm(ctx, v79); |
8809 | 0 | let v82 = constructor_x64_or(ctx, I64, v80, v81); |
8810 | 0 | let v83 = C::gpr_to_reg(ctx, v82); |
8811 | 0 | let v70 = RegMemImm::Imm { |
8812 | 0 | simm32: 0x1, |
8813 | 0 | }; |
8814 | 0 | let v71 = &C::gpr_mem_imm_new(ctx, &v70); |
8815 | 0 | let v84 = C::gpr_new(ctx, v83); |
8816 | 0 | let v85 = &constructor_x64_test(ctx, &OperandSize::Size64, v71, v84); |
8817 | 0 | let v86 = &constructor_icmp_cond_result(ctx, v85, &CC::NZ); |
8818 | 0 | // Rule at src/isa/x64/inst.isle line 4436. |
8819 | 0 | return v86.clone(); |
8820 | | } |
8821 | 0 | _ => {} |
8822 | 0 | } |
8823 | 0 | let v44 = C::put_in_regs(ctx, arg1); |
8824 | 0 | let v46 = constructor_value_regs_get_gpr(ctx, v44, 0x0); |
8825 | 0 | let v47 = C::put_in_regs(ctx, arg1); |
8826 | 0 | let v49 = constructor_value_regs_get_gpr(ctx, v47, 0x1); |
8827 | 0 | let v50 = C::put_in_regs(ctx, arg2); |
8828 | 0 | let v51 = constructor_value_regs_get_gpr(ctx, v50, 0x0); |
8829 | 0 | let v52 = C::put_in_regs(ctx, arg2); |
8830 | 0 | let v53 = constructor_value_regs_get_gpr(ctx, v52, 0x1); |
8831 | 0 | let v87 = &C::gpr_to_gpr_mem_imm(ctx, v53); |
8832 | 0 | let v88 = &constructor_x64_cmp(ctx, &OperandSize::Size64, v87, v49); |
8833 | 0 | let v89 = &C::intcc_without_eq(ctx, arg0); |
8834 | 0 | let v90 = &C::intcc_to_cc(ctx, v89); |
8835 | 0 | let v91 = &constructor_x64_setcc(ctx, v90); |
8836 | 0 | let v92 = &constructor_x64_setcc(ctx, &CC::Z); |
8837 | 0 | let v93 = &constructor_consumes_flags_concat(ctx, v91, v92); |
8838 | 0 | let v94 = constructor_with_flags(ctx, v88, v93); |
8839 | 0 | let v95 = C::value_regs_get(ctx, v94, 0x0); |
8840 | 0 | let v96 = C::value_regs_get(ctx, v94, 0x1); |
8841 | 0 | let v97 = &C::gpr_to_gpr_mem_imm(ctx, v51); |
8842 | 0 | let v98 = &constructor_x64_cmp(ctx, &OperandSize::Size64, v97, v46); |
8843 | 0 | let v99 = &C::intcc_unsigned(ctx, arg0); |
8844 | 0 | let v100 = &C::intcc_to_cc(ctx, v99); |
8845 | 0 | let v101 = &constructor_x64_setcc(ctx, v100); |
8846 | 0 | let v102 = constructor_with_flags_reg(ctx, v98, v101); |
8847 | 0 | let v103 = C::gpr_new(ctx, v96); |
8848 | 0 | let v104 = &constructor_reg_to_gpr_mem_imm(ctx, v102); |
8849 | 0 | let v105 = constructor_x64_and(ctx, I64, v103, v104); |
8850 | 0 | let v106 = C::gpr_to_reg(ctx, v105); |
8851 | 0 | let v107 = C::gpr_new(ctx, v95); |
8852 | 0 | let v108 = &constructor_reg_to_gpr_mem_imm(ctx, v106); |
8853 | 0 | let v109 = constructor_x64_or(ctx, I64, v107, v108); |
8854 | 0 | let v110 = C::gpr_to_reg(ctx, v109); |
8855 | 0 | let v70 = RegMemImm::Imm { |
8856 | 0 | simm32: 0x1, |
8857 | 0 | }; |
8858 | 0 | let v111 = &C::gpr_mem_imm_new(ctx, &v70); |
8859 | 0 | let v112 = C::gpr_new(ctx, v110); |
8860 | 0 | let v113 = &constructor_x64_test(ctx, &OperandSize::Size64, v111, v112); |
8861 | 0 | let v114 = &constructor_icmp_cond_result(ctx, v113, &CC::NZ); |
8862 | 0 | // Rule at src/isa/x64/inst.isle line 4451. |
8863 | 0 | return v114.clone(); |
8864 | 196k | } |
8865 | 196k | let v29 = C::def_inst(ctx, arg1); |
8866 | 196k | if let Some(v30188k ) = v29 { |
8867 | 188k | let v31 = &C::inst_data(ctx, v30); |
8868 | | if let &InstructionData::UnaryImm { |
8869 | 2 | opcode: ref v32, |
8870 | 2 | imm: v33, |
8871 | 188k | } = v31 { |
8872 | 2 | if let &Opcode::Iconst = v32 { |
8873 | 2 | let v34 = C::u64_from_imm64(ctx, v33); |
8874 | 2 | if v34 == 0x0 { |
8875 | 0 | let v35 = C::value_type(ctx, arg2); |
8876 | 0 | let v36 = &C::raw_operand_size_of_type(ctx, v35); |
8877 | 0 | let v37 = C::put_in_reg(ctx, arg2); |
8878 | 0 | let v38 = C::gpr_new(ctx, v37); |
8879 | 0 | let v39 = &C::gpr_to_gpr_mem_imm(ctx, v38); |
8880 | 0 | let v40 = &constructor_x64_test(ctx, v36, v39, v38); |
8881 | 0 | let v41 = &C::intcc_reverse(ctx, arg0); |
8882 | 0 | let v42 = &C::intcc_to_cc(ctx, v41); |
8883 | 0 | let v43 = &constructor_icmp_cond_result(ctx, v40, v42); |
8884 | 0 | // Rule at src/isa/x64/inst.isle line 4408. |
8885 | 0 | return v43.clone(); |
8886 | 0 | } |
8887 | 0 | } |
8888 | 188k | } |
8889 | 8.19k | } |
8890 | 196k | let v17 = C::def_inst(ctx, arg2); |
8891 | 196k | if let Some(v18192k ) = v17 { |
8892 | 192k | let v19 = &C::inst_data(ctx, v18); |
8893 | | if let &InstructionData::UnaryImm { |
8894 | 95.3k | opcode: ref v20, |
8895 | 95.3k | imm: v21, |
8896 | 192k | } = v19 { |
8897 | 95.3k | if let &Opcode::Iconst = v20 { |
8898 | 95.3k | let v22 = C::u64_from_imm64(ctx, v21); |
8899 | 95.3k | if v22 == 0x0 { |
8900 | 55.9k | let v4 = &C::raw_operand_size_of_type(ctx, v2); |
8901 | 55.9k | let v23 = C::put_in_reg(ctx, arg1); |
8902 | 55.9k | let v24 = C::gpr_new(ctx, v23); |
8903 | 55.9k | let v25 = &C::gpr_to_gpr_mem_imm(ctx, v24); |
8904 | 55.9k | let v26 = &constructor_x64_test(ctx, v4, v25, v24); |
8905 | 55.9k | let v27 = &C::intcc_to_cc(ctx, arg0); |
8906 | 55.9k | let v28 = &constructor_icmp_cond_result(ctx, v26, v27); |
8907 | 55.9k | // Rule at src/isa/x64/inst.isle line 4403. |
8908 | 55.9k | return v28.clone(); |
8909 | 39.4k | } |
8910 | 0 | } |
8911 | 97.2k | } |
8912 | 3.92k | } |
8913 | 140k | let v10 = &C::simm32_from_value(ctx, arg1); |
8914 | 140k | if let Some(v110 ) = v10 { |
8915 | 0 | let v4 = &C::raw_operand_size_of_type(ctx, v2); |
8916 | 0 | let v12 = constructor_put_in_gpr(ctx, arg2); |
8917 | 0 | let v13 = &constructor_x64_cmp(ctx, v4, v11, v12); |
8918 | 0 | let v14 = &C::intcc_reverse(ctx, arg0); |
8919 | 0 | let v15 = &C::intcc_to_cc(ctx, v14); |
8920 | 0 | let v16 = &constructor_icmp_cond_result(ctx, v13, v15); |
8921 | 0 | // Rule at src/isa/x64/inst.isle line 4398. |
8922 | 0 | return v16.clone(); |
8923 | 140k | } |
8924 | 140k | let v4 = &C::raw_operand_size_of_type(ctx, v2); |
8925 | 140k | let v5 = &constructor_put_in_gpr_mem_imm(ctx, arg2); |
8926 | 140k | let v6 = constructor_put_in_gpr(ctx, arg1); |
8927 | 140k | let v7 = &constructor_x64_cmp(ctx, v4, v5, v6); |
8928 | 140k | let v8 = &C::intcc_to_cc(ctx, arg0); |
8929 | 140k | let v9 = &constructor_icmp_cond_result(ctx, v7, v8); |
8930 | 140k | // Rule at src/isa/x64/inst.isle line 4391. |
8931 | 140k | return v9.clone(); |
8932 | 196k | } |
8933 | | |
8934 | | // Generated as internal constructor for term lower_fcmp_bool. |
8935 | 0 | pub fn constructor_lower_fcmp_bool<C: Context>( |
8936 | 0 | ctx: &mut C, |
8937 | 0 | arg0: &FcmpCondResult, |
8938 | 0 | ) -> ValueRegs { |
8939 | 0 | match arg0 { |
8940 | | &FcmpCondResult::Condition { |
8941 | 0 | producer: ref v1, |
8942 | 0 | cc: ref v2, |
8943 | 0 | } => { |
8944 | 0 | let v3 = &constructor_x64_setcc(ctx, v2); |
8945 | 0 | let v4 = constructor_with_flags(ctx, v1, v3); |
8946 | 0 | // Rule at src/isa/x64/inst.isle line 4486. |
8947 | 0 | return v4; |
8948 | | } |
8949 | | &FcmpCondResult::AndCondition { |
8950 | 0 | producer: ref v5, |
8951 | 0 | cc1: ref v6, |
8952 | 0 | cc2: ref v7, |
8953 | 0 | } => { |
8954 | 0 | let v8 = &constructor_x64_setcc(ctx, v6); |
8955 | 0 | let v9 = &constructor_x64_setcc(ctx, v7); |
8956 | 0 | let v10 = &constructor_consumes_flags_concat(ctx, v8, v9); |
8957 | 0 | let v11 = constructor_with_flags(ctx, v5, v10); |
8958 | 0 | let v13 = constructor_value_regs_get_gpr(ctx, v11, 0x0); |
8959 | 0 | let v15 = constructor_value_regs_get_gpr(ctx, v11, 0x1); |
8960 | 0 | let v17 = &C::gpr_to_gpr_mem_imm(ctx, v15); |
8961 | 0 | let v18 = constructor_x64_and(ctx, I8, v13, v17); |
8962 | 0 | let v19 = C::gpr_to_reg(ctx, v18); |
8963 | 0 | let v20 = C::value_reg(ctx, v19); |
8964 | 0 | // Rule at src/isa/x64/inst.isle line 4489. |
8965 | 0 | return v20; |
8966 | | } |
8967 | | &FcmpCondResult::OrCondition { |
8968 | 0 | producer: ref v21, |
8969 | 0 | cc1: ref v22, |
8970 | 0 | cc2: ref v23, |
8971 | 0 | } => { |
8972 | 0 | let v24 = &constructor_x64_setcc(ctx, v22); |
8973 | 0 | let v25 = &constructor_x64_setcc(ctx, v23); |
8974 | 0 | let v26 = &constructor_consumes_flags_concat(ctx, v24, v25); |
8975 | 0 | let v27 = constructor_with_flags(ctx, v21, v26); |
8976 | 0 | let v28 = constructor_value_regs_get_gpr(ctx, v27, 0x0); |
8977 | 0 | let v29 = constructor_value_regs_get_gpr(ctx, v27, 0x1); |
8978 | 0 | let v30 = &C::gpr_to_gpr_mem_imm(ctx, v29); |
8979 | 0 | let v31 = constructor_x64_or(ctx, I8, v28, v30); |
8980 | 0 | let v32 = C::gpr_to_reg(ctx, v31); |
8981 | 0 | let v33 = C::value_reg(ctx, v32); |
8982 | 0 | // Rule at src/isa/x64/inst.isle line 4498. |
8983 | 0 | return v33; |
8984 | | } |
8985 | 0 | _ => {} |
8986 | 0 | } |
8987 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "lower_fcmp_bool", "src/isa/x64/inst.isle line 4484") |
8988 | 0 | } |
8989 | | |
8990 | | // Generated as internal constructor for term emit_fcmp. |
8991 | 0 | pub fn constructor_emit_fcmp<C: Context>( |
8992 | 0 | ctx: &mut C, |
8993 | 0 | arg0: &FloatCC, |
8994 | 0 | arg1: Value, |
8995 | 0 | arg2: Value, |
8996 | 0 | ) -> FcmpCondResult { |
8997 | 0 | match arg0 { |
8998 | | &FloatCC::Equal => { |
8999 | 0 | let v2 = C::value_type(ctx, arg1); |
9000 | 0 | let v3 = C::ty_scalar_float(ctx, v2); |
9001 | 0 | if let Some(v4) = v3 { |
9002 | 0 | let v6 = &constructor_x64_ucomis(ctx, arg2, arg1); |
9003 | 0 | let v9 = FcmpCondResult::AndCondition { |
9004 | 0 | producer: v6.clone(), |
9005 | 0 | cc1: CC::NP, |
9006 | 0 | cc2: CC::Z, |
9007 | 0 | }; |
9008 | 0 | // Rule at src/isa/x64/inst.isle line 4525. |
9009 | 0 | return v9; |
9010 | 0 | } |
9011 | | } |
9012 | | &FloatCC::GreaterThan => { |
9013 | 0 | let v2 = C::value_type(ctx, arg1); |
9014 | 0 | let v3 = C::ty_scalar_float(ctx, v2); |
9015 | 0 | if let Some(v4) = v3 { |
9016 | 0 | let v6 = &constructor_x64_ucomis(ctx, arg2, arg1); |
9017 | 0 | let v18 = FcmpCondResult::Condition { |
9018 | 0 | producer: v6.clone(), |
9019 | 0 | cc: CC::NBE, |
9020 | 0 | }; |
9021 | 0 | // Rule at src/isa/x64/inst.isle line 4541. |
9022 | 0 | return v18; |
9023 | 0 | } |
9024 | | } |
9025 | | &FloatCC::GreaterThanOrEqual => { |
9026 | 0 | let v2 = C::value_type(ctx, arg1); |
9027 | 0 | let v3 = C::ty_scalar_float(ctx, v2); |
9028 | 0 | if let Some(v4) = v3 { |
9029 | 0 | let v6 = &constructor_x64_ucomis(ctx, arg2, arg1); |
9030 | 0 | let v20 = FcmpCondResult::Condition { |
9031 | 0 | producer: v6.clone(), |
9032 | 0 | cc: CC::NB, |
9033 | 0 | }; |
9034 | 0 | // Rule at src/isa/x64/inst.isle line 4543. |
9035 | 0 | return v20; |
9036 | 0 | } |
9037 | | } |
9038 | | &FloatCC::LessThan => { |
9039 | 0 | let v2 = C::value_type(ctx, arg1); |
9040 | 0 | let v3 = C::ty_scalar_float(ctx, v2); |
9041 | 0 | if let Some(v4) = v3 { |
9042 | 0 | let v25 = &constructor_x64_ucomis(ctx, arg1, arg2); |
9043 | 0 | let v26 = FcmpCondResult::Condition { |
9044 | 0 | producer: v25.clone(), |
9045 | 0 | cc: CC::NBE, |
9046 | 0 | }; |
9047 | 0 | // Rule at src/isa/x64/inst.isle line 4553. |
9048 | 0 | return v26; |
9049 | 0 | } |
9050 | | } |
9051 | | &FloatCC::LessThanOrEqual => { |
9052 | 0 | let v2 = C::value_type(ctx, arg1); |
9053 | 0 | let v3 = C::ty_scalar_float(ctx, v2); |
9054 | 0 | if let Some(v4) = v3 { |
9055 | 0 | let v25 = &constructor_x64_ucomis(ctx, arg1, arg2); |
9056 | 0 | let v27 = FcmpCondResult::Condition { |
9057 | 0 | producer: v25.clone(), |
9058 | 0 | cc: CC::NB, |
9059 | 0 | }; |
9060 | 0 | // Rule at src/isa/x64/inst.isle line 4556. |
9061 | 0 | return v27; |
9062 | 0 | } |
9063 | | } |
9064 | | &FloatCC::NotEqual => { |
9065 | 0 | let v2 = C::value_type(ctx, arg1); |
9066 | 0 | let v3 = C::ty_scalar_float(ctx, v2); |
9067 | 0 | if let Some(v4) = v3 { |
9068 | 0 | let v6 = &constructor_x64_ucomis(ctx, arg2, arg1); |
9069 | 0 | let v12 = FcmpCondResult::OrCondition { |
9070 | 0 | producer: v6.clone(), |
9071 | 0 | cc1: CC::P, |
9072 | 0 | cc2: CC::NZ, |
9073 | 0 | }; |
9074 | 0 | // Rule at src/isa/x64/inst.isle line 4528. |
9075 | 0 | return v12; |
9076 | 0 | } |
9077 | | } |
9078 | | &FloatCC::Ordered => { |
9079 | 0 | let v2 = C::value_type(ctx, arg1); |
9080 | 0 | let v3 = C::ty_scalar_float(ctx, v2); |
9081 | 0 | if let Some(v4) = v3 { |
9082 | 0 | let v6 = &constructor_x64_ucomis(ctx, arg2, arg1); |
9083 | 0 | let v13 = FcmpCondResult::Condition { |
9084 | 0 | producer: v6.clone(), |
9085 | 0 | cc: CC::NP, |
9086 | 0 | }; |
9087 | 0 | // Rule at src/isa/x64/inst.isle line 4533. |
9088 | 0 | return v13; |
9089 | 0 | } |
9090 | | } |
9091 | | &FloatCC::OrderedNotEqual => { |
9092 | 0 | let v2 = C::value_type(ctx, arg1); |
9093 | 0 | let v3 = C::ty_scalar_float(ctx, v2); |
9094 | 0 | if let Some(v4) = v3 { |
9095 | 0 | let v6 = &constructor_x64_ucomis(ctx, arg2, arg1); |
9096 | 0 | let v15 = FcmpCondResult::Condition { |
9097 | 0 | producer: v6.clone(), |
9098 | 0 | cc: CC::NZ, |
9099 | 0 | }; |
9100 | 0 | // Rule at src/isa/x64/inst.isle line 4537. |
9101 | 0 | return v15; |
9102 | 0 | } |
9103 | | } |
9104 | | &FloatCC::Unordered => { |
9105 | 0 | let v2 = C::value_type(ctx, arg1); |
9106 | 0 | let v3 = C::ty_scalar_float(ctx, v2); |
9107 | 0 | if let Some(v4) = v3 { |
9108 | 0 | let v6 = &constructor_x64_ucomis(ctx, arg2, arg1); |
9109 | 0 | let v14 = FcmpCondResult::Condition { |
9110 | 0 | producer: v6.clone(), |
9111 | 0 | cc: CC::P, |
9112 | 0 | }; |
9113 | 0 | // Rule at src/isa/x64/inst.isle line 4535. |
9114 | 0 | return v14; |
9115 | 0 | } |
9116 | | } |
9117 | | &FloatCC::UnorderedOrEqual => { |
9118 | 0 | let v2 = C::value_type(ctx, arg1); |
9119 | 0 | let v3 = C::ty_scalar_float(ctx, v2); |
9120 | 0 | if let Some(v4) = v3 { |
9121 | 0 | let v6 = &constructor_x64_ucomis(ctx, arg2, arg1); |
9122 | 0 | let v16 = FcmpCondResult::Condition { |
9123 | 0 | producer: v6.clone(), |
9124 | 0 | cc: CC::Z, |
9125 | 0 | }; |
9126 | 0 | // Rule at src/isa/x64/inst.isle line 4539. |
9127 | 0 | return v16; |
9128 | 0 | } |
9129 | | } |
9130 | | &FloatCC::UnorderedOrGreaterThan => { |
9131 | 0 | let v2 = C::value_type(ctx, arg1); |
9132 | 0 | let v3 = C::ty_scalar_float(ctx, v2); |
9133 | 0 | if let Some(v4) = v3 { |
9134 | 0 | let v25 = &constructor_x64_ucomis(ctx, arg1, arg2); |
9135 | 0 | let v28 = FcmpCondResult::Condition { |
9136 | 0 | producer: v25.clone(), |
9137 | 0 | cc: CC::B, |
9138 | 0 | }; |
9139 | 0 | // Rule at src/isa/x64/inst.isle line 4559. |
9140 | 0 | return v28; |
9141 | 0 | } |
9142 | | } |
9143 | | &FloatCC::UnorderedOrGreaterThanOrEqual => { |
9144 | 0 | let v2 = C::value_type(ctx, arg1); |
9145 | 0 | let v3 = C::ty_scalar_float(ctx, v2); |
9146 | 0 | if let Some(v4) = v3 { |
9147 | 0 | let v25 = &constructor_x64_ucomis(ctx, arg1, arg2); |
9148 | 0 | let v29 = FcmpCondResult::Condition { |
9149 | 0 | producer: v25.clone(), |
9150 | 0 | cc: CC::BE, |
9151 | 0 | }; |
9152 | 0 | // Rule at src/isa/x64/inst.isle line 4562. |
9153 | 0 | return v29; |
9154 | 0 | } |
9155 | | } |
9156 | | &FloatCC::UnorderedOrLessThan => { |
9157 | 0 | let v2 = C::value_type(ctx, arg1); |
9158 | 0 | let v3 = C::ty_scalar_float(ctx, v2); |
9159 | 0 | if let Some(v4) = v3 { |
9160 | 0 | let v6 = &constructor_x64_ucomis(ctx, arg2, arg1); |
9161 | 0 | let v22 = FcmpCondResult::Condition { |
9162 | 0 | producer: v6.clone(), |
9163 | 0 | cc: CC::B, |
9164 | 0 | }; |
9165 | 0 | // Rule at src/isa/x64/inst.isle line 4545. |
9166 | 0 | return v22; |
9167 | 0 | } |
9168 | | } |
9169 | | &FloatCC::UnorderedOrLessThanOrEqual => { |
9170 | 0 | let v2 = C::value_type(ctx, arg1); |
9171 | 0 | let v3 = C::ty_scalar_float(ctx, v2); |
9172 | 0 | if let Some(v4) = v3 { |
9173 | 0 | let v6 = &constructor_x64_ucomis(ctx, arg2, arg1); |
9174 | 0 | let v24 = FcmpCondResult::Condition { |
9175 | 0 | producer: v6.clone(), |
9176 | 0 | cc: CC::BE, |
9177 | 0 | }; |
9178 | 0 | // Rule at src/isa/x64/inst.isle line 4547. |
9179 | 0 | return v24; |
9180 | 0 | } |
9181 | | } |
9182 | 0 | _ => {} |
9183 | | } |
9184 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "emit_fcmp", "src/isa/x64/inst.isle line 4523") |
9185 | 0 | } |
9186 | | |
9187 | | // Generated as internal constructor for term x64_mfence. |
9188 | 0 | pub fn constructor_x64_mfence<C: Context>( |
9189 | 0 | ctx: &mut C, |
9190 | 0 | ) -> SideEffectNoResult { |
9191 | 0 | let v1 = MInst::Fence { |
9192 | 0 | kind: FenceKind::MFence, |
9193 | 0 | }; |
9194 | 0 | let v2 = SideEffectNoResult::Inst { |
9195 | 0 | inst: v1, |
9196 | 0 | }; |
9197 | 0 | // Rule at src/isa/x64/inst.isle line 4575. |
9198 | 0 | return v2; |
9199 | 0 | } |
9200 | | |
9201 | | // Generated as internal constructor for term x64_cmpxchg. |
9202 | 0 | pub fn constructor_x64_cmpxchg<C: Context>( |
9203 | 0 | ctx: &mut C, |
9204 | 0 | arg0: Type, |
9205 | 0 | arg1: Gpr, |
9206 | 0 | arg2: Gpr, |
9207 | 0 | arg3: &SyntheticAmode, |
9208 | 0 | ) -> Gpr { |
9209 | 0 | let v4 = C::temp_writable_gpr(ctx); |
9210 | 0 | let v5 = C::gpr_to_reg(ctx, arg2); |
9211 | 0 | let v6 = C::gpr_to_reg(ctx, arg1); |
9212 | 0 | let v7 = C::writable_gpr_to_reg(ctx, v4); |
9213 | 0 | let v8 = MInst::LockCmpxchg { |
9214 | 0 | ty: arg0, |
9215 | 0 | replacement: v5, |
9216 | 0 | expected: v6, |
9217 | 0 | mem: arg3.clone(), |
9218 | 0 | dst_old: v7, |
9219 | 0 | }; |
9220 | 0 | let v9 = C::emit(ctx, &v8); |
9221 | 0 | let v10 = C::writable_gpr_to_gpr(ctx, v4); |
9222 | 0 | // Rule at src/isa/x64/inst.isle line 4579. |
9223 | 0 | return v10; |
9224 | 0 | } |
9225 | | |
9226 | | // Generated as internal constructor for term x64_atomic_rmw_seq. |
9227 | 0 | pub fn constructor_x64_atomic_rmw_seq<C: Context>( |
9228 | 0 | ctx: &mut C, |
9229 | 0 | arg0: Type, |
9230 | 0 | arg1: &MachAtomicRmwOp, |
9231 | 0 | arg2: &SyntheticAmode, |
9232 | 0 | arg3: Gpr, |
9233 | 0 | ) -> Gpr { |
9234 | 0 | let v4 = C::temp_writable_gpr(ctx); |
9235 | 0 | let v5 = C::temp_writable_gpr(ctx); |
9236 | 0 | let v6 = C::gpr_to_reg(ctx, arg3); |
9237 | 0 | let v7 = C::writable_gpr_to_reg(ctx, v5); |
9238 | 0 | let v8 = C::writable_gpr_to_reg(ctx, v4); |
9239 | 0 | let v9 = MInst::AtomicRmwSeq { |
9240 | 0 | ty: arg0, |
9241 | 0 | op: arg1.clone(), |
9242 | 0 | mem: arg2.clone(), |
9243 | 0 | operand: v6, |
9244 | 0 | temp: v7, |
9245 | 0 | dst_old: v8, |
9246 | 0 | }; |
9247 | 0 | let v10 = C::emit(ctx, &v9); |
9248 | 0 | let v11 = C::writable_gpr_to_gpr(ctx, v4); |
9249 | 0 | // Rule at src/isa/x64/inst.isle line 4585. |
9250 | 0 | return v11; |
9251 | 0 | } |
9252 | | |
9253 | | // Generated as internal constructor for term bitcast_xmm_to_gpr. |
9254 | 0 | pub fn constructor_bitcast_xmm_to_gpr<C: Context>( |
9255 | 0 | ctx: &mut C, |
9256 | 0 | arg0: Type, |
9257 | 0 | arg1: Xmm, |
9258 | 0 | ) -> Gpr { |
9259 | 0 | match arg0 { |
9260 | | F32 => { |
9261 | 0 | let v2 = constructor_x64_movd_to_gpr(ctx, arg1); |
9262 | 0 | // Rule at src/isa/x64/inst.isle line 4600. |
9263 | 0 | return v2; |
9264 | | } |
9265 | | F64 => { |
9266 | 0 | let v3 = constructor_x64_movq_to_gpr(ctx, arg1); |
9267 | 0 | // Rule at src/isa/x64/inst.isle line 4602. |
9268 | 0 | return v3; |
9269 | | } |
9270 | 0 | _ => {} |
9271 | 0 | } |
9272 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "bitcast_xmm_to_gpr", "src/isa/x64/inst.isle line 4599") |
9273 | 0 | } |
9274 | | |
9275 | | // Generated as internal constructor for term bitcast_gpr_to_xmm. |
9276 | 0 | pub fn constructor_bitcast_gpr_to_xmm<C: Context>( |
9277 | 0 | ctx: &mut C, |
9278 | 0 | arg0: Type, |
9279 | 0 | arg1: Gpr, |
9280 | 0 | ) -> Xmm { |
9281 | 0 | match arg0 { |
9282 | | I32 => { |
9283 | 0 | let v2 = &C::gpr_to_gpr_mem(ctx, arg1); |
9284 | 0 | let v3 = constructor_x64_movd_to_xmm(ctx, v2); |
9285 | 0 | // Rule at src/isa/x64/inst.isle line 4606. |
9286 | 0 | return v3; |
9287 | | } |
9288 | | I64 => { |
9289 | 0 | let v2 = &C::gpr_to_gpr_mem(ctx, arg1); |
9290 | 0 | let v4 = constructor_x64_movq_to_xmm(ctx, v2); |
9291 | 0 | // Rule at src/isa/x64/inst.isle line 4608. |
9292 | 0 | return v4; |
9293 | | } |
9294 | 0 | _ => {} |
9295 | 0 | } |
9296 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "bitcast_gpr_to_xmm", "src/isa/x64/inst.isle line 4605") |
9297 | 0 | } |
9298 | | |
9299 | | // Generated as internal constructor for term stack_addr_impl. |
9300 | 112 | pub fn constructor_stack_addr_impl<C: Context>( |
9301 | 112 | ctx: &mut C, |
9302 | 112 | arg0: StackSlot, |
9303 | 112 | arg1: Offset32, |
9304 | 112 | ) -> Gpr { |
9305 | 112 | let v2 = C::temp_writable_gpr(ctx); |
9306 | 112 | let v3 = C::writable_gpr_to_reg(ctx, v2); |
9307 | 112 | let v4 = &C::abi_stackslot_addr(ctx, v3, arg0, arg1); |
9308 | 112 | let v5 = C::emit(ctx, v4); |
9309 | 112 | let v6 = C::writable_gpr_to_gpr(ctx, v2); |
9310 | 112 | // Rule at src/isa/x64/inst.isle line 4614. |
9311 | 112 | return v6; |
9312 | 112 | } |
9313 | | |
9314 | | // Generated as internal constructor for term x64_checked_srem_seq. |
9315 | 0 | pub fn constructor_x64_checked_srem_seq<C: Context>( |
9316 | 0 | ctx: &mut C, |
9317 | 0 | arg0: &OperandSize, |
9318 | 0 | arg1: Gpr, |
9319 | 0 | arg2: Gpr, |
9320 | 0 | arg3: Gpr, |
9321 | 0 | ) -> ValueRegs { |
9322 | 0 | let v4 = C::temp_writable_gpr(ctx); |
9323 | 0 | let v5 = C::temp_writable_gpr(ctx); |
9324 | 0 | let v6 = MInst::CheckedSRemSeq { |
9325 | 0 | size: arg0.clone(), |
9326 | 0 | dividend_lo: arg1, |
9327 | 0 | dividend_hi: arg2, |
9328 | 0 | divisor: arg3, |
9329 | 0 | dst_quotient: v4, |
9330 | 0 | dst_remainder: v5, |
9331 | 0 | }; |
9332 | 0 | let v7 = C::emit(ctx, &v6); |
9333 | 0 | let v8 = constructor_writable_gpr_to_r_reg(ctx, v4); |
9334 | 0 | let v9 = constructor_writable_gpr_to_r_reg(ctx, v5); |
9335 | 0 | let v10 = C::value_regs(ctx, v8, v9); |
9336 | 0 | // Rule at src/isa/x64/inst.isle line 4623. |
9337 | 0 | return v10; |
9338 | 0 | } |
9339 | | |
9340 | | // Generated as internal constructor for term x64_checked_srem_seq8. |
9341 | 0 | pub fn constructor_x64_checked_srem_seq8<C: Context>( |
9342 | 0 | ctx: &mut C, |
9343 | 0 | arg0: Gpr, |
9344 | 0 | arg1: Gpr, |
9345 | 0 | ) -> Gpr { |
9346 | 0 | let v2 = C::temp_writable_gpr(ctx); |
9347 | 0 | let v3 = MInst::CheckedSRemSeq8 { |
9348 | 0 | dividend: arg0, |
9349 | 0 | divisor: arg1, |
9350 | 0 | dst: v2, |
9351 | 0 | }; |
9352 | 0 | let v4 = C::emit(ctx, &v3); |
9353 | 0 | let v5 = C::writable_gpr_to_gpr(ctx, v2); |
9354 | 0 | // Rule at src/isa/x64/inst.isle line 4630. |
9355 | 0 | return v5; |
9356 | 0 | } |
9357 | | |
9358 | | // Generated as internal constructor for term x64_div8. |
9359 | 0 | pub fn constructor_x64_div8<C: Context>( |
9360 | 0 | ctx: &mut C, |
9361 | 0 | arg0: Gpr, |
9362 | 0 | arg1: &GprMem, |
9363 | 0 | arg2: &DivSignedness, |
9364 | 0 | arg3: &TrapCode, |
9365 | 0 | ) -> Gpr { |
9366 | 0 | let v4 = C::temp_writable_gpr(ctx); |
9367 | 0 | let v5 = MInst::Div8 { |
9368 | 0 | sign: arg2.clone(), |
9369 | 0 | trap: arg3.clone(), |
9370 | 0 | divisor: arg1.clone(), |
9371 | 0 | dividend: arg0, |
9372 | 0 | dst: v4, |
9373 | 0 | }; |
9374 | 0 | let v6 = C::emit(ctx, &v5); |
9375 | 0 | let v7 = C::writable_gpr_to_gpr(ctx, v4); |
9376 | 0 | // Rule at src/isa/x64/inst.isle line 4637. |
9377 | 0 | return v7; |
9378 | 0 | } |
9379 | | |
9380 | | // Generated as internal constructor for term x64_div. |
9381 | 1.44k | pub fn constructor_x64_div<C: Context>( |
9382 | 1.44k | ctx: &mut C, |
9383 | 1.44k | arg0: Gpr, |
9384 | 1.44k | arg1: Gpr, |
9385 | 1.44k | arg2: &GprMem, |
9386 | 1.44k | arg3: &OperandSize, |
9387 | 1.44k | arg4: &DivSignedness, |
9388 | 1.44k | arg5: &TrapCode, |
9389 | 1.44k | ) -> ValueRegs { |
9390 | 1.44k | let v6 = C::temp_writable_gpr(ctx); |
9391 | 1.44k | let v7 = C::temp_writable_gpr(ctx); |
9392 | 1.44k | let v8 = MInst::Div { |
9393 | 1.44k | size: arg3.clone(), |
9394 | 1.44k | sign: arg4.clone(), |
9395 | 1.44k | trap: arg5.clone(), |
9396 | 1.44k | divisor: arg2.clone(), |
9397 | 1.44k | dividend_lo: arg0, |
9398 | 1.44k | dividend_hi: arg1, |
9399 | 1.44k | dst_quotient: v6, |
9400 | 1.44k | dst_remainder: v7, |
9401 | 1.44k | }; |
9402 | 1.44k | let v9 = C::emit(ctx, &v8); |
9403 | 1.44k | let v10 = constructor_writable_gpr_to_r_reg(ctx, v6); |
9404 | 1.44k | let v11 = constructor_writable_gpr_to_r_reg(ctx, v7); |
9405 | 1.44k | let v12 = C::value_regs(ctx, v10, v11); |
9406 | 1.44k | // Rule at src/isa/x64/inst.isle line 4647. |
9407 | 1.44k | return v12; |
9408 | 1.44k | } |
9409 | | |
9410 | | // Generated as internal constructor for term x64_div_quotient. |
9411 | 1.26k | pub fn constructor_x64_div_quotient<C: Context>( |
9412 | 1.26k | ctx: &mut C, |
9413 | 1.26k | arg0: Gpr, |
9414 | 1.26k | arg1: Gpr, |
9415 | 1.26k | arg2: &GprMem, |
9416 | 1.26k | arg3: &OperandSize, |
9417 | 1.26k | arg4: &DivSignedness, |
9418 | 1.26k | arg5: &TrapCode, |
9419 | 1.26k | ) -> ValueRegs { |
9420 | 1.26k | let v6 = constructor_x64_div(ctx, arg0, arg1, arg2, arg3, arg4, arg5); |
9421 | 1.26k | let v8 = C::value_regs_get(ctx, v6, 0x0); |
9422 | 1.26k | let v9 = C::value_reg(ctx, v8); |
9423 | 1.26k | // Rule at src/isa/x64/inst.isle line 4655. |
9424 | 1.26k | return v9; |
9425 | 1.26k | } |
9426 | | |
9427 | | // Generated as internal constructor for term x64_div_remainder. |
9428 | 175 | pub fn constructor_x64_div_remainder<C: Context>( |
9429 | 175 | ctx: &mut C, |
9430 | 175 | arg0: Gpr, |
9431 | 175 | arg1: Gpr, |
9432 | 175 | arg2: &GprMem, |
9433 | 175 | arg3: &OperandSize, |
9434 | 175 | arg4: &DivSignedness, |
9435 | 175 | arg5: &TrapCode, |
9436 | 175 | ) -> ValueRegs { |
9437 | 175 | let v6 = constructor_x64_div(ctx, arg0, arg1, arg2, arg3, arg4, arg5); |
9438 | 175 | let v8 = C::value_regs_get(ctx, v6, 0x1); |
9439 | 175 | let v9 = C::value_reg(ctx, v8); |
9440 | 175 | // Rule at src/isa/x64/inst.isle line 4660. |
9441 | 175 | return v9; |
9442 | 175 | } |
9443 | | |
9444 | | // Generated as internal constructor for term x64_sign_extend_data. |
9445 | 121 | pub fn constructor_x64_sign_extend_data<C: Context>( |
9446 | 121 | ctx: &mut C, |
9447 | 121 | arg0: Gpr, |
9448 | 121 | arg1: &OperandSize, |
9449 | 121 | ) -> Gpr { |
9450 | 121 | let v2 = C::temp_writable_gpr(ctx); |
9451 | 121 | let v3 = MInst::SignExtendData { |
9452 | 121 | size: arg1.clone(), |
9453 | 121 | src: arg0, |
9454 | 121 | dst: v2, |
9455 | 121 | }; |
9456 | 121 | let v4 = C::emit(ctx, &v3); |
9457 | 121 | let v5 = C::writable_gpr_to_gpr(ctx, v2); |
9458 | 121 | // Rule at src/isa/x64/inst.isle line 4665. |
9459 | 121 | return v5; |
9460 | 121 | } |
9461 | | |
9462 | | // Generated as internal constructor for term read_pinned_gpr. |
9463 | 0 | pub fn constructor_read_pinned_gpr<C: Context>( |
9464 | 0 | ctx: &mut C, |
9465 | 0 | ) -> Gpr { |
9466 | 0 | let v0 = C::preg_pinned(ctx); |
9467 | 0 | let v1 = constructor_mov_from_preg(ctx, v0); |
9468 | 0 | let v2 = C::gpr_new(ctx, v1); |
9469 | 0 | // Rule at src/isa/x64/inst.isle line 4673. |
9470 | 0 | return v2; |
9471 | 0 | } |
9472 | | |
9473 | | // Generated as internal constructor for term write_pinned_gpr. |
9474 | 0 | pub fn constructor_write_pinned_gpr<C: Context>( |
9475 | 0 | ctx: &mut C, |
9476 | 0 | arg0: Gpr, |
9477 | 0 | ) -> SideEffectNoResult { |
9478 | 0 | let v1 = C::preg_pinned(ctx); |
9479 | 0 | let v2 = &constructor_mov_to_preg(ctx, v1, arg0); |
9480 | 0 | // Rule at src/isa/x64/inst.isle line 4677. |
9481 | 0 | return v2.clone(); |
9482 | 0 | } |
9483 | | |
9484 | | // Generated as internal constructor for term elf_tls_get_addr. |
9485 | 0 | pub fn constructor_elf_tls_get_addr<C: Context>( |
9486 | 0 | ctx: &mut C, |
9487 | 0 | arg0: ExternalName, |
9488 | 0 | ) -> Gpr { |
9489 | 0 | let v1 = C::temp_writable_gpr(ctx); |
9490 | 0 | let v2 = MInst::ElfTlsGetAddr { |
9491 | 0 | symbol: arg0, |
9492 | 0 | dst: v1, |
9493 | 0 | }; |
9494 | 0 | let v3 = C::emit(ctx, &v2); |
9495 | 0 | let v4 = C::writable_gpr_to_gpr(ctx, v1); |
9496 | 0 | // Rule at src/isa/x64/inst.isle line 4725. |
9497 | 0 | return v4; |
9498 | 0 | } |
9499 | | |
9500 | | // Generated as internal constructor for term macho_tls_get_addr. |
9501 | 0 | pub fn constructor_macho_tls_get_addr<C: Context>( |
9502 | 0 | ctx: &mut C, |
9503 | 0 | arg0: ExternalName, |
9504 | 0 | ) -> Gpr { |
9505 | 0 | let v1 = C::temp_writable_gpr(ctx); |
9506 | 0 | let v2 = MInst::MachOTlsGetAddr { |
9507 | 0 | symbol: arg0, |
9508 | 0 | dst: v1, |
9509 | 0 | }; |
9510 | 0 | let v3 = C::emit(ctx, &v2); |
9511 | 0 | let v4 = C::writable_gpr_to_gpr(ctx, v1); |
9512 | 0 | // Rule at src/isa/x64/inst.isle line 4732. |
9513 | 0 | return v4; |
9514 | 0 | } |
9515 | | |
9516 | | // Generated as internal constructor for term coff_tls_get_addr. |
9517 | 0 | pub fn constructor_coff_tls_get_addr<C: Context>( |
9518 | 0 | ctx: &mut C, |
9519 | 0 | arg0: ExternalName, |
9520 | 0 | ) -> Gpr { |
9521 | 0 | let v1 = C::temp_writable_gpr(ctx); |
9522 | 0 | let v2 = C::temp_writable_gpr(ctx); |
9523 | 0 | let v3 = MInst::CoffTlsGetAddr { |
9524 | 0 | symbol: arg0, |
9525 | 0 | dst: v1, |
9526 | 0 | tmp: v2, |
9527 | 0 | }; |
9528 | 0 | let v4 = C::emit(ctx, &v3); |
9529 | 0 | let v5 = C::writable_gpr_to_gpr(ctx, v1); |
9530 | 0 | // Rule at src/isa/x64/inst.isle line 4739. |
9531 | 0 | return v5; |
9532 | 0 | } |
9533 | | |
9534 | | // Generated as internal constructor for term reg_to_xmm_mem. |
9535 | 0 | pub fn constructor_reg_to_xmm_mem<C: Context>( |
9536 | 0 | ctx: &mut C, |
9537 | 0 | arg0: Reg, |
9538 | 0 | ) -> XmmMem { |
9539 | 0 | let v1 = C::xmm_new(ctx, arg0); |
9540 | 0 | let v2 = &C::xmm_to_xmm_mem(ctx, v1); |
9541 | 0 | // Rule at src/isa/x64/inst.isle line 4837. |
9542 | 0 | return v2.clone(); |
9543 | 0 | } |
9544 | | |
9545 | | // Generated as internal constructor for term xmm_to_reg_mem. |
9546 | 0 | pub fn constructor_xmm_to_reg_mem<C: Context>( |
9547 | 0 | ctx: &mut C, |
9548 | 0 | arg0: Reg, |
9549 | 0 | ) -> XmmMem { |
9550 | 0 | let v1 = C::xmm_new(ctx, arg0); |
9551 | 0 | let v2 = C::xmm_to_reg(ctx, v1); |
9552 | 0 | let v3 = RegMem::Reg { |
9553 | 0 | reg: v2, |
9554 | 0 | }; |
9555 | 0 | let v4 = &C::reg_mem_to_xmm_mem(ctx, &v3); |
9556 | 0 | // Rule at src/isa/x64/inst.isle line 4840. |
9557 | 0 | return v4.clone(); |
9558 | 0 | } |
9559 | | |
9560 | | // Generated as internal constructor for term writable_gpr_to_r_reg. |
9561 | 682k | pub fn constructor_writable_gpr_to_r_reg<C: Context>( |
9562 | 682k | ctx: &mut C, |
9563 | 682k | arg0: WritableGpr, |
9564 | 682k | ) -> Reg { |
9565 | 682k | let v1 = C::writable_gpr_to_reg(ctx, arg0); |
9566 | 682k | let v2 = C::writable_reg_to_reg(ctx, v1); |
9567 | 682k | // Rule at src/isa/x64/inst.isle line 4844. |
9568 | 682k | return v2; |
9569 | 682k | } |
9570 | | |
9571 | | // Generated as internal constructor for term writable_gpr_to_gpr_mem. |
9572 | 0 | pub fn constructor_writable_gpr_to_gpr_mem<C: Context>( |
9573 | 0 | ctx: &mut C, |
9574 | 0 | arg0: WritableGpr, |
9575 | 0 | ) -> GprMem { |
9576 | 0 | let v1 = C::writable_gpr_to_gpr(ctx, arg0); |
9577 | 0 | let v2 = &C::gpr_to_gpr_mem(ctx, v1); |
9578 | 0 | // Rule at src/isa/x64/inst.isle line 4847. |
9579 | 0 | return v2.clone(); |
9580 | 0 | } |
9581 | | |
9582 | | // Generated as internal constructor for term writable_gpr_to_value_regs. |
9583 | 0 | pub fn constructor_writable_gpr_to_value_regs<C: Context>( |
9584 | 0 | ctx: &mut C, |
9585 | 0 | arg0: WritableGpr, |
9586 | 0 | ) -> ValueRegs { |
9587 | 0 | let v1 = constructor_writable_gpr_to_r_reg(ctx, arg0); |
9588 | 0 | let v2 = C::value_reg(ctx, v1); |
9589 | 0 | // Rule at src/isa/x64/inst.isle line 4850. |
9590 | 0 | return v2; |
9591 | 0 | } |
9592 | | |
9593 | | // Generated as internal constructor for term writable_xmm_to_r_reg. |
9594 | 0 | pub fn constructor_writable_xmm_to_r_reg<C: Context>( |
9595 | 0 | ctx: &mut C, |
9596 | 0 | arg0: WritableXmm, |
9597 | 0 | ) -> Reg { |
9598 | 0 | let v1 = C::writable_xmm_to_reg(ctx, arg0); |
9599 | 0 | let v2 = C::writable_reg_to_reg(ctx, v1); |
9600 | 0 | // Rule at src/isa/x64/inst.isle line 4853. |
9601 | 0 | return v2; |
9602 | 0 | } |
9603 | | |
9604 | | // Generated as internal constructor for term writable_xmm_to_xmm_mem. |
9605 | 0 | pub fn constructor_writable_xmm_to_xmm_mem<C: Context>( |
9606 | 0 | ctx: &mut C, |
9607 | 0 | arg0: WritableXmm, |
9608 | 0 | ) -> XmmMem { |
9609 | 0 | let v1 = C::writable_xmm_to_xmm(ctx, arg0); |
9610 | 0 | let v2 = &C::xmm_to_xmm_mem(ctx, v1); |
9611 | 0 | // Rule at src/isa/x64/inst.isle line 4856. |
9612 | 0 | return v2.clone(); |
9613 | 0 | } |
9614 | | |
9615 | | // Generated as internal constructor for term writable_xmm_to_value_regs. |
9616 | 0 | pub fn constructor_writable_xmm_to_value_regs<C: Context>( |
9617 | 0 | ctx: &mut C, |
9618 | 0 | arg0: WritableXmm, |
9619 | 0 | ) -> ValueRegs { |
9620 | 0 | let v1 = constructor_writable_xmm_to_r_reg(ctx, arg0); |
9621 | 0 | let v2 = C::value_reg(ctx, v1); |
9622 | 0 | // Rule at src/isa/x64/inst.isle line 4859. |
9623 | 0 | return v2; |
9624 | 0 | } |
9625 | | |
9626 | | // Generated as internal constructor for term synthetic_amode_to_gpr_mem. |
9627 | 325k | pub fn constructor_synthetic_amode_to_gpr_mem<C: Context>( |
9628 | 325k | ctx: &mut C, |
9629 | 325k | arg0: &SyntheticAmode, |
9630 | 325k | ) -> GprMem { |
9631 | 325k | let v1 = &C::synthetic_amode_to_reg_mem(ctx, arg0); |
9632 | 325k | let v2 = &C::reg_mem_to_gpr_mem(ctx, v1); |
9633 | 325k | // Rule at src/isa/x64/inst.isle line 4866. |
9634 | 325k | return v2.clone(); |
9635 | 325k | } |
9636 | | |
9637 | | // Generated as internal constructor for term amode_to_gpr_mem. |
9638 | 325k | pub fn constructor_amode_to_gpr_mem<C: Context>( |
9639 | 325k | ctx: &mut C, |
9640 | 325k | arg0: &Amode, |
9641 | 325k | ) -> GprMem { |
9642 | 325k | let v1 = &C::amode_to_synthetic_amode(ctx, arg0); |
9643 | 325k | let v2 = &constructor_synthetic_amode_to_gpr_mem(ctx, v1); |
9644 | 325k | // Rule at src/isa/x64/inst.isle line 4864. |
9645 | 325k | return v2.clone(); |
9646 | 325k | } |
9647 | | |
9648 | | // Generated as internal constructor for term amode_to_xmm_mem. |
9649 | 0 | pub fn constructor_amode_to_xmm_mem<C: Context>( |
9650 | 0 | ctx: &mut C, |
9651 | 0 | arg0: &Amode, |
9652 | 0 | ) -> XmmMem { |
9653 | 0 | let v1 = &C::amode_to_synthetic_amode(ctx, arg0); |
9654 | 0 | let v2 = &constructor_synthetic_amode_to_xmm_mem(ctx, v1); |
9655 | 0 | // Rule at src/isa/x64/inst.isle line 4869. |
9656 | 0 | return v2.clone(); |
9657 | 0 | } |
9658 | | |
9659 | | // Generated as internal constructor for term synthetic_amode_to_xmm_mem. |
9660 | 0 | pub fn constructor_synthetic_amode_to_xmm_mem<C: Context>( |
9661 | 0 | ctx: &mut C, |
9662 | 0 | arg0: &SyntheticAmode, |
9663 | 0 | ) -> XmmMem { |
9664 | 0 | let v1 = &C::synthetic_amode_to_reg_mem(ctx, arg0); |
9665 | 0 | let v2 = &C::reg_mem_to_xmm_mem(ctx, v1); |
9666 | 0 | // Rule at src/isa/x64/inst.isle line 4872. |
9667 | 0 | return v2.clone(); |
9668 | 0 | } |
9669 | | |
9670 | | // Generated as internal constructor for term const_to_xmm_mem. |
9671 | 0 | pub fn constructor_const_to_xmm_mem<C: Context>( |
9672 | 0 | ctx: &mut C, |
9673 | 0 | arg0: VCodeConstant, |
9674 | 0 | ) -> XmmMem { |
9675 | 0 | let v1 = &C::const_to_synthetic_amode(ctx, arg0); |
9676 | 0 | let v2 = &constructor_synthetic_amode_to_xmm_mem(ctx, v1); |
9677 | 0 | // Rule at src/isa/x64/inst.isle line 4877. |
9678 | 0 | return v2.clone(); |
9679 | 0 | } |
9680 | | |
9681 | | // Generated as internal constructor for term xmm_to_xmm_mem_aligned. |
9682 | 0 | pub fn constructor_xmm_to_xmm_mem_aligned<C: Context>( |
9683 | 0 | ctx: &mut C, |
9684 | 0 | arg0: Xmm, |
9685 | 0 | ) -> XmmMemAligned { |
9686 | 0 | let v1 = &C::xmm_to_xmm_mem(ctx, arg0); |
9687 | 0 | let v2 = &C::xmm_mem_to_xmm_mem_aligned(ctx, v1); |
9688 | 0 | // Rule at src/isa/x64/inst.isle line 4880. |
9689 | 0 | return v2.clone(); |
9690 | 0 | } |
9691 | | |
9692 | | // Generated as internal constructor for term amode_to_xmm_mem_aligned. |
9693 | 0 | pub fn constructor_amode_to_xmm_mem_aligned<C: Context>( |
9694 | 0 | ctx: &mut C, |
9695 | 0 | arg0: &Amode, |
9696 | 0 | ) -> XmmMemAligned { |
9697 | 0 | let v1 = &constructor_amode_to_xmm_mem(ctx, arg0); |
9698 | 0 | let v2 = &C::xmm_mem_to_xmm_mem_aligned(ctx, v1); |
9699 | 0 | // Rule at src/isa/x64/inst.isle line 4882. |
9700 | 0 | return v2.clone(); |
9701 | 0 | } |
9702 | | |
9703 | | // Generated as internal constructor for term synthetic_amode_to_xmm_mem_aligned. |
9704 | 0 | pub fn constructor_synthetic_amode_to_xmm_mem_aligned<C: Context>( |
9705 | 0 | ctx: &mut C, |
9706 | 0 | arg0: &SyntheticAmode, |
9707 | 0 | ) -> XmmMemAligned { |
9708 | 0 | let v1 = &constructor_synthetic_amode_to_xmm_mem(ctx, arg0); |
9709 | 0 | let v2 = &C::xmm_mem_to_xmm_mem_aligned(ctx, v1); |
9710 | 0 | // Rule at src/isa/x64/inst.isle line 4884. |
9711 | 0 | return v2.clone(); |
9712 | 0 | } |
9713 | | |
9714 | | // Generated as internal constructor for term put_in_xmm_mem_aligned. |
9715 | 0 | pub fn constructor_put_in_xmm_mem_aligned<C: Context>( |
9716 | 0 | ctx: &mut C, |
9717 | 0 | arg0: Value, |
9718 | 0 | ) -> XmmMemAligned { |
9719 | 0 | let v1 = &C::put_in_xmm_mem(ctx, arg0); |
9720 | 0 | let v2 = &C::xmm_mem_to_xmm_mem_aligned(ctx, v1); |
9721 | 0 | // Rule at src/isa/x64/inst.isle line 4886. |
9722 | 0 | return v2.clone(); |
9723 | 0 | } |
9724 | | |
9725 | | // Generated as internal constructor for term mov_from_preg. |
9726 | 0 | pub fn constructor_mov_from_preg<C: Context>( |
9727 | 0 | ctx: &mut C, |
9728 | 0 | arg0: PReg, |
9729 | 0 | ) -> Reg { |
9730 | 0 | let v1 = C::temp_writable_gpr(ctx); |
9731 | 0 | let v2 = MInst::MovFromPReg { |
9732 | 0 | src: arg0, |
9733 | 0 | dst: v1, |
9734 | 0 | }; |
9735 | 0 | let v3 = C::emit(ctx, &v2); |
9736 | 0 | let v4 = constructor_writable_gpr_to_r_reg(ctx, v1); |
9737 | 0 | // Rule at src/isa/x64/inst.isle line 4890. |
9738 | 0 | return v4; |
9739 | 0 | } |
9740 | | |
9741 | | // Generated as internal constructor for term mov_to_preg. |
9742 | 0 | pub fn constructor_mov_to_preg<C: Context>( |
9743 | 0 | ctx: &mut C, |
9744 | 0 | arg0: PReg, |
9745 | 0 | arg1: Gpr, |
9746 | 0 | ) -> SideEffectNoResult { |
9747 | 0 | let v2 = MInst::MovToPReg { |
9748 | 0 | src: arg1, |
9749 | 0 | dst: arg0, |
9750 | 0 | }; |
9751 | 0 | let v3 = SideEffectNoResult::Inst { |
9752 | 0 | inst: v2, |
9753 | 0 | }; |
9754 | 0 | // Rule at src/isa/x64/inst.isle line 4896. |
9755 | 0 | return v3; |
9756 | 0 | } |
9757 | | |
9758 | | // Generated as internal constructor for term x64_rbp. |
9759 | 0 | pub fn constructor_x64_rbp<C: Context>( |
9760 | 0 | ctx: &mut C, |
9761 | 0 | ) -> Reg { |
9762 | 0 | let v0 = C::preg_rbp(ctx); |
9763 | 0 | let v1 = constructor_mov_from_preg(ctx, v0); |
9764 | 0 | // Rule at src/isa/x64/inst.isle line 4909. |
9765 | 0 | return v1; |
9766 | 0 | } |
9767 | | |
9768 | | // Generated as internal constructor for term x64_rsp. |
9769 | 0 | pub fn constructor_x64_rsp<C: Context>( |
9770 | 0 | ctx: &mut C, |
9771 | 0 | ) -> Reg { |
9772 | 0 | let v0 = C::preg_rsp(ctx); |
9773 | 0 | let v1 = constructor_mov_from_preg(ctx, v0); |
9774 | 0 | // Rule at src/isa/x64/inst.isle line 4913. |
9775 | 0 | return v1; |
9776 | 0 | } |
9777 | | |
9778 | | // Generated as internal constructor for term lower. |
9779 | 2.66M | pub fn constructor_lower<C: Context>( |
9780 | 2.66M | ctx: &mut C, |
9781 | 2.66M | arg0: Inst, |
9782 | 2.66M | ) -> Option<InstOutput> { |
9783 | 2.66M | let v6 = &C::inst_data(ctx, arg0); |
9784 | 2.66M | match v6 { |
9785 | | &InstructionData::AtomicCas { |
9786 | 18.4E | opcode: ref v1488, |
9787 | 18.4E | args: ref v1489, |
9788 | 18.4E | flags: v1490, |
9789 | 18.4E | } => { |
9790 | 18.4E | if let &Opcode::AtomicCas = v1488 { |
9791 | 18.4E | let v1 = C::first_result(ctx, arg0); |
9792 | 18.4E | if let Some(v2) = v1 { |
9793 | 18.4E | let v3 = C::value_type(ctx, v2); |
9794 | 18.4E | let v4 = C::fits_in_64(ctx, v3); |
9795 | 18.4E | if let Some(v5) = v4 { |
9796 | 18.4E | let v1463 = C::ty_int(ctx, v3); |
9797 | 18.4E | if let Some(v14640 ) = v1463 { |
9798 | 0 | let v1491 = C::unpack_value_array_3(ctx, v1489); |
9799 | 0 | let v1495 = constructor_put_in_gpr(ctx, v1491.1); |
9800 | 0 | let v1496 = constructor_put_in_gpr(ctx, v1491.2); |
9801 | 0 | let v1497 = C::zero_offset(ctx); |
9802 | 0 | let v1498 = &constructor_to_amode(ctx, v1490, v1491.0, v1497); |
9803 | 0 | let v1499 = &C::amode_to_synthetic_amode(ctx, v1498); |
9804 | 0 | let v1500 = constructor_x64_cmpxchg(ctx, v5, v1495, v1496, v1499); |
9805 | 0 | let v1501 = constructor_output_gpr(ctx, v1500); |
9806 | 0 | // Rule at src/isa/x64/lower.isle line 2749. |
9807 | 0 | return Some(v1501); |
9808 | 0 | } |
9809 | 0 | } |
9810 | 0 | } |
9811 | 0 | } |
9812 | | } |
9813 | | &InstructionData::AtomicRmw { |
9814 | 0 | opcode: ref v1502, |
9815 | 0 | args: ref v1503, |
9816 | 0 | flags: v1504, |
9817 | 0 | op: ref v1505, |
9818 | 0 | } => { |
9819 | 0 | if let &Opcode::AtomicRmw = v1502 { |
9820 | 0 | let v1 = C::first_result(ctx, arg0); |
9821 | 0 | if let Some(v2) = v1 { |
9822 | 0 | let v3 = C::value_type(ctx, v2); |
9823 | 0 | let v4 = C::fits_in_64(ctx, v3); |
9824 | 0 | if let Some(v5) = v4 { |
9825 | 0 | let v1463 = C::ty_int(ctx, v3); |
9826 | 0 | if let Some(v1464) = v1463 { |
9827 | 0 | let v1509 = &C::atomic_rmw_op_to_mach_atomic_rmw_op(ctx, v1505); |
9828 | 0 | let v1465 = C::zero_offset(ctx); |
9829 | 0 | let v1506 = C::unpack_value_array_2(ctx, v1503); |
9830 | 0 | let v1510 = &constructor_to_amode(ctx, v1504, v1506.0, v1465); |
9831 | 0 | let v1511 = &C::amode_to_synthetic_amode(ctx, v1510); |
9832 | 0 | let v1512 = constructor_put_in_gpr(ctx, v1506.1); |
9833 | 0 | let v1513 = constructor_x64_atomic_rmw_seq(ctx, v5, v1509, v1511, v1512); |
9834 | 0 | let v1514 = constructor_output_gpr(ctx, v1513); |
9835 | 0 | // Rule at src/isa/x64/lower.isle line 2765. |
9836 | 0 | return Some(v1514); |
9837 | 0 | } |
9838 | 0 | } |
9839 | 0 | } |
9840 | 0 | } |
9841 | | } |
9842 | | &InstructionData::Binary { |
9843 | 613k | opcode: ref v36, |
9844 | 613k | args: ref v37, |
9845 | 613k | } => { |
9846 | 613k | match v36 { |
9847 | | &Opcode::Swizzle => { |
9848 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
9849 | 0 | let v1013 = constructor_put_in_xmm(ctx, v38.1); |
9850 | 0 | let v2072 = C::swizzle_zero_mask(ctx); |
9851 | 0 | let v2073 = &constructor_const_to_xmm_mem(ctx, v2072); |
9852 | 0 | let v2074 = constructor_x64_paddusb(ctx, v1013, v2073); |
9853 | 0 | let v2075 = constructor_put_in_xmm(ctx, v38.0); |
9854 | 0 | let v2076 = &C::xmm_to_xmm_mem(ctx, v2074); |
9855 | 0 | let v2077 = constructor_x64_pshufb(ctx, v2075, v2076); |
9856 | 0 | let v2078 = constructor_output_xmm(ctx, v2077); |
9857 | 0 | // Rule at src/isa/x64/lower.isle line 3702. |
9858 | 0 | return Some(v2078); |
9859 | | } |
9860 | | &Opcode::X86Pshufb => { |
9861 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
9862 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
9863 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
9864 | 0 | let v2079 = constructor_x64_pshufb(ctx, v68, v69); |
9865 | 0 | let v2080 = constructor_output_xmm(ctx, v2079); |
9866 | 0 | // Rule at src/isa/x64/lower.isle line 3708. |
9867 | 0 | return Some(v2080); |
9868 | | } |
9869 | | &Opcode::Smin => { |
9870 | 18.4E | let v1 = C::first_result(ctx, arg0); |
9871 | 18.4E | if let Some(v2) = v1 { |
9872 | 18.4E | let v3 = C::value_type(ctx, v2); |
9873 | 18.4E | match v3 { |
9874 | | I8X16 => { |
9875 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
9876 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
9877 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
9878 | 0 | let v600 = constructor_x64_pminsb(ctx, v68, v69); |
9879 | 0 | let v601 = constructor_output_xmm(ctx, v600); |
9880 | 0 | // Rule at src/isa/x64/lower.isle line 1332. |
9881 | 0 | return Some(v601); |
9882 | | } |
9883 | | I16X8 => { |
9884 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
9885 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
9886 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
9887 | 0 | let v602 = constructor_x64_pminsw(ctx, v68, v69); |
9888 | 0 | let v603 = constructor_output_xmm(ctx, v602); |
9889 | 0 | // Rule at src/isa/x64/lower.isle line 1335. |
9890 | 0 | return Some(v603); |
9891 | | } |
9892 | | I32X4 => { |
9893 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
9894 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
9895 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
9896 | 0 | let v604 = constructor_x64_pminsd(ctx, v68, v69); |
9897 | 0 | let v605 = constructor_output_xmm(ctx, v604); |
9898 | 0 | // Rule at src/isa/x64/lower.isle line 1338. |
9899 | 0 | return Some(v605); |
9900 | | } |
9901 | 18.4E | _ => {} |
9902 | 18.4E | } |
9903 | 18.4E | let v4 = C::fits_in_64(ctx, v3); |
9904 | 18.4E | if let Some(v50 ) = v4 { |
9905 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
9906 | 0 | let v589 = constructor_cmp_and_choose(ctx, v5, &CC::L, v38.0, v38.1); |
9907 | 0 | let v590 = C::output(ctx, v589); |
9908 | 0 | // Rule at src/isa/x64/lower.isle line 1313. |
9909 | 0 | return Some(v590); |
9910 | 0 | } |
9911 | 0 | } |
9912 | | } |
9913 | | &Opcode::Umin => { |
9914 | 746 | let v1 = C::first_result(ctx, arg0); |
9915 | 746 | if let Some(v2) = v1 { |
9916 | 746 | let v3 = C::value_type(ctx, v2); |
9917 | 746 | match v3 { |
9918 | | I8X16 => { |
9919 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
9920 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
9921 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
9922 | 0 | let v612 = constructor_x64_pminub(ctx, v68, v69); |
9923 | 0 | let v613 = constructor_output_xmm(ctx, v612); |
9924 | 0 | // Rule at src/isa/x64/lower.isle line 1354. |
9925 | 0 | return Some(v613); |
9926 | | } |
9927 | | I16X8 => { |
9928 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
9929 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
9930 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
9931 | 0 | let v614 = constructor_x64_pminuw(ctx, v68, v69); |
9932 | 0 | let v615 = constructor_output_xmm(ctx, v614); |
9933 | 0 | // Rule at src/isa/x64/lower.isle line 1357. |
9934 | 0 | return Some(v615); |
9935 | | } |
9936 | | I32X4 => { |
9937 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
9938 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
9939 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
9940 | 0 | let v616 = constructor_x64_pminud(ctx, v68, v69); |
9941 | 0 | let v617 = constructor_output_xmm(ctx, v616); |
9942 | 0 | // Rule at src/isa/x64/lower.isle line 1360. |
9943 | 0 | return Some(v617); |
9944 | | } |
9945 | 746 | _ => {} |
9946 | 746 | } |
9947 | 746 | let v4 = C::fits_in_64(ctx, v3); |
9948 | 746 | if let Some(v5) = v4 { |
9949 | 746 | let v38 = C::unpack_value_array_2(ctx, v37); |
9950 | 746 | let v583 = constructor_cmp_and_choose(ctx, v5, &CC::B, v38.0, v38.1); |
9951 | 746 | let v584 = C::output(ctx, v583); |
9952 | 746 | // Rule at src/isa/x64/lower.isle line 1307. |
9953 | 746 | return Some(v584); |
9954 | 0 | } |
9955 | 0 | } |
9956 | | } |
9957 | | &Opcode::Smax => { |
9958 | 0 | let v1 = C::first_result(ctx, arg0); |
9959 | 0 | if let Some(v2) = v1 { |
9960 | 0 | let v3 = C::value_type(ctx, v2); |
9961 | 0 | match v3 { |
9962 | | I8X16 => { |
9963 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
9964 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
9965 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
9966 | 0 | let v594 = constructor_x64_pmaxsb(ctx, v68, v69); |
9967 | 0 | let v595 = constructor_output_xmm(ctx, v594); |
9968 | 0 | // Rule at src/isa/x64/lower.isle line 1321. |
9969 | 0 | return Some(v595); |
9970 | | } |
9971 | | I16X8 => { |
9972 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
9973 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
9974 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
9975 | 0 | let v596 = constructor_x64_pmaxsw(ctx, v68, v69); |
9976 | 0 | let v597 = constructor_output_xmm(ctx, v596); |
9977 | 0 | // Rule at src/isa/x64/lower.isle line 1324. |
9978 | 0 | return Some(v597); |
9979 | | } |
9980 | | I32X4 => { |
9981 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
9982 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
9983 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
9984 | 0 | let v598 = constructor_x64_pmaxsd(ctx, v68, v69); |
9985 | 0 | let v599 = constructor_output_xmm(ctx, v598); |
9986 | 0 | // Rule at src/isa/x64/lower.isle line 1327. |
9987 | 0 | return Some(v599); |
9988 | | } |
9989 | 0 | _ => {} |
9990 | 0 | } |
9991 | 0 | let v4 = C::fits_in_64(ctx, v3); |
9992 | 0 | if let Some(v5) = v4 { |
9993 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
9994 | 0 | let v592 = constructor_cmp_and_choose(ctx, v5, &CC::NL, v38.0, v38.1); |
9995 | 0 | let v593 = C::output(ctx, v592); |
9996 | 0 | // Rule at src/isa/x64/lower.isle line 1316. |
9997 | 0 | return Some(v593); |
9998 | 0 | } |
9999 | 0 | } |
10000 | | } |
10001 | | &Opcode::Umax => { |
10002 | 819 | let v1 = C::first_result(ctx, arg0); |
10003 | 819 | if let Some(v2) = v1 { |
10004 | 819 | let v3 = C::value_type(ctx, v2); |
10005 | 819 | match v3 { |
10006 | | I8X16 => { |
10007 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10008 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
10009 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
10010 | 0 | let v606 = constructor_x64_pmaxub(ctx, v68, v69); |
10011 | 0 | let v607 = constructor_output_xmm(ctx, v606); |
10012 | 0 | // Rule at src/isa/x64/lower.isle line 1343. |
10013 | 0 | return Some(v607); |
10014 | | } |
10015 | | I16X8 => { |
10016 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10017 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
10018 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
10019 | 0 | let v608 = constructor_x64_pmaxuw(ctx, v68, v69); |
10020 | 0 | let v609 = constructor_output_xmm(ctx, v608); |
10021 | 0 | // Rule at src/isa/x64/lower.isle line 1346. |
10022 | 0 | return Some(v609); |
10023 | | } |
10024 | | I32X4 => { |
10025 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10026 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
10027 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
10028 | 0 | let v610 = constructor_x64_pmaxud(ctx, v68, v69); |
10029 | 0 | let v611 = constructor_output_xmm(ctx, v610); |
10030 | 0 | // Rule at src/isa/x64/lower.isle line 1349. |
10031 | 0 | return Some(v611); |
10032 | | } |
10033 | 819 | _ => {} |
10034 | 819 | } |
10035 | 819 | let v4 = C::fits_in_64(ctx, v3); |
10036 | 819 | if let Some(v5) = v4 { |
10037 | 819 | let v38 = C::unpack_value_array_2(ctx, v37); |
10038 | 819 | let v586 = constructor_cmp_and_choose(ctx, v5, &CC::NB, v38.0, v38.1); |
10039 | 819 | let v587 = C::output(ctx, v586); |
10040 | 819 | // Rule at src/isa/x64/lower.isle line 1310. |
10041 | 819 | return Some(v587); |
10042 | 0 | } |
10043 | 0 | } |
10044 | | } |
10045 | | &Opcode::AvgRound => { |
10046 | 0 | let v1 = C::first_result(ctx, arg0); |
10047 | 0 | if let Some(v2) = v1 { |
10048 | 0 | let v3 = C::value_type(ctx, v2); |
10049 | 0 | let v64 = C::multi_lane(ctx, v3); |
10050 | 0 | if let Some(v65) = v64 { |
10051 | 0 | match v65.0 { |
10052 | | 0x8 => { |
10053 | 0 | if v65.1 == 0x10 { |
10054 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10055 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
10056 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
10057 | 0 | let v335 = constructor_x64_pavgb(ctx, v68, v69); |
10058 | 0 | let v336 = constructor_output_xmm(ctx, v335); |
10059 | 0 | // Rule at src/isa/x64/lower.isle line 779. |
10060 | 0 | return Some(v336); |
10061 | 0 | } |
10062 | | } |
10063 | | 0x10 => { |
10064 | 0 | if v65.1 == 0x8 { |
10065 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10066 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
10067 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
10068 | 0 | let v337 = constructor_x64_pavgw(ctx, v68, v69); |
10069 | 0 | let v338 = constructor_output_xmm(ctx, v337); |
10070 | 0 | // Rule at src/isa/x64/lower.isle line 783. |
10071 | 0 | return Some(v338); |
10072 | 0 | } |
10073 | | } |
10074 | 0 | _ => {} |
10075 | | } |
10076 | 0 | } |
10077 | 0 | } |
10078 | | } |
10079 | | &Opcode::UaddSat => { |
10080 | 0 | let v1 = C::first_result(ctx, arg0); |
10081 | 0 | if let Some(v2) = v1 { |
10082 | 0 | let v3 = C::value_type(ctx, v2); |
10083 | 0 | let v64 = C::multi_lane(ctx, v3); |
10084 | 0 | if let Some(v65) = v64 { |
10085 | 0 | match v65.0 { |
10086 | | 0x8 => { |
10087 | 0 | if v65.1 == 0x10 { |
10088 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10089 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
10090 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
10091 | 0 | let v108 = constructor_x64_paddusb(ctx, v68, v69); |
10092 | 0 | let v109 = constructor_output_xmm(ctx, v108); |
10093 | 0 | // Rule at src/isa/x64/lower.isle line 126. |
10094 | 0 | return Some(v109); |
10095 | 0 | } |
10096 | | } |
10097 | | 0x10 => { |
10098 | 0 | if v65.1 == 0x8 { |
10099 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10100 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
10101 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
10102 | 0 | let v110 = constructor_x64_paddusw(ctx, v68, v69); |
10103 | 0 | let v111 = constructor_output_xmm(ctx, v110); |
10104 | 0 | // Rule at src/isa/x64/lower.isle line 130. |
10105 | 0 | return Some(v111); |
10106 | 0 | } |
10107 | | } |
10108 | 0 | _ => {} |
10109 | | } |
10110 | 0 | } |
10111 | 0 | } |
10112 | | } |
10113 | | &Opcode::SaddSat => { |
10114 | 0 | let v1 = C::first_result(ctx, arg0); |
10115 | 0 | if let Some(v2) = v1 { |
10116 | 0 | let v3 = C::value_type(ctx, v2); |
10117 | 0 | let v64 = C::multi_lane(ctx, v3); |
10118 | 0 | if let Some(v65) = v64 { |
10119 | 0 | match v65.0 { |
10120 | | 0x8 => { |
10121 | 0 | if v65.1 == 0x10 { |
10122 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10123 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
10124 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
10125 | 0 | let v104 = constructor_x64_paddsb(ctx, v68, v69); |
10126 | 0 | let v105 = constructor_output_xmm(ctx, v104); |
10127 | 0 | // Rule at src/isa/x64/lower.isle line 116. |
10128 | 0 | return Some(v105); |
10129 | 0 | } |
10130 | | } |
10131 | | 0x10 => { |
10132 | 0 | if v65.1 == 0x8 { |
10133 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10134 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
10135 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
10136 | 0 | let v106 = constructor_x64_paddsw(ctx, v68, v69); |
10137 | 0 | let v107 = constructor_output_xmm(ctx, v106); |
10138 | 0 | // Rule at src/isa/x64/lower.isle line 120. |
10139 | 0 | return Some(v107); |
10140 | 0 | } |
10141 | | } |
10142 | 0 | _ => {} |
10143 | | } |
10144 | 0 | } |
10145 | 0 | } |
10146 | | } |
10147 | | &Opcode::UsubSat => { |
10148 | 0 | let v1 = C::first_result(ctx, arg0); |
10149 | 0 | if let Some(v2) = v1 { |
10150 | 0 | let v3 = C::value_type(ctx, v2); |
10151 | 0 | let v64 = C::multi_lane(ctx, v3); |
10152 | 0 | if let Some(v65) = v64 { |
10153 | 0 | match v65.0 { |
10154 | | 0x8 => { |
10155 | 0 | if v65.1 == 0x10 { |
10156 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10157 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
10158 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
10159 | 0 | let v130 = constructor_x64_psubusb(ctx, v68, v69); |
10160 | 0 | let v131 = constructor_output_xmm(ctx, v130); |
10161 | 0 | // Rule at src/isa/x64/lower.isle line 187. |
10162 | 0 | return Some(v131); |
10163 | 0 | } |
10164 | | } |
10165 | | 0x10 => { |
10166 | 0 | if v65.1 == 0x8 { |
10167 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10168 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
10169 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
10170 | 0 | let v132 = constructor_x64_psubusw(ctx, v68, v69); |
10171 | 0 | let v133 = constructor_output_xmm(ctx, v132); |
10172 | 0 | // Rule at src/isa/x64/lower.isle line 191. |
10173 | 0 | return Some(v133); |
10174 | 0 | } |
10175 | | } |
10176 | 0 | _ => {} |
10177 | | } |
10178 | 0 | } |
10179 | 0 | } |
10180 | | } |
10181 | | &Opcode::SsubSat => { |
10182 | 0 | let v1 = C::first_result(ctx, arg0); |
10183 | 0 | if let Some(v2) = v1 { |
10184 | 0 | let v3 = C::value_type(ctx, v2); |
10185 | 0 | let v64 = C::multi_lane(ctx, v3); |
10186 | 0 | if let Some(v65) = v64 { |
10187 | 0 | match v65.0 { |
10188 | | 0x8 => { |
10189 | 0 | if v65.1 == 0x10 { |
10190 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10191 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
10192 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
10193 | 0 | let v126 = constructor_x64_psubsb(ctx, v68, v69); |
10194 | 0 | let v127 = constructor_output_xmm(ctx, v126); |
10195 | 0 | // Rule at src/isa/x64/lower.isle line 177. |
10196 | 0 | return Some(v127); |
10197 | 0 | } |
10198 | | } |
10199 | | 0x10 => { |
10200 | 0 | if v65.1 == 0x8 { |
10201 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10202 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
10203 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
10204 | 0 | let v128 = constructor_x64_psubsw(ctx, v68, v69); |
10205 | 0 | let v129 = constructor_output_xmm(ctx, v128); |
10206 | 0 | // Rule at src/isa/x64/lower.isle line 181. |
10207 | 0 | return Some(v129); |
10208 | 0 | } |
10209 | | } |
10210 | 0 | _ => {} |
10211 | | } |
10212 | 0 | } |
10213 | 0 | } |
10214 | | } |
10215 | | &Opcode::Iadd => { |
10216 | 490k | let v1 = C::first_result(ctx, arg0); |
10217 | 490k | if let Some(v2) = v1 { |
10218 | 490k | let v3 = C::value_type(ctx, v2); |
10219 | 490k | if v3 == I128 { |
10220 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10221 | 0 | let v78 = C::put_in_regs(ctx, v38.0); |
10222 | 0 | let v80 = constructor_value_regs_get_gpr(ctx, v78, 0x0); |
10223 | 0 | let v82 = constructor_value_regs_get_gpr(ctx, v78, 0x1); |
10224 | 0 | let v83 = C::put_in_regs(ctx, v38.1); |
10225 | 0 | let v84 = constructor_value_regs_get_gpr(ctx, v83, 0x0); |
10226 | 0 | let v85 = constructor_value_regs_get_gpr(ctx, v83, 0x1); |
10227 | 0 | let v86 = &C::gpr_to_gpr_mem_imm(ctx, v84); |
10228 | 0 | let v87 = &constructor_x64_add_with_flags_paired(ctx, I64, v80, v86); |
10229 | 0 | let v88 = &C::gpr_to_gpr_mem_imm(ctx, v85); |
10230 | 0 | let v89 = &constructor_x64_adc_paired(ctx, I64, v82, v88); |
10231 | 0 | let v90 = constructor_with_flags(ctx, v87, v89); |
10232 | 0 | let v91 = C::output(ctx, v90); |
10233 | 0 | // Rule at src/isa/x64/lower.isle line 88. |
10234 | 0 | return Some(v91); |
10235 | 490k | } |
10236 | 490k | let v64 = C::multi_lane(ctx, v3); |
10237 | 490k | if let Some(v6524 ) = v64 { |
10238 | 24 | match v65.0 { |
10239 | | 0x8 => { |
10240 | 24 | if v65.1 == 0x10 { |
10241 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10242 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
10243 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
10244 | 0 | let v70 = constructor_x64_paddb(ctx, v68, v69); |
10245 | 0 | let v71 = constructor_output_xmm(ctx, v70); |
10246 | 0 | // Rule at src/isa/x64/lower.isle line 71. |
10247 | 0 | return Some(v71); |
10248 | 0 | } |
10249 | | } |
10250 | | 0x10 => { |
10251 | 0 | if v65.1 == 0x8 { |
10252 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10253 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
10254 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
10255 | 0 | let v72 = constructor_x64_paddw(ctx, v68, v69); |
10256 | 0 | let v73 = constructor_output_xmm(ctx, v72); |
10257 | 0 | // Rule at src/isa/x64/lower.isle line 75. |
10258 | 0 | return Some(v73); |
10259 | 0 | } |
10260 | | } |
10261 | | 0x20 => { |
10262 | 0 | if v65.1 == 0x4 { |
10263 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10264 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
10265 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
10266 | 0 | let v74 = constructor_x64_paddd(ctx, v68, v69); |
10267 | 0 | let v75 = constructor_output_xmm(ctx, v74); |
10268 | 0 | // Rule at src/isa/x64/lower.isle line 79. |
10269 | 0 | return Some(v75); |
10270 | 0 | } |
10271 | | } |
10272 | | 0x40 => { |
10273 | 0 | if v65.1 == 0x2 { |
10274 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10275 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
10276 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
10277 | 0 | let v76 = constructor_x64_paddq(ctx, v68, v69); |
10278 | 0 | let v77 = constructor_output_xmm(ctx, v76); |
10279 | 0 | // Rule at src/isa/x64/lower.isle line 83. |
10280 | 0 | return Some(v77); |
10281 | 0 | } |
10282 | | } |
10283 | 0 | _ => {} |
10284 | | } |
10285 | 490k | } |
10286 | 490k | let v4 = C::fits_in_64(ctx, v3); |
10287 | 490k | if let Some(v5) = v4 { |
10288 | 490k | let v38 = C::unpack_value_array_2(ctx, v37); |
10289 | 490k | let v58 = &C::sinkable_load(ctx, v38.0); |
10290 | 490k | if let Some(v595.89k ) = v58 { |
10291 | 5.89k | let v60 = constructor_put_in_gpr(ctx, v38.1); |
10292 | 5.89k | let v61 = &constructor_sink_load_to_gpr_mem_imm(ctx, v59); |
10293 | 5.89k | let v62 = constructor_x64_add(ctx, v5, v60, v61); |
10294 | 5.89k | let v63 = constructor_output_gpr(ctx, v62); |
10295 | 5.89k | // Rule at src/isa/x64/lower.isle line 65. |
10296 | 5.89k | return Some(v63); |
10297 | 484k | } |
10298 | 484k | let v53 = &C::sinkable_load(ctx, v38.1); |
10299 | 484k | if let Some(v54104 ) = v53 { |
10300 | 104 | let v41 = constructor_put_in_gpr(ctx, v38.0); |
10301 | 104 | let v55 = &constructor_sink_load_to_gpr_mem_imm(ctx, v54); |
10302 | 104 | let v56 = constructor_x64_add(ctx, v5, v41, v55); |
10303 | 104 | let v57 = constructor_output_gpr(ctx, v56); |
10304 | 104 | // Rule at src/isa/x64/lower.isle line 62. |
10305 | 104 | return Some(v57); |
10306 | 484k | } |
10307 | 0 | } |
10308 | 484k | let v45 = C::ty_32_or_64(ctx, v3); |
10309 | 484k | if let Some(v46484k ) = v45 { |
10310 | 484k | let v48 = C::zero_offset(ctx); |
10311 | 484k | let v47 = C::mem_flags_trusted(ctx); |
10312 | 484k | let v38 = C::unpack_value_array_2(ctx, v37); |
10313 | 484k | let v49 = &constructor_to_amode_add(ctx, v47, v38.0, v38.1, v48); |
10314 | 484k | let v50 = &C::amode_to_synthetic_amode(ctx, v49); |
10315 | 484k | let v51 = constructor_x64_lea(ctx, v46, v50); |
10316 | 484k | let v52 = constructor_output_gpr(ctx, v51); |
10317 | 484k | // Rule at src/isa/x64/lower.isle line 56. |
10318 | 484k | return Some(v52); |
10319 | 30 | } |
10320 | 30 | let v34 = C::fits_in_16(ctx, v3); |
10321 | 30 | if let Some(v350 ) = v34 { |
10322 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10323 | 0 | let v41 = constructor_put_in_gpr(ctx, v38.0); |
10324 | 0 | let v42 = &constructor_put_in_gpr_mem_imm(ctx, v38.1); |
10325 | 0 | let v43 = constructor_x64_add(ctx, v35, v41, v42); |
10326 | 0 | let v44 = constructor_output_gpr(ctx, v43); |
10327 | 0 | // Rule at src/isa/x64/lower.isle line 45. |
10328 | 0 | return Some(v44); |
10329 | 0 | } |
10330 | 0 | } |
10331 | | } |
10332 | | &Opcode::Isub => { |
10333 | 32.2k | let v1 = C::first_result(ctx, arg0); |
10334 | 32.2k | if let Some(v2) = v1 { |
10335 | 32.2k | let v3 = C::value_type(ctx, v2); |
10336 | 32.2k | if v3 == I128 { |
10337 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10338 | 0 | let v78 = C::put_in_regs(ctx, v38.0); |
10339 | 0 | let v80 = constructor_value_regs_get_gpr(ctx, v78, 0x0); |
10340 | 0 | let v82 = constructor_value_regs_get_gpr(ctx, v78, 0x1); |
10341 | 0 | let v83 = C::put_in_regs(ctx, v38.1); |
10342 | 0 | let v84 = constructor_value_regs_get_gpr(ctx, v83, 0x0); |
10343 | 0 | let v85 = constructor_value_regs_get_gpr(ctx, v83, 0x1); |
10344 | 0 | let v86 = &C::gpr_to_gpr_mem_imm(ctx, v84); |
10345 | 0 | let v122 = &constructor_x64_sub_with_flags_paired(ctx, I64, v80, v86); |
10346 | 0 | let v88 = &C::gpr_to_gpr_mem_imm(ctx, v85); |
10347 | 0 | let v123 = &constructor_x64_sbb_paired(ctx, I64, v82, v88); |
10348 | 0 | let v124 = constructor_with_flags(ctx, v122, v123); |
10349 | 0 | let v125 = C::output(ctx, v124); |
10350 | 0 | // Rule at src/isa/x64/lower.isle line 162. |
10351 | 0 | return Some(v125); |
10352 | 32.2k | } |
10353 | 32.2k | let v64 = C::multi_lane(ctx, v3); |
10354 | 32.2k | if let Some(v650 ) = v64 { |
10355 | 0 | match v65.0 { |
10356 | | 0x8 => { |
10357 | 0 | if v65.1 == 0x10 { |
10358 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10359 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
10360 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
10361 | 0 | let v114 = constructor_x64_psubb(ctx, v68, v69); |
10362 | 0 | let v115 = constructor_output_xmm(ctx, v114); |
10363 | 0 | // Rule at src/isa/x64/lower.isle line 145. |
10364 | 0 | return Some(v115); |
10365 | 0 | } |
10366 | | } |
10367 | | 0x10 => { |
10368 | 0 | if v65.1 == 0x8 { |
10369 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10370 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
10371 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
10372 | 0 | let v116 = constructor_x64_psubw(ctx, v68, v69); |
10373 | 0 | let v117 = constructor_output_xmm(ctx, v116); |
10374 | 0 | // Rule at src/isa/x64/lower.isle line 149. |
10375 | 0 | return Some(v117); |
10376 | 0 | } |
10377 | | } |
10378 | | 0x20 => { |
10379 | 0 | if v65.1 == 0x4 { |
10380 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10381 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
10382 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
10383 | 0 | let v118 = constructor_x64_psubd(ctx, v68, v69); |
10384 | 0 | let v119 = constructor_output_xmm(ctx, v118); |
10385 | 0 | // Rule at src/isa/x64/lower.isle line 153. |
10386 | 0 | return Some(v119); |
10387 | 0 | } |
10388 | | } |
10389 | | 0x40 => { |
10390 | 0 | if v65.1 == 0x2 { |
10391 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10392 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
10393 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
10394 | 0 | let v120 = constructor_x64_psubq(ctx, v68, v69); |
10395 | 0 | let v121 = constructor_output_xmm(ctx, v120); |
10396 | 0 | // Rule at src/isa/x64/lower.isle line 157. |
10397 | 0 | return Some(v121); |
10398 | 0 | } |
10399 | | } |
10400 | 0 | _ => {} |
10401 | | } |
10402 | 32.2k | } |
10403 | 32.2k | let v4 = C::fits_in_64(ctx, v3); |
10404 | 32.2k | if let Some(v5) = v4 { |
10405 | 32.2k | let v38 = C::unpack_value_array_2(ctx, v37); |
10406 | 32.2k | let v41 = constructor_put_in_gpr(ctx, v38.0); |
10407 | 32.2k | let v42 = &constructor_put_in_gpr_mem_imm(ctx, v38.1); |
10408 | 32.2k | let v112 = constructor_x64_sub(ctx, v5, v41, v42); |
10409 | 32.2k | let v113 = constructor_output_gpr(ctx, v112); |
10410 | 32.2k | // Rule at src/isa/x64/lower.isle line 139. |
10411 | 32.2k | return Some(v113); |
10412 | 0 | } |
10413 | 0 | } |
10414 | | } |
10415 | | &Opcode::Imul => { |
10416 | 20.4k | let v1 = C::first_result(ctx, arg0); |
10417 | 20.4k | if let Some(v2) = v1 { |
10418 | 20.4k | let v3 = C::value_type(ctx, v2); |
10419 | 20.4k | let v64 = C::multi_lane(ctx, v3); |
10420 | 20.4k | if let Some(v650 ) = v64 { |
10421 | 0 | if v65.0 == 0x40 { |
10422 | 0 | if v65.1 == 0x2 { |
10423 | 0 | let v363 = C::avx512vl_enabled(ctx, v3); |
10424 | 0 | if v363 == true { |
10425 | 0 | let v364 = C::avx512dq_enabled(ctx, v3); |
10426 | 0 | if v364 == true { |
10427 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10428 | 0 | let v365 = &C::put_in_xmm_mem(ctx, v38.0); |
10429 | 0 | let v366 = constructor_put_in_xmm(ctx, v38.1); |
10430 | 0 | let v367 = constructor_x64_vpmullq(ctx, v365, v366); |
10431 | 0 | let v368 = constructor_output_xmm(ctx, v367); |
10432 | 0 | // Rule at src/isa/x64/lower.isle line 855. |
10433 | 0 | return Some(v368); |
10434 | 0 | } |
10435 | 0 | } |
10436 | 0 | } |
10437 | 0 | } |
10438 | 20.4k | } |
10439 | 20.4k | if v3 == I128 { |
10440 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10441 | 0 | let v78 = C::put_in_regs(ctx, v38.0); |
10442 | 0 | let v80 = constructor_value_regs_get_gpr(ctx, v78, 0x0); |
10443 | 0 | let v82 = constructor_value_regs_get_gpr(ctx, v78, 0x1); |
10444 | 0 | let v83 = C::put_in_regs(ctx, v38.1); |
10445 | 0 | let v84 = constructor_value_regs_get_gpr(ctx, v83, 0x0); |
10446 | 0 | let v85 = constructor_value_regs_get_gpr(ctx, v83, 0x1); |
10447 | 0 | let v345 = &C::gpr_to_gpr_mem_imm(ctx, v85); |
10448 | 0 | let v346 = constructor_x64_mul(ctx, I64, v80, v345); |
10449 | 0 | let v347 = &C::gpr_to_gpr_mem_imm(ctx, v84); |
10450 | 0 | let v348 = constructor_x64_mul(ctx, I64, v82, v347); |
10451 | 0 | let v349 = &C::gpr_to_gpr_mem_imm(ctx, v348); |
10452 | 0 | let v350 = constructor_x64_add(ctx, I64, v346, v349); |
10453 | 0 | let v351 = &C::gpr_to_gpr_mem(ctx, v84); |
10454 | 0 | let v352 = constructor_mulhi_u(ctx, I64, v80, v351); |
10455 | 0 | let v353 = constructor_value_regs_get_gpr(ctx, v352, 0x0); |
10456 | 0 | let v354 = constructor_value_regs_get_gpr(ctx, v352, 0x1); |
10457 | 0 | let v355 = &C::gpr_to_gpr_mem_imm(ctx, v354); |
10458 | 0 | let v356 = constructor_x64_add(ctx, I64, v350, v355); |
10459 | 0 | let v357 = constructor_value_gprs(ctx, v353, v356); |
10460 | 0 | let v358 = C::output(ctx, v357); |
10461 | 0 | // Rule at src/isa/x64/lower.isle line 820. |
10462 | 0 | return Some(v358); |
10463 | 20.4k | } |
10464 | 20.4k | if let Some(v650 ) = v64 { |
10465 | 0 | match v65.0 { |
10466 | | 0x10 => { |
10467 | 0 | if v65.1 == 0x8 { |
10468 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10469 | 0 | let v154 = C::def_inst(ctx, v38.1); |
10470 | 0 | if let Some(v155) = v154 { |
10471 | 0 | let v156 = &C::inst_data(ctx, v155); |
10472 | | if let &InstructionData::Unary { |
10473 | 0 | opcode: ref v157, |
10474 | 0 | arg: v158, |
10475 | 0 | } = v156 { |
10476 | 0 | match v157 { |
10477 | | &Opcode::SwidenLow => { |
10478 | 0 | let v163 = C::def_inst(ctx, v38.0); |
10479 | 0 | if let Some(v164) = v163 { |
10480 | 0 | let v165 = &C::inst_data(ctx, v164); |
10481 | | if let &InstructionData::Unary { |
10482 | 0 | opcode: ref v166, |
10483 | 0 | arg: v167, |
10484 | 0 | } = v165 { |
10485 | 0 | if let &Opcode::SwidenLow = v166 { |
10486 | 0 | let v387 = C::value_type(ctx, v167); |
10487 | 0 | let v388 = C::multi_lane(ctx, v387); |
10488 | 0 | if let Some(v389) = v388 { |
10489 | 0 | if v389.0 == 0x8 { |
10490 | 0 | if v389.1 == 0x10 { |
10491 | 0 | let v392 = C::value_type(ctx, v158); |
10492 | 0 | let v393 = C::multi_lane(ctx, v392); |
10493 | 0 | if let Some(v394) = v393 { |
10494 | 0 | if v394.0 == 0x8 { |
10495 | 0 | if v394.1 == 0x10 { |
10496 | 0 | let v418 = &C::put_in_xmm_mem(ctx, v167); |
10497 | 0 | let v426 = constructor_x64_pmovsxbw(ctx, v418); |
10498 | 0 | let v421 = &C::put_in_xmm_mem(ctx, v158); |
10499 | 0 | let v427 = constructor_x64_pmovsxbw(ctx, v421); |
10500 | 0 | let v428 = &C::xmm_to_xmm_mem(ctx, v427); |
10501 | 0 | let v429 = constructor_x64_pmullw(ctx, v426, v428); |
10502 | 0 | let v430 = constructor_output_xmm(ctx, v429); |
10503 | 0 | // Rule at src/isa/x64/lower.isle line 939. |
10504 | 0 | return Some(v430); |
10505 | 0 | } |
10506 | 0 | } |
10507 | 0 | } |
10508 | 0 | } |
10509 | 0 | } |
10510 | 0 | } |
10511 | 0 | } |
10512 | 0 | } |
10513 | 0 | } |
10514 | | } |
10515 | | &Opcode::SwidenHigh => { |
10516 | 0 | let v163 = C::def_inst(ctx, v38.0); |
10517 | 0 | if let Some(v164) = v163 { |
10518 | 0 | let v165 = &C::inst_data(ctx, v164); |
10519 | | if let &InstructionData::Unary { |
10520 | 0 | opcode: ref v166, |
10521 | 0 | arg: v167, |
10522 | 0 | } = v165 { |
10523 | 0 | if let &Opcode::SwidenHigh = v166 { |
10524 | 0 | let v387 = C::value_type(ctx, v167); |
10525 | 0 | let v388 = C::multi_lane(ctx, v387); |
10526 | 0 | if let Some(v389) = v388 { |
10527 | 0 | if v389.0 == 0x8 { |
10528 | 0 | if v389.1 == 0x10 { |
10529 | 0 | let v392 = C::value_type(ctx, v158); |
10530 | 0 | let v393 = C::multi_lane(ctx, v392); |
10531 | 0 | if let Some(v394) = v393 { |
10532 | 0 | if v394.0 == 0x8 { |
10533 | 0 | if v394.1 == 0x10 { |
10534 | 0 | let v168 = constructor_put_in_xmm(ctx, v167); |
10535 | 0 | let v397 = &C::xmm_to_xmm_mem(ctx, v168); |
10536 | 0 | let v399 = constructor_x64_palignr(ctx, v168, v397, 0x8); |
10537 | 0 | let v400 = &C::xmm_to_xmm_mem(ctx, v399); |
10538 | 0 | let v401 = constructor_x64_pmovsxbw(ctx, v400); |
10539 | 0 | let v402 = constructor_put_in_xmm(ctx, v158); |
10540 | 0 | let v403 = &C::xmm_to_xmm_mem(ctx, v402); |
10541 | 0 | let v404 = constructor_x64_palignr(ctx, v402, v403, 0x8); |
10542 | 0 | let v405 = &C::xmm_to_xmm_mem(ctx, v404); |
10543 | 0 | let v406 = constructor_x64_pmovsxbw(ctx, v405); |
10544 | 0 | let v407 = &C::xmm_to_xmm_mem(ctx, v406); |
10545 | 0 | let v408 = constructor_x64_pmullw(ctx, v401, v407); |
10546 | 0 | let v409 = constructor_output_xmm(ctx, v408); |
10547 | 0 | // Rule at src/isa/x64/lower.isle line 903. |
10548 | 0 | return Some(v409); |
10549 | 0 | } |
10550 | 0 | } |
10551 | 0 | } |
10552 | 0 | } |
10553 | 0 | } |
10554 | 0 | } |
10555 | 0 | } |
10556 | 0 | } |
10557 | 0 | } |
10558 | | } |
10559 | | &Opcode::UwidenLow => { |
10560 | 0 | let v163 = C::def_inst(ctx, v38.0); |
10561 | 0 | if let Some(v164) = v163 { |
10562 | 0 | let v165 = &C::inst_data(ctx, v164); |
10563 | | if let &InstructionData::Unary { |
10564 | 0 | opcode: ref v166, |
10565 | 0 | arg: v167, |
10566 | 0 | } = v165 { |
10567 | 0 | if let &Opcode::UwidenLow = v166 { |
10568 | 0 | let v387 = C::value_type(ctx, v167); |
10569 | 0 | let v388 = C::multi_lane(ctx, v387); |
10570 | 0 | if let Some(v389) = v388 { |
10571 | 0 | if v389.0 == 0x8 { |
10572 | 0 | if v389.1 == 0x10 { |
10573 | 0 | let v392 = C::value_type(ctx, v158); |
10574 | 0 | let v393 = C::multi_lane(ctx, v392); |
10575 | 0 | if let Some(v394) = v393 { |
10576 | 0 | if v394.0 == 0x8 { |
10577 | 0 | if v394.1 == 0x10 { |
10578 | 0 | let v418 = &C::put_in_xmm_mem(ctx, v167); |
10579 | 0 | let v450 = constructor_x64_pmovzxbw(ctx, v418); |
10580 | 0 | let v421 = &C::put_in_xmm_mem(ctx, v158); |
10581 | 0 | let v451 = constructor_x64_pmovzxbw(ctx, v421); |
10582 | 0 | let v452 = &C::xmm_to_xmm_mem(ctx, v451); |
10583 | 0 | let v453 = constructor_x64_pmullw(ctx, v450, v452); |
10584 | 0 | let v454 = constructor_output_xmm(ctx, v453); |
10585 | 0 | // Rule at src/isa/x64/lower.isle line 1007. |
10586 | 0 | return Some(v454); |
10587 | 0 | } |
10588 | 0 | } |
10589 | 0 | } |
10590 | 0 | } |
10591 | 0 | } |
10592 | 0 | } |
10593 | 0 | } |
10594 | 0 | } |
10595 | 0 | } |
10596 | | } |
10597 | | &Opcode::UwidenHigh => { |
10598 | 0 | let v163 = C::def_inst(ctx, v38.0); |
10599 | 0 | if let Some(v164) = v163 { |
10600 | 0 | let v165 = &C::inst_data(ctx, v164); |
10601 | | if let &InstructionData::Unary { |
10602 | 0 | opcode: ref v166, |
10603 | 0 | arg: v167, |
10604 | 0 | } = v165 { |
10605 | 0 | if let &Opcode::UwidenHigh = v166 { |
10606 | 0 | let v387 = C::value_type(ctx, v167); |
10607 | 0 | let v388 = C::multi_lane(ctx, v387); |
10608 | 0 | if let Some(v389) = v388 { |
10609 | 0 | if v389.0 == 0x8 { |
10610 | 0 | if v389.1 == 0x10 { |
10611 | 0 | let v392 = C::value_type(ctx, v158); |
10612 | 0 | let v393 = C::multi_lane(ctx, v392); |
10613 | 0 | if let Some(v394) = v393 { |
10614 | 0 | if v394.0 == 0x8 { |
10615 | 0 | if v394.1 == 0x10 { |
10616 | 0 | let v168 = constructor_put_in_xmm(ctx, v167); |
10617 | 0 | let v397 = &C::xmm_to_xmm_mem(ctx, v168); |
10618 | 0 | let v399 = constructor_x64_palignr(ctx, v168, v397, 0x8); |
10619 | 0 | let v400 = &C::xmm_to_xmm_mem(ctx, v399); |
10620 | 0 | let v439 = constructor_x64_pmovzxbw(ctx, v400); |
10621 | 0 | let v402 = constructor_put_in_xmm(ctx, v158); |
10622 | 0 | let v403 = &C::xmm_to_xmm_mem(ctx, v402); |
10623 | 0 | let v404 = constructor_x64_palignr(ctx, v402, v403, 0x8); |
10624 | 0 | let v405 = &C::xmm_to_xmm_mem(ctx, v404); |
10625 | 0 | let v440 = constructor_x64_pmovzxbw(ctx, v405); |
10626 | 0 | let v441 = &C::xmm_to_xmm_mem(ctx, v440); |
10627 | 0 | let v442 = constructor_x64_pmullw(ctx, v439, v441); |
10628 | 0 | let v443 = constructor_output_xmm(ctx, v442); |
10629 | 0 | // Rule at src/isa/x64/lower.isle line 971. |
10630 | 0 | return Some(v443); |
10631 | 0 | } |
10632 | 0 | } |
10633 | 0 | } |
10634 | 0 | } |
10635 | 0 | } |
10636 | 0 | } |
10637 | 0 | } |
10638 | 0 | } |
10639 | 0 | } |
10640 | | } |
10641 | 0 | _ => {} |
10642 | | } |
10643 | 0 | } |
10644 | 0 | } |
10645 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
10646 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
10647 | 0 | let v359 = constructor_x64_pmullw(ctx, v68, v69); |
10648 | 0 | let v360 = constructor_output_xmm(ctx, v359); |
10649 | 0 | // Rule at src/isa/x64/lower.isle line 847. |
10650 | 0 | return Some(v360); |
10651 | 0 | } |
10652 | | } |
10653 | | 0x20 => { |
10654 | 0 | if v65.1 == 0x4 { |
10655 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10656 | 0 | let v154 = C::def_inst(ctx, v38.1); |
10657 | 0 | if let Some(v155) = v154 { |
10658 | 0 | let v156 = &C::inst_data(ctx, v155); |
10659 | | if let &InstructionData::Unary { |
10660 | 0 | opcode: ref v157, |
10661 | 0 | arg: v158, |
10662 | 0 | } = v156 { |
10663 | 0 | match v157 { |
10664 | | &Opcode::SwidenLow => { |
10665 | 0 | let v163 = C::def_inst(ctx, v38.0); |
10666 | 0 | if let Some(v164) = v163 { |
10667 | 0 | let v165 = &C::inst_data(ctx, v164); |
10668 | | if let &InstructionData::Unary { |
10669 | 0 | opcode: ref v166, |
10670 | 0 | arg: v167, |
10671 | 0 | } = v165 { |
10672 | 0 | if let &Opcode::SwidenLow = v166 { |
10673 | 0 | let v387 = C::value_type(ctx, v167); |
10674 | 0 | let v388 = C::multi_lane(ctx, v387); |
10675 | 0 | if let Some(v389) = v388 { |
10676 | 0 | if v389.0 == 0x10 { |
10677 | 0 | if v389.1 == 0x8 { |
10678 | 0 | let v392 = C::value_type(ctx, v158); |
10679 | 0 | let v393 = C::multi_lane(ctx, v392); |
10680 | 0 | if let Some(v394) = v393 { |
10681 | 0 | if v394.0 == 0x10 { |
10682 | 0 | if v394.1 == 0x8 { |
10683 | 0 | let v168 = constructor_put_in_xmm(ctx, v167); |
10684 | 0 | let v410 = constructor_put_in_xmm(ctx, v158); |
10685 | 0 | let v411 = &C::xmm_to_xmm_mem(ctx, v410); |
10686 | 0 | let v412 = constructor_x64_pmullw(ctx, v168, v411); |
10687 | 0 | let v413 = &C::xmm_to_xmm_mem(ctx, v410); |
10688 | 0 | let v414 = constructor_x64_pmulhw(ctx, v168, v413); |
10689 | 0 | let v415 = &C::xmm_to_xmm_mem(ctx, v414); |
10690 | 0 | let v431 = constructor_x64_punpcklwd(ctx, v412, v415); |
10691 | 0 | let v432 = constructor_output_xmm(ctx, v431); |
10692 | 0 | // Rule at src/isa/x64/lower.isle line 949. |
10693 | 0 | return Some(v432); |
10694 | 0 | } |
10695 | 0 | } |
10696 | 0 | } |
10697 | 0 | } |
10698 | 0 | } |
10699 | 0 | } |
10700 | 0 | } |
10701 | 0 | } |
10702 | 0 | } |
10703 | | } |
10704 | | &Opcode::SwidenHigh => { |
10705 | 0 | let v163 = C::def_inst(ctx, v38.0); |
10706 | 0 | if let Some(v164) = v163 { |
10707 | 0 | let v165 = &C::inst_data(ctx, v164); |
10708 | | if let &InstructionData::Unary { |
10709 | 0 | opcode: ref v166, |
10710 | 0 | arg: v167, |
10711 | 0 | } = v165 { |
10712 | 0 | if let &Opcode::SwidenHigh = v166 { |
10713 | 0 | let v387 = C::value_type(ctx, v167); |
10714 | 0 | let v388 = C::multi_lane(ctx, v387); |
10715 | 0 | if let Some(v389) = v388 { |
10716 | 0 | if v389.0 == 0x10 { |
10717 | 0 | if v389.1 == 0x8 { |
10718 | 0 | let v392 = C::value_type(ctx, v158); |
10719 | 0 | let v393 = C::multi_lane(ctx, v392); |
10720 | 0 | if let Some(v394) = v393 { |
10721 | 0 | if v394.0 == 0x10 { |
10722 | 0 | if v394.1 == 0x8 { |
10723 | 0 | let v168 = constructor_put_in_xmm(ctx, v167); |
10724 | 0 | let v410 = constructor_put_in_xmm(ctx, v158); |
10725 | 0 | let v411 = &C::xmm_to_xmm_mem(ctx, v410); |
10726 | 0 | let v412 = constructor_x64_pmullw(ctx, v168, v411); |
10727 | 0 | let v413 = &C::xmm_to_xmm_mem(ctx, v410); |
10728 | 0 | let v414 = constructor_x64_pmulhw(ctx, v168, v413); |
10729 | 0 | let v415 = &C::xmm_to_xmm_mem(ctx, v414); |
10730 | 0 | let v416 = constructor_x64_punpckhwd(ctx, v412, v415); |
10731 | 0 | let v417 = constructor_output_xmm(ctx, v416); |
10732 | 0 | // Rule at src/isa/x64/lower.isle line 917. |
10733 | 0 | return Some(v417); |
10734 | 0 | } |
10735 | 0 | } |
10736 | 0 | } |
10737 | 0 | } |
10738 | 0 | } |
10739 | 0 | } |
10740 | 0 | } |
10741 | 0 | } |
10742 | 0 | } |
10743 | | } |
10744 | | &Opcode::UwidenLow => { |
10745 | 0 | let v163 = C::def_inst(ctx, v38.0); |
10746 | 0 | if let Some(v164) = v163 { |
10747 | 0 | let v165 = &C::inst_data(ctx, v164); |
10748 | | if let &InstructionData::Unary { |
10749 | 0 | opcode: ref v166, |
10750 | 0 | arg: v167, |
10751 | 0 | } = v165 { |
10752 | 0 | if let &Opcode::UwidenLow = v166 { |
10753 | 0 | let v387 = C::value_type(ctx, v167); |
10754 | 0 | let v388 = C::multi_lane(ctx, v387); |
10755 | 0 | if let Some(v389) = v388 { |
10756 | 0 | if v389.0 == 0x10 { |
10757 | 0 | if v389.1 == 0x8 { |
10758 | 0 | let v392 = C::value_type(ctx, v158); |
10759 | 0 | let v393 = C::multi_lane(ctx, v392); |
10760 | 0 | if let Some(v394) = v393 { |
10761 | 0 | if v394.0 == 0x10 { |
10762 | 0 | if v394.1 == 0x8 { |
10763 | 0 | let v168 = constructor_put_in_xmm(ctx, v167); |
10764 | 0 | let v410 = constructor_put_in_xmm(ctx, v158); |
10765 | 0 | let v411 = &C::xmm_to_xmm_mem(ctx, v410); |
10766 | 0 | let v412 = constructor_x64_pmullw(ctx, v168, v411); |
10767 | 0 | let v413 = &C::xmm_to_xmm_mem(ctx, v410); |
10768 | 0 | let v444 = constructor_x64_pmulhuw(ctx, v168, v413); |
10769 | 0 | let v445 = &C::xmm_to_xmm_mem(ctx, v444); |
10770 | 0 | let v455 = constructor_x64_punpcklwd(ctx, v412, v445); |
10771 | 0 | let v456 = constructor_output_xmm(ctx, v455); |
10772 | 0 | // Rule at src/isa/x64/lower.isle line 1017. |
10773 | 0 | return Some(v456); |
10774 | 0 | } |
10775 | 0 | } |
10776 | 0 | } |
10777 | 0 | } |
10778 | 0 | } |
10779 | 0 | } |
10780 | 0 | } |
10781 | 0 | } |
10782 | 0 | } |
10783 | | } |
10784 | | &Opcode::UwidenHigh => { |
10785 | 0 | let v163 = C::def_inst(ctx, v38.0); |
10786 | 0 | if let Some(v164) = v163 { |
10787 | 0 | let v165 = &C::inst_data(ctx, v164); |
10788 | | if let &InstructionData::Unary { |
10789 | 0 | opcode: ref v166, |
10790 | 0 | arg: v167, |
10791 | 0 | } = v165 { |
10792 | 0 | if let &Opcode::UwidenHigh = v166 { |
10793 | 0 | let v387 = C::value_type(ctx, v167); |
10794 | 0 | let v388 = C::multi_lane(ctx, v387); |
10795 | 0 | if let Some(v389) = v388 { |
10796 | 0 | if v389.0 == 0x10 { |
10797 | 0 | if v389.1 == 0x8 { |
10798 | 0 | let v392 = C::value_type(ctx, v158); |
10799 | 0 | let v393 = C::multi_lane(ctx, v392); |
10800 | 0 | if let Some(v394) = v393 { |
10801 | 0 | if v394.0 == 0x10 { |
10802 | 0 | if v394.1 == 0x8 { |
10803 | 0 | let v168 = constructor_put_in_xmm(ctx, v167); |
10804 | 0 | let v410 = constructor_put_in_xmm(ctx, v158); |
10805 | 0 | let v411 = &C::xmm_to_xmm_mem(ctx, v410); |
10806 | 0 | let v412 = constructor_x64_pmullw(ctx, v168, v411); |
10807 | 0 | let v413 = &C::xmm_to_xmm_mem(ctx, v410); |
10808 | 0 | let v444 = constructor_x64_pmulhuw(ctx, v168, v413); |
10809 | 0 | let v445 = &C::xmm_to_xmm_mem(ctx, v444); |
10810 | 0 | let v446 = constructor_x64_punpckhwd(ctx, v412, v445); |
10811 | 0 | let v447 = constructor_output_xmm(ctx, v446); |
10812 | 0 | // Rule at src/isa/x64/lower.isle line 985. |
10813 | 0 | return Some(v447); |
10814 | 0 | } |
10815 | 0 | } |
10816 | 0 | } |
10817 | 0 | } |
10818 | 0 | } |
10819 | 0 | } |
10820 | 0 | } |
10821 | 0 | } |
10822 | 0 | } |
10823 | | } |
10824 | 0 | _ => {} |
10825 | | } |
10826 | 0 | } |
10827 | 0 | } |
10828 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
10829 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
10830 | 0 | let v361 = constructor_x64_pmulld(ctx, v68, v69); |
10831 | 0 | let v362 = constructor_output_xmm(ctx, v361); |
10832 | 0 | // Rule at src/isa/x64/lower.isle line 850. |
10833 | 0 | return Some(v362); |
10834 | 0 | } |
10835 | | } |
10836 | | 0x40 => { |
10837 | 0 | if v65.1 == 0x2 { |
10838 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
10839 | 0 | let v154 = C::def_inst(ctx, v38.1); |
10840 | 0 | if let Some(v155) = v154 { |
10841 | 0 | let v156 = &C::inst_data(ctx, v155); |
10842 | | if let &InstructionData::Unary { |
10843 | 0 | opcode: ref v157, |
10844 | 0 | arg: v158, |
10845 | 0 | } = v156 { |
10846 | 0 | match v157 { |
10847 | | &Opcode::SwidenLow => { |
10848 | 0 | let v163 = C::def_inst(ctx, v38.0); |
10849 | 0 | if let Some(v164) = v163 { |
10850 | 0 | let v165 = &C::inst_data(ctx, v164); |
10851 | | if let &InstructionData::Unary { |
10852 | 0 | opcode: ref v166, |
10853 | 0 | arg: v167, |
10854 | 0 | } = v165 { |
10855 | 0 | if let &Opcode::SwidenLow = v166 { |
10856 | 0 | let v387 = C::value_type(ctx, v167); |
10857 | 0 | let v388 = C::multi_lane(ctx, v387); |
10858 | 0 | if let Some(v389) = v388 { |
10859 | 0 | if v389.0 == 0x20 { |
10860 | 0 | if v389.1 == 0x4 { |
10861 | 0 | let v392 = C::value_type(ctx, v158); |
10862 | 0 | let v393 = C::multi_lane(ctx, v392); |
10863 | 0 | if let Some(v394) = v393 { |
10864 | 0 | if v394.0 == 0x20 { |
10865 | 0 | if v394.1 == 0x4 { |
10866 | 0 | let v418 = &C::put_in_xmm_mem(ctx, v167); |
10867 | 0 | let v434 = constructor_x64_pshufd(ctx, v418, 0x50); |
10868 | 0 | let v421 = &C::put_in_xmm_mem(ctx, v158); |
10869 | 0 | let v435 = constructor_x64_pshufd(ctx, v421, 0x50); |
10870 | 0 | let v436 = &C::xmm_to_xmm_mem(ctx, v435); |
10871 | 0 | let v437 = constructor_x64_pmuldq(ctx, v434, v436); |
10872 | 0 | let v438 = constructor_output_xmm(ctx, v437); |
10873 | 0 | // Rule at src/isa/x64/lower.isle line 961. |
10874 | 0 | return Some(v438); |
10875 | 0 | } |
10876 | 0 | } |
10877 | 0 | } |
10878 | 0 | } |
10879 | 0 | } |
10880 | 0 | } |
10881 | 0 | } |
10882 | 0 | } |
10883 | 0 | } |
10884 | | } |
10885 | | &Opcode::SwidenHigh => { |
10886 | 0 | let v163 = C::def_inst(ctx, v38.0); |
10887 | 0 | if let Some(v164) = v163 { |
10888 | 0 | let v165 = &C::inst_data(ctx, v164); |
10889 | | if let &InstructionData::Unary { |
10890 | 0 | opcode: ref v166, |
10891 | 0 | arg: v167, |
10892 | 0 | } = v165 { |
10893 | 0 | if let &Opcode::SwidenHigh = v166 { |
10894 | 0 | let v387 = C::value_type(ctx, v167); |
10895 | 0 | let v388 = C::multi_lane(ctx, v387); |
10896 | 0 | if let Some(v389) = v388 { |
10897 | 0 | if v389.0 == 0x20 { |
10898 | 0 | if v389.1 == 0x4 { |
10899 | 0 | let v392 = C::value_type(ctx, v158); |
10900 | 0 | let v393 = C::multi_lane(ctx, v392); |
10901 | 0 | if let Some(v394) = v393 { |
10902 | 0 | if v394.0 == 0x20 { |
10903 | 0 | if v394.1 == 0x4 { |
10904 | 0 | let v418 = &C::put_in_xmm_mem(ctx, v167); |
10905 | 0 | let v420 = constructor_x64_pshufd(ctx, v418, 0xFA); |
10906 | 0 | let v421 = &C::put_in_xmm_mem(ctx, v158); |
10907 | 0 | let v422 = constructor_x64_pshufd(ctx, v421, 0xFA); |
10908 | 0 | let v423 = &C::xmm_to_xmm_mem(ctx, v422); |
10909 | 0 | let v424 = constructor_x64_pmuldq(ctx, v420, v423); |
10910 | 0 | let v425 = constructor_output_xmm(ctx, v424); |
10911 | 0 | // Rule at src/isa/x64/lower.isle line 929. |
10912 | 0 | return Some(v425); |
10913 | 0 | } |
10914 | 0 | } |
10915 | 0 | } |
10916 | 0 | } |
10917 | 0 | } |
10918 | 0 | } |
10919 | 0 | } |
10920 | 0 | } |
10921 | 0 | } |
10922 | | } |
10923 | | &Opcode::UwidenLow => { |
10924 | 0 | let v163 = C::def_inst(ctx, v38.0); |
10925 | 0 | if let Some(v164) = v163 { |
10926 | 0 | let v165 = &C::inst_data(ctx, v164); |
10927 | | if let &InstructionData::Unary { |
10928 | 0 | opcode: ref v166, |
10929 | 0 | arg: v167, |
10930 | 0 | } = v165 { |
10931 | 0 | if let &Opcode::UwidenLow = v166 { |
10932 | 0 | let v387 = C::value_type(ctx, v167); |
10933 | 0 | let v388 = C::multi_lane(ctx, v387); |
10934 | 0 | if let Some(v389) = v388 { |
10935 | 0 | if v389.0 == 0x20 { |
10936 | 0 | if v389.1 == 0x4 { |
10937 | 0 | let v392 = C::value_type(ctx, v158); |
10938 | 0 | let v393 = C::multi_lane(ctx, v392); |
10939 | 0 | if let Some(v394) = v393 { |
10940 | 0 | if v394.0 == 0x20 { |
10941 | 0 | if v394.1 == 0x4 { |
10942 | 0 | let v418 = &C::put_in_xmm_mem(ctx, v167); |
10943 | 0 | let v434 = constructor_x64_pshufd(ctx, v418, 0x50); |
10944 | 0 | let v421 = &C::put_in_xmm_mem(ctx, v158); |
10945 | 0 | let v435 = constructor_x64_pshufd(ctx, v421, 0x50); |
10946 | 0 | let v436 = &C::xmm_to_xmm_mem(ctx, v435); |
10947 | 0 | let v457 = constructor_x64_pmuludq(ctx, v434, v436); |
10948 | 0 | let v458 = constructor_output_xmm(ctx, v457); |
10949 | 0 | // Rule at src/isa/x64/lower.isle line 1029. |
10950 | 0 | return Some(v458); |
10951 | 0 | } |
10952 | 0 | } |
10953 | 0 | } |
10954 | 0 | } |
10955 | 0 | } |
10956 | 0 | } |
10957 | 0 | } |
10958 | 0 | } |
10959 | 0 | } |
10960 | | } |
10961 | | &Opcode::UwidenHigh => { |
10962 | 0 | let v163 = C::def_inst(ctx, v38.0); |
10963 | 0 | if let Some(v164) = v163 { |
10964 | 0 | let v165 = &C::inst_data(ctx, v164); |
10965 | | if let &InstructionData::Unary { |
10966 | 0 | opcode: ref v166, |
10967 | 0 | arg: v167, |
10968 | 0 | } = v165 { |
10969 | 0 | if let &Opcode::UwidenHigh = v166 { |
10970 | 0 | let v387 = C::value_type(ctx, v167); |
10971 | 0 | let v388 = C::multi_lane(ctx, v387); |
10972 | 0 | if let Some(v389) = v388 { |
10973 | 0 | if v389.0 == 0x20 { |
10974 | 0 | if v389.1 == 0x4 { |
10975 | 0 | let v392 = C::value_type(ctx, v158); |
10976 | 0 | let v393 = C::multi_lane(ctx, v392); |
10977 | 0 | if let Some(v394) = v393 { |
10978 | 0 | if v394.0 == 0x20 { |
10979 | 0 | if v394.1 == 0x4 { |
10980 | 0 | let v418 = &C::put_in_xmm_mem(ctx, v167); |
10981 | 0 | let v420 = constructor_x64_pshufd(ctx, v418, 0xFA); |
10982 | 0 | let v421 = &C::put_in_xmm_mem(ctx, v158); |
10983 | 0 | let v422 = constructor_x64_pshufd(ctx, v421, 0xFA); |
10984 | 0 | let v423 = &C::xmm_to_xmm_mem(ctx, v422); |
10985 | 0 | let v448 = constructor_x64_pmuludq(ctx, v420, v423); |
10986 | 0 | let v449 = constructor_output_xmm(ctx, v448); |
10987 | 0 | // Rule at src/isa/x64/lower.isle line 997. |
10988 | 0 | return Some(v449); |
10989 | 0 | } |
10990 | 0 | } |
10991 | 0 | } |
10992 | 0 | } |
10993 | 0 | } |
10994 | 0 | } |
10995 | 0 | } |
10996 | 0 | } |
10997 | 0 | } |
10998 | | } |
10999 | 0 | _ => {} |
11000 | | } |
11001 | 0 | } |
11002 | 0 | } |
11003 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11004 | 0 | let v366 = constructor_put_in_xmm(ctx, v38.1); |
11005 | 0 | let v370 = &C::xmi_imm(ctx, 0x20); |
11006 | 0 | let v371 = constructor_x64_psrlq(ctx, v68, v370); |
11007 | 0 | let v372 = &C::xmm_to_xmm_mem(ctx, v366); |
11008 | 0 | let v373 = constructor_x64_pmuludq(ctx, v371, v372); |
11009 | 0 | let v374 = &C::xmi_imm(ctx, 0x20); |
11010 | 0 | let v375 = constructor_x64_psrlq(ctx, v366, v374); |
11011 | 0 | let v376 = &C::xmm_to_xmm_mem(ctx, v375); |
11012 | 0 | let v377 = constructor_x64_pmuludq(ctx, v68, v376); |
11013 | 0 | let v378 = &C::xmm_to_xmm_mem(ctx, v377); |
11014 | 0 | let v379 = constructor_x64_paddq(ctx, v373, v378); |
11015 | 0 | let v380 = &C::xmi_imm(ctx, 0x20); |
11016 | 0 | let v381 = constructor_x64_psllq(ctx, v379, v380); |
11017 | 0 | let v382 = &C::xmm_to_xmm_mem(ctx, v366); |
11018 | 0 | let v383 = constructor_x64_pmuludq(ctx, v68, v382); |
11019 | 0 | let v384 = &C::xmm_to_xmm_mem(ctx, v381); |
11020 | 0 | let v385 = constructor_x64_paddq(ctx, v383, v384); |
11021 | 0 | let v386 = constructor_output_xmm(ctx, v385); |
11022 | 0 | // Rule at src/isa/x64/lower.isle line 881. |
11023 | 0 | return Some(v386); |
11024 | 0 | } |
11025 | | } |
11026 | 0 | _ => {} |
11027 | | } |
11028 | 20.4k | } |
11029 | 20.4k | let v4 = C::fits_in_64(ctx, v3); |
11030 | 20.4k | if let Some(v5) = v4 { |
11031 | 20.4k | let v38 = C::unpack_value_array_2(ctx, v37); |
11032 | 20.4k | let v58 = &C::sinkable_load(ctx, v38.0); |
11033 | 20.4k | if let Some(v59155 ) = v58 { |
11034 | 155 | let v60 = constructor_put_in_gpr(ctx, v38.1); |
11035 | 155 | let v61 = &constructor_sink_load_to_gpr_mem_imm(ctx, v59); |
11036 | 155 | let v343 = constructor_x64_mul(ctx, v5, v60, v61); |
11037 | 155 | let v344 = constructor_output_gpr(ctx, v343); |
11038 | 155 | // Rule at src/isa/x64/lower.isle line 801. |
11039 | 155 | return Some(v344); |
11040 | 20.2k | } |
11041 | 20.2k | let v140 = &C::simm32_from_value(ctx, v38.0); |
11042 | 20.2k | if let Some(v1410 ) = v140 { |
11043 | 0 | let v60 = constructor_put_in_gpr(ctx, v38.1); |
11044 | 0 | let v341 = constructor_x64_mul(ctx, v5, v60, v141); |
11045 | 0 | let v342 = constructor_output_gpr(ctx, v341); |
11046 | 0 | // Rule at src/isa/x64/lower.isle line 798. |
11047 | 0 | return Some(v342); |
11048 | 20.2k | } |
11049 | 20.2k | let v41 = constructor_put_in_gpr(ctx, v38.0); |
11050 | 20.2k | let v42 = &constructor_put_in_gpr_mem_imm(ctx, v38.1); |
11051 | 20.2k | let v339 = constructor_x64_mul(ctx, v5, v41, v42); |
11052 | 20.2k | let v340 = constructor_output_gpr(ctx, v339); |
11053 | 20.2k | // Rule at src/isa/x64/lower.isle line 792. |
11054 | 20.2k | return Some(v340); |
11055 | 0 | } |
11056 | 0 | } |
11057 | | } |
11058 | | &Opcode::Umulhi => { |
11059 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11060 | 0 | let v1756 = C::value_type(ctx, v38.0); |
11061 | 0 | match v1756 { |
11062 | | I16 => { |
11063 | 0 | let v41 = constructor_put_in_gpr(ctx, v38.0); |
11064 | 0 | let v1939 = &constructor_put_in_gpr_mem(ctx, v38.1); |
11065 | 0 | let v1940 = constructor_mul_hi(ctx, I16, false, v41, v1939); |
11066 | 0 | let v1941 = constructor_value_regs_get_gpr(ctx, v1940, 0x1); |
11067 | 0 | let v1942 = constructor_output_gpr(ctx, v1941); |
11068 | 0 | // Rule at src/isa/x64/lower.isle line 3504. |
11069 | 0 | return Some(v1942); |
11070 | | } |
11071 | | I32 => { |
11072 | 0 | let v41 = constructor_put_in_gpr(ctx, v38.0); |
11073 | 0 | let v1939 = &constructor_put_in_gpr_mem(ctx, v38.1); |
11074 | 0 | let v1943 = constructor_mul_hi(ctx, I32, false, v41, v1939); |
11075 | 0 | let v1944 = constructor_value_regs_get_gpr(ctx, v1943, 0x1); |
11076 | 0 | let v1945 = constructor_output_gpr(ctx, v1944); |
11077 | 0 | // Rule at src/isa/x64/lower.isle line 3509. |
11078 | 0 | return Some(v1945); |
11079 | | } |
11080 | | I64 => { |
11081 | 0 | let v41 = constructor_put_in_gpr(ctx, v38.0); |
11082 | 0 | let v1939 = &constructor_put_in_gpr_mem(ctx, v38.1); |
11083 | 0 | let v1946 = constructor_mul_hi(ctx, I64, false, v41, v1939); |
11084 | 0 | let v1947 = constructor_value_regs_get_gpr(ctx, v1946, 0x1); |
11085 | 0 | let v1948 = constructor_output_gpr(ctx, v1947); |
11086 | 0 | // Rule at src/isa/x64/lower.isle line 3514. |
11087 | 0 | return Some(v1948); |
11088 | | } |
11089 | 0 | _ => {} |
11090 | | } |
11091 | | } |
11092 | | &Opcode::Smulhi => { |
11093 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11094 | 0 | let v1756 = C::value_type(ctx, v38.0); |
11095 | 0 | match v1756 { |
11096 | | I16 => { |
11097 | 0 | let v41 = constructor_put_in_gpr(ctx, v38.0); |
11098 | 0 | let v1939 = &constructor_put_in_gpr_mem(ctx, v38.1); |
11099 | 0 | let v1949 = constructor_mul_hi(ctx, I16, true, v41, v1939); |
11100 | 0 | let v1950 = constructor_value_regs_get_gpr(ctx, v1949, 0x1); |
11101 | 0 | let v1951 = constructor_output_gpr(ctx, v1950); |
11102 | 0 | // Rule at src/isa/x64/lower.isle line 3521. |
11103 | 0 | return Some(v1951); |
11104 | | } |
11105 | | I32 => { |
11106 | 0 | let v41 = constructor_put_in_gpr(ctx, v38.0); |
11107 | 0 | let v1939 = &constructor_put_in_gpr_mem(ctx, v38.1); |
11108 | 0 | let v1952 = constructor_mul_hi(ctx, I32, true, v41, v1939); |
11109 | 0 | let v1953 = constructor_value_regs_get_gpr(ctx, v1952, 0x1); |
11110 | 0 | let v1954 = constructor_output_gpr(ctx, v1953); |
11111 | 0 | // Rule at src/isa/x64/lower.isle line 3526. |
11112 | 0 | return Some(v1954); |
11113 | | } |
11114 | | I64 => { |
11115 | 0 | let v41 = constructor_put_in_gpr(ctx, v38.0); |
11116 | 0 | let v1939 = &constructor_put_in_gpr_mem(ctx, v38.1); |
11117 | 0 | let v1955 = constructor_mul_hi(ctx, I64, true, v41, v1939); |
11118 | 0 | let v1956 = constructor_value_regs_get_gpr(ctx, v1955, 0x1); |
11119 | 0 | let v1957 = constructor_output_gpr(ctx, v1956); |
11120 | 0 | // Rule at src/isa/x64/lower.isle line 3531. |
11121 | 0 | return Some(v1957); |
11122 | | } |
11123 | 0 | _ => {} |
11124 | | } |
11125 | | } |
11126 | | &Opcode::SqmulRoundSat => { |
11127 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11128 | 0 | let v1756 = C::value_type(ctx, v38.0); |
11129 | 0 | if v1756 == I16X8 { |
11130 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11131 | 0 | let v366 = constructor_put_in_xmm(ctx, v38.1); |
11132 | 0 | let v2223 = C::sqmul_round_sat_mask(ctx); |
11133 | 0 | let v2224 = &constructor_const_to_xmm_mem(ctx, v2223); |
11134 | 0 | let v372 = &C::xmm_to_xmm_mem(ctx, v366); |
11135 | 0 | let v2225 = constructor_x64_pmulhrsw(ctx, v68, v372); |
11136 | 0 | let v2226 = constructor_x64_pcmpeqw(ctx, v2225, v2224); |
11137 | 0 | let v2227 = &C::xmm_to_xmm_mem(ctx, v2226); |
11138 | 0 | let v2228 = constructor_x64_pxor(ctx, v2225, v2227); |
11139 | 0 | let v2229 = constructor_output_xmm(ctx, v2228); |
11140 | 0 | // Rule at src/isa/x64/lower.isle line 3929. |
11141 | 0 | return Some(v2229); |
11142 | 0 | } |
11143 | | } |
11144 | | &Opcode::X86Pmulhrsw => { |
11145 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11146 | 0 | let v1756 = C::value_type(ctx, v38.0); |
11147 | 0 | if v1756 == I16X8 { |
11148 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11149 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
11150 | 0 | let v2230 = constructor_x64_pmulhrsw(ctx, v68, v69); |
11151 | 0 | let v2231 = constructor_output_xmm(ctx, v2230); |
11152 | 0 | // Rule at src/isa/x64/lower.isle line 3940. |
11153 | 0 | return Some(v2231); |
11154 | 0 | } |
11155 | | } |
11156 | | &Opcode::Udiv => { |
11157 | 1.14k | let v38 = C::unpack_value_array_2(ctx, v37); |
11158 | 1.14k | let v1756 = C::value_type(ctx, v38.0); |
11159 | 1.14k | if v1756 == I8 { |
11160 | 0 | let v1881 = constructor_extend_to_gpr(ctx, v38.0, I32, &ExtendKind::Zero); |
11161 | 0 | let v177 = constructor_put_in_gpr(ctx, v38.1); |
11162 | 0 | let v1882 = &C::gpr_to_gpr_mem(ctx, v177); |
11163 | 0 | let v1885 = constructor_x64_div8(ctx, v1881, v1882, &DivSignedness::Unsigned, &TrapCode::IntegerDivisionByZero); |
11164 | 0 | let v1886 = constructor_output_gpr(ctx, v1885); |
11165 | 0 | // Rule at src/isa/x64/lower.isle line 3383. |
11166 | 0 | return Some(v1886); |
11167 | 1.14k | } |
11168 | 1.14k | let v1887 = C::fits_in_64(ctx, v1756); |
11169 | 1.14k | if let Some(v1888) = v1887 { |
11170 | 1.14k | let v41 = constructor_put_in_gpr(ctx, v38.0); |
11171 | 1.14k | let v15 = constructor_imm(ctx, I64, 0x0); |
11172 | 1.14k | let v1889 = C::gpr_new(ctx, v15); |
11173 | 1.14k | let v1890 = constructor_put_in_gpr(ctx, v38.1); |
11174 | 1.14k | let v1891 = &C::gpr_to_gpr_mem(ctx, v1890); |
11175 | 1.14k | let v1892 = &C::raw_operand_size_of_type(ctx, v1888); |
11176 | 1.14k | let v1893 = constructor_x64_div_quotient(ctx, v41, v1889, v1891, v1892, &DivSignedness::Unsigned, &TrapCode::IntegerDivisionByZero); |
11177 | 1.14k | let v1894 = C::output(ctx, v1893); |
11178 | 1.14k | // Rule at src/isa/x64/lower.isle line 3392. |
11179 | 1.14k | return Some(v1894); |
11180 | 0 | } |
11181 | | } |
11182 | | &Opcode::Sdiv => { |
11183 | 121 | let v38 = C::unpack_value_array_2(ctx, v37); |
11184 | 121 | let v1756 = C::value_type(ctx, v38.0); |
11185 | 121 | if v1756 == I8 { |
11186 | 0 | let v41 = constructor_put_in_gpr(ctx, v38.0); |
11187 | 0 | let v1896 = constructor_x64_sign_extend_data(ctx, v41, &OperandSize::Size8); |
11188 | 0 | let v1897 = constructor_nonzero_sdiv_divisor(ctx, I8, v38.1); |
11189 | 0 | let v1898 = &C::reg_to_gpr_mem(ctx, v1897); |
11190 | 0 | let v1901 = constructor_x64_div8(ctx, v1896, v1898, &DivSignedness::Signed, &TrapCode::IntegerOverflow); |
11191 | 0 | let v1902 = constructor_output_gpr(ctx, v1901); |
11192 | 0 | // Rule at src/isa/x64/lower.isle line 3402. |
11193 | 0 | return Some(v1902); |
11194 | 121 | } |
11195 | 121 | let v1887 = C::fits_in_64(ctx, v1756); |
11196 | 121 | if let Some(v1888) = v1887 { |
11197 | 121 | let v41 = constructor_put_in_gpr(ctx, v38.0); |
11198 | 121 | let v1903 = &C::raw_operand_size_of_type(ctx, v1888); |
11199 | 121 | let v1904 = constructor_x64_sign_extend_data(ctx, v41, v1903); |
11200 | 121 | let v1905 = constructor_nonzero_sdiv_divisor(ctx, v1888, v38.1); |
11201 | 121 | let v1906 = &C::reg_to_gpr_mem(ctx, v1905); |
11202 | 121 | let v1907 = constructor_x64_div_quotient(ctx, v41, v1904, v1906, v1903, &DivSignedness::Signed, &TrapCode::IntegerOverflow); |
11203 | 121 | let v1908 = C::output(ctx, v1907); |
11204 | 121 | // Rule at src/isa/x64/lower.isle line 3408. |
11205 | 121 | return Some(v1908); |
11206 | 0 | } |
11207 | | } |
11208 | | &Opcode::Urem => { |
11209 | 175 | let v38 = C::unpack_value_array_2(ctx, v37); |
11210 | 175 | let v1756 = C::value_type(ctx, v38.0); |
11211 | 175 | if v1756 == I8 { |
11212 | 0 | let v1881 = constructor_extend_to_gpr(ctx, v38.0, I32, &ExtendKind::Zero); |
11213 | 0 | let v177 = constructor_put_in_gpr(ctx, v38.1); |
11214 | 0 | let v1882 = &C::gpr_to_gpr_mem(ctx, v177); |
11215 | 0 | let v1885 = constructor_x64_div8(ctx, v1881, v1882, &DivSignedness::Unsigned, &TrapCode::IntegerDivisionByZero); |
11216 | 0 | let v968 = Imm8Reg::Imm8 { |
11217 | 0 | imm: 0x8, |
11218 | 0 | }; |
11219 | 0 | let v1909 = &C::imm8_reg_to_imm8_gpr(ctx, &v968); |
11220 | 0 | let v1910 = constructor_x64_shr(ctx, I64, v1885, v1909); |
11221 | 0 | let v1911 = constructor_output_gpr(ctx, v1910); |
11222 | 0 | // Rule at src/isa/x64/lower.isle line 3441. |
11223 | 0 | return Some(v1911); |
11224 | 175 | } |
11225 | 175 | let v1887 = C::fits_in_64(ctx, v1756); |
11226 | 175 | if let Some(v1888) = v1887 { |
11227 | 175 | let v41 = constructor_put_in_gpr(ctx, v38.0); |
11228 | 175 | let v15 = constructor_imm(ctx, I64, 0x0); |
11229 | 175 | let v1889 = C::gpr_new(ctx, v15); |
11230 | 175 | let v1890 = constructor_put_in_gpr(ctx, v38.1); |
11231 | 175 | let v1891 = &C::gpr_to_gpr_mem(ctx, v1890); |
11232 | 175 | let v1892 = &C::raw_operand_size_of_type(ctx, v1888); |
11233 | 175 | let v1912 = constructor_x64_div_remainder(ctx, v41, v1889, v1891, v1892, &DivSignedness::Unsigned, &TrapCode::IntegerDivisionByZero); |
11234 | 175 | let v1913 = C::output(ctx, v1912); |
11235 | 175 | // Rule at src/isa/x64/lower.isle line 3450. |
11236 | 175 | return Some(v1913); |
11237 | 0 | } |
11238 | | } |
11239 | | &Opcode::Srem => { |
11240 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11241 | 0 | let v154 = C::def_inst(ctx, v38.1); |
11242 | 0 | if let Some(v155) = v154 { |
11243 | 0 | let v156 = &C::inst_data(ctx, v155); |
11244 | | if let &InstructionData::UnaryImm { |
11245 | 0 | opcode: ref v1914, |
11246 | 0 | imm: v1915, |
11247 | 0 | } = v156 { |
11248 | 0 | if let &Opcode::Iconst = v1914 { |
11249 | 0 | let v1756 = C::value_type(ctx, v38.0); |
11250 | 0 | if v1756 == I8 { |
11251 | 0 | let v1916 = C::safe_divisor_from_imm64(ctx, I8, v1915); |
11252 | 0 | if let Some(v1917) = v1916 { |
11253 | 0 | let v41 = constructor_put_in_gpr(ctx, v38.0); |
11254 | 0 | let v1896 = constructor_x64_sign_extend_data(ctx, v41, &OperandSize::Size8); |
11255 | 0 | let v1918 = constructor_imm(ctx, I8, v1917); |
11256 | 0 | let v1919 = &C::reg_to_gpr_mem(ctx, v1918); |
11257 | 0 | let v1920 = constructor_x64_div8(ctx, v1896, v1919, &DivSignedness::Signed, &TrapCode::IntegerDivisionByZero); |
11258 | 0 | let v968 = Imm8Reg::Imm8 { |
11259 | 0 | imm: 0x8, |
11260 | 0 | }; |
11261 | 0 | let v1921 = &C::imm8_reg_to_imm8_gpr(ctx, &v968); |
11262 | 0 | let v1922 = constructor_x64_shr(ctx, I64, v1920, v1921); |
11263 | 0 | let v1923 = constructor_output_gpr(ctx, v1922); |
11264 | 0 | // Rule at src/isa/x64/lower.isle line 3465. |
11265 | 0 | return Some(v1923); |
11266 | 0 | } |
11267 | 0 | } |
11268 | 0 | let v1924 = C::safe_divisor_from_imm64(ctx, v1756, v1915); |
11269 | 0 | if let Some(v1925) = v1924 { |
11270 | 0 | let v41 = constructor_put_in_gpr(ctx, v38.0); |
11271 | 0 | let v1926 = &C::raw_operand_size_of_type(ctx, v1756); |
11272 | 0 | let v1927 = constructor_x64_sign_extend_data(ctx, v41, v1926); |
11273 | 0 | let v1928 = constructor_imm(ctx, v1756, v1925); |
11274 | 0 | let v1929 = &C::reg_to_gpr_mem(ctx, v1928); |
11275 | 0 | let v1930 = constructor_x64_div_remainder(ctx, v41, v1927, v1929, v1926, &DivSignedness::Signed, &TrapCode::IntegerDivisionByZero); |
11276 | 0 | let v1931 = C::output(ctx, v1930); |
11277 | 0 | // Rule at src/isa/x64/lower.isle line 3474. |
11278 | 0 | return Some(v1931); |
11279 | 0 | } |
11280 | 0 | } |
11281 | 0 | } |
11282 | 0 | } |
11283 | 0 | let v1756 = C::value_type(ctx, v38.0); |
11284 | 0 | if v1756 == I8 { |
11285 | 0 | let v41 = constructor_put_in_gpr(ctx, v38.0); |
11286 | 0 | let v1896 = constructor_x64_sign_extend_data(ctx, v41, &OperandSize::Size8); |
11287 | 0 | let v1932 = constructor_put_in_gpr(ctx, v38.1); |
11288 | 0 | let v1933 = constructor_x64_checked_srem_seq8(ctx, v1896, v1932); |
11289 | 0 | let v968 = Imm8Reg::Imm8 { |
11290 | 0 | imm: 0x8, |
11291 | 0 | }; |
11292 | 0 | let v1909 = &C::imm8_reg_to_imm8_gpr(ctx, &v968); |
11293 | 0 | let v1934 = constructor_x64_shr(ctx, I64, v1933, v1909); |
11294 | 0 | let v1935 = constructor_output_gpr(ctx, v1934); |
11295 | 0 | // Rule at src/isa/x64/lower.isle line 3487. |
11296 | 0 | return Some(v1935); |
11297 | 0 | } |
11298 | 0 | let v41 = constructor_put_in_gpr(ctx, v38.0); |
11299 | 0 | let v1926 = &C::raw_operand_size_of_type(ctx, v1756); |
11300 | 0 | let v1927 = constructor_x64_sign_extend_data(ctx, v41, v1926); |
11301 | 0 | let v1890 = constructor_put_in_gpr(ctx, v38.1); |
11302 | 0 | let v1936 = constructor_x64_checked_srem_seq(ctx, v1926, v41, v1927, v1890); |
11303 | 0 | let v1937 = C::value_regs_get(ctx, v1936, 0x1); |
11304 | 0 | let v1938 = constructor_output_reg(ctx, v1937); |
11305 | 0 | // Rule at src/isa/x64/lower.isle line 3493. |
11306 | 0 | return Some(v1938); |
11307 | | } |
11308 | | &Opcode::IaddCout => { |
11309 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11310 | 0 | let v92 = C::value_type(ctx, v38.1); |
11311 | 0 | let v93 = C::ty_32_or_64(ctx, v92); |
11312 | 0 | if let Some(v94) = v93 { |
11313 | 0 | let v41 = constructor_put_in_gpr(ctx, v38.0); |
11314 | 0 | let v42 = &constructor_put_in_gpr_mem_imm(ctx, v38.1); |
11315 | 0 | let v95 = &constructor_x64_add_with_flags_paired(ctx, v94, v41, v42); |
11316 | 0 | let v97 = &constructor_x64_setcc_paired(ctx, &CC::O); |
11317 | 0 | let v98 = constructor_with_flags(ctx, v95, v97); |
11318 | 0 | let v99 = C::value_regs_get(ctx, v98, 0x0); |
11319 | 0 | let v100 = C::value_reg(ctx, v99); |
11320 | 0 | let v101 = C::value_regs_get(ctx, v98, 0x1); |
11321 | 0 | let v102 = C::value_reg(ctx, v101); |
11322 | 0 | let v103 = C::output_pair(ctx, v100, v102); |
11323 | 0 | // Rule at src/isa/x64/lower.isle line 108. |
11324 | 0 | return Some(v103); |
11325 | 0 | } |
11326 | | } |
11327 | | &Opcode::Band => { |
11328 | 42.4k | let v1 = C::first_result(ctx, arg0); |
11329 | 42.4k | if let Some(v2) = v1 { |
11330 | 42.4k | let v3 = C::value_type(ctx, v2); |
11331 | 42.4k | let v134 = C::ty_int_ref_scalar_64(ctx, v3); |
11332 | 42.4k | if let Some(v135) = v134 { |
11333 | 42.4k | let v171 = C::use_bmi1(ctx, v3); |
11334 | 42.4k | if v171 == true { |
11335 | 42.4k | let v38 = C::unpack_value_array_2(ctx, v37); |
11336 | 42.4k | let v163 = C::def_inst(ctx, v38.0); |
11337 | 42.4k | if let Some(v16440.3k ) = v163 { |
11338 | 40.3k | let v165 = &C::inst_data(ctx, v164); |
11339 | | if let &InstructionData::Unary { |
11340 | 980 | opcode: ref v166, |
11341 | 980 | arg: v167, |
11342 | 40.3k | } = v165 { |
11343 | 980 | if let &Opcode::Bnot = v166 { |
11344 | 62 | let v176 = constructor_put_in_gpr(ctx, v167); |
11345 | 62 | let v177 = constructor_put_in_gpr(ctx, v38.1); |
11346 | 62 | let v178 = constructor_x64_andn(ctx, v3, v176, v177); |
11347 | 62 | let v179 = constructor_output_gpr(ctx, v178); |
11348 | 62 | // Rule at src/isa/x64/lower.isle line 270. |
11349 | 62 | return Some(v179); |
11350 | 918 | } |
11351 | 39.3k | } |
11352 | 2.12k | } |
11353 | 42.3k | let v154 = C::def_inst(ctx, v38.1); |
11354 | 42.3k | if let Some(v15542.3k ) = v154 { |
11355 | 42.3k | let v156 = &C::inst_data(ctx, v155); |
11356 | | if let &InstructionData::Unary { |
11357 | 864 | opcode: ref v157, |
11358 | 864 | arg: v158, |
11359 | 42.3k | } = v156 { |
11360 | 864 | if let &Opcode::Bnot = v157 { |
11361 | 87 | let v172 = constructor_put_in_gpr(ctx, v158); |
11362 | 87 | let v173 = constructor_put_in_gpr(ctx, v38.0); |
11363 | 87 | let v174 = constructor_x64_andn(ctx, v3, v172, v173); |
11364 | 87 | let v175 = constructor_output_gpr(ctx, v174); |
11365 | 87 | // Rule at src/isa/x64/lower.isle line 266. |
11366 | 87 | return Some(v175); |
11367 | 776 | } |
11368 | 41.4k | } |
11369 | 82 | } |
11370 | 1 | } |
11371 | 0 | } |
11372 | 42.3k | let v64 = C::multi_lane(ctx, v3); |
11373 | 42.3k | if let Some(v651 ) = v64 { |
11374 | 1 | let v38 = C::unpack_value_array_2(ctx, v37); |
11375 | 1 | let v163 = C::def_inst(ctx, v38.0); |
11376 | 1 | if let Some(v164) = v163 { |
11377 | 1 | let v165 = &C::inst_data(ctx, v164); |
11378 | | if let &InstructionData::Unary { |
11379 | 1 | opcode: ref v166, |
11380 | 1 | arg: v167, |
11381 | 1 | } = v165 { |
11382 | 1 | if let &Opcode::Bnot = v166 { |
11383 | 0 | let v168 = constructor_put_in_xmm(ctx, v167); |
11384 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
11385 | 0 | let v169 = constructor_sse_and_not(ctx, v3, v168, v69); |
11386 | 0 | let v170 = constructor_output_xmm(ctx, v169); |
11387 | 0 | // Rule at src/isa/x64/lower.isle line 263. |
11388 | 0 | return Some(v170); |
11389 | 0 | } |
11390 | 0 | } |
11391 | 0 | } |
11392 | 0 | let v154 = C::def_inst(ctx, v38.1); |
11393 | 0 | if let Some(v155) = v154 { |
11394 | 0 | let v156 = &C::inst_data(ctx, v155); |
11395 | | if let &InstructionData::Unary { |
11396 | 0 | opcode: ref v157, |
11397 | 0 | arg: v158, |
11398 | 0 | } = v156 { |
11399 | 0 | if let &Opcode::Bnot = v157 { |
11400 | 0 | let v159 = constructor_put_in_xmm(ctx, v158); |
11401 | 0 | let v160 = &C::put_in_xmm_mem(ctx, v38.0); |
11402 | 0 | let v161 = constructor_sse_and_not(ctx, v3, v159, v160); |
11403 | 0 | let v162 = constructor_output_xmm(ctx, v161); |
11404 | 0 | // Rule at src/isa/x64/lower.isle line 261. |
11405 | 0 | return Some(v162); |
11406 | 0 | } |
11407 | 0 | } |
11408 | 0 | } |
11409 | 42.2k | } |
11410 | 42.2k | if v3 == I128 { |
11411 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11412 | 0 | let v78 = C::put_in_regs(ctx, v38.0); |
11413 | 0 | let v80 = constructor_value_regs_get_gpr(ctx, v78, 0x0); |
11414 | 0 | let v82 = constructor_value_regs_get_gpr(ctx, v78, 0x1); |
11415 | 0 | let v83 = C::put_in_regs(ctx, v38.1); |
11416 | 0 | let v84 = constructor_value_regs_get_gpr(ctx, v83, 0x0); |
11417 | 0 | let v85 = constructor_value_regs_get_gpr(ctx, v83, 0x1); |
11418 | 0 | let v86 = &C::gpr_to_gpr_mem_imm(ctx, v84); |
11419 | 0 | let v150 = constructor_x64_and(ctx, I64, v80, v86); |
11420 | 0 | let v88 = &C::gpr_to_gpr_mem_imm(ctx, v85); |
11421 | 0 | let v151 = constructor_x64_and(ctx, I64, v82, v88); |
11422 | 0 | let v152 = constructor_value_gprs(ctx, v150, v151); |
11423 | 0 | let v153 = C::output(ctx, v152); |
11424 | 0 | // Rule at src/isa/x64/lower.isle line 235. |
11425 | 0 | return Some(v153); |
11426 | 42.2k | } |
11427 | 42.2k | if let Some(v650 ) = v64 { |
11428 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11429 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11430 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
11431 | 0 | let v148 = constructor_sse_and(ctx, v3, v68, v69); |
11432 | 0 | let v149 = constructor_output_xmm(ctx, v148); |
11433 | 0 | // Rule at src/isa/x64/lower.isle line 229. |
11434 | 0 | return Some(v149); |
11435 | 42.2k | } |
11436 | 42.2k | let v144 = C::ty_scalar_float(ctx, v3); |
11437 | 42.2k | if let Some(v1450 ) = v144 { |
11438 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11439 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11440 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
11441 | 0 | let v146 = constructor_sse_and(ctx, v145, v68, v69); |
11442 | 0 | let v147 = constructor_output_xmm(ctx, v146); |
11443 | 0 | // Rule at src/isa/x64/lower.isle line 217. |
11444 | 0 | return Some(v147); |
11445 | 42.2k | } |
11446 | 42.2k | if let Some(v135) = v134 { |
11447 | 42.2k | let v38 = C::unpack_value_array_2(ctx, v37); |
11448 | 42.2k | let v140 = &C::simm32_from_value(ctx, v38.0); |
11449 | 42.2k | if let Some(v1410 ) = v140 { |
11450 | 0 | let v60 = constructor_put_in_gpr(ctx, v38.1); |
11451 | 0 | let v142 = constructor_x64_and(ctx, v3, v60, v141); |
11452 | 0 | let v143 = constructor_output_gpr(ctx, v142); |
11453 | 0 | // Rule at src/isa/x64/lower.isle line 211. |
11454 | 0 | return Some(v143); |
11455 | 42.2k | } |
11456 | 42.2k | let v58 = &C::sinkable_load(ctx, v38.0); |
11457 | 42.2k | if let Some(v59656 ) = v58 { |
11458 | 656 | let v60 = constructor_put_in_gpr(ctx, v38.1); |
11459 | 656 | let v61 = &constructor_sink_load_to_gpr_mem_imm(ctx, v59); |
11460 | 656 | let v138 = constructor_x64_and(ctx, v3, v60, v61); |
11461 | 656 | let v139 = constructor_output_gpr(ctx, v138); |
11462 | 656 | // Rule at src/isa/x64/lower.isle line 207. |
11463 | 656 | return Some(v139); |
11464 | 41.6k | } |
11465 | 41.6k | let v41 = constructor_put_in_gpr(ctx, v38.0); |
11466 | 41.6k | let v42 = &constructor_put_in_gpr_mem_imm(ctx, v38.1); |
11467 | 41.6k | let v136 = constructor_x64_and(ctx, v3, v41, v42); |
11468 | 41.6k | let v137 = constructor_output_gpr(ctx, v136); |
11469 | 41.6k | // Rule at src/isa/x64/lower.isle line 200. |
11470 | 41.6k | return Some(v137); |
11471 | 0 | } |
11472 | 0 | } |
11473 | | } |
11474 | | &Opcode::Bor => { |
11475 | 7.66k | let v1 = C::first_result(ctx, arg0); |
11476 | 7.66k | if let Some(v2) = v1 { |
11477 | 7.66k | let v3 = C::value_type(ctx, v2); |
11478 | 7.66k | if v3 == I128 { |
11479 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11480 | 0 | let v78 = C::put_in_regs(ctx, v38.0); |
11481 | 0 | let v190 = C::put_in_regs(ctx, v38.1); |
11482 | 0 | let v191 = constructor_or_i128(ctx, v78, v190); |
11483 | 0 | let v192 = C::output(ctx, v191); |
11484 | 0 | // Rule at src/isa/x64/lower.isle line 324. |
11485 | 0 | return Some(v192); |
11486 | 7.66k | } |
11487 | 7.66k | let v64 = C::multi_lane(ctx, v3); |
11488 | 7.66k | if let Some(v650 ) = v64 { |
11489 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11490 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11491 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
11492 | 0 | let v188 = constructor_sse_or(ctx, v3, v68, v69); |
11493 | 0 | let v189 = constructor_output_xmm(ctx, v188); |
11494 | 0 | // Rule at src/isa/x64/lower.isle line 309. |
11495 | 0 | return Some(v189); |
11496 | 7.66k | } |
11497 | 7.66k | let v144 = C::ty_scalar_float(ctx, v3); |
11498 | 7.66k | if let Some(v1450 ) = v144 { |
11499 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11500 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11501 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
11502 | 0 | let v186 = constructor_sse_or(ctx, v145, v68, v69); |
11503 | 0 | let v187 = constructor_output_xmm(ctx, v186); |
11504 | 0 | // Rule at src/isa/x64/lower.isle line 297. |
11505 | 0 | return Some(v187); |
11506 | 7.66k | } |
11507 | 7.66k | let v134 = C::ty_int_ref_scalar_64(ctx, v3); |
11508 | 7.66k | if let Some(v135) = v134 { |
11509 | 7.66k | let v38 = C::unpack_value_array_2(ctx, v37); |
11510 | 7.66k | let v140 = &C::simm32_from_value(ctx, v38.0); |
11511 | 7.66k | if let Some(v1410 ) = v140 { |
11512 | 0 | let v60 = constructor_put_in_gpr(ctx, v38.1); |
11513 | 0 | let v184 = constructor_x64_or(ctx, v3, v60, v141); |
11514 | 0 | let v185 = constructor_output_gpr(ctx, v184); |
11515 | 0 | // Rule at src/isa/x64/lower.isle line 291. |
11516 | 0 | return Some(v185); |
11517 | 7.66k | } |
11518 | 7.66k | let v58 = &C::sinkable_load(ctx, v38.0); |
11519 | 7.66k | if let Some(v5911 ) = v58 { |
11520 | 11 | let v60 = constructor_put_in_gpr(ctx, v38.1); |
11521 | 11 | let v61 = &constructor_sink_load_to_gpr_mem_imm(ctx, v59); |
11522 | 11 | let v182 = constructor_x64_or(ctx, v3, v60, v61); |
11523 | 11 | let v183 = constructor_output_gpr(ctx, v182); |
11524 | 11 | // Rule at src/isa/x64/lower.isle line 287. |
11525 | 11 | return Some(v183); |
11526 | 7.65k | } |
11527 | 7.65k | let v41 = constructor_put_in_gpr(ctx, v38.0); |
11528 | 7.65k | let v42 = &constructor_put_in_gpr_mem_imm(ctx, v38.1); |
11529 | 7.65k | let v180 = constructor_x64_or(ctx, v3, v41, v42); |
11530 | 7.65k | let v181 = constructor_output_gpr(ctx, v180); |
11531 | 7.65k | // Rule at src/isa/x64/lower.isle line 280. |
11532 | 7.65k | return Some(v181); |
11533 | 0 | } |
11534 | 0 | } |
11535 | | } |
11536 | | &Opcode::Bxor => { |
11537 | 1.91k | let v1 = C::first_result(ctx, arg0); |
11538 | 1.91k | if let Some(v2) = v1 { |
11539 | 1.91k | let v3 = C::value_type(ctx, v2); |
11540 | 1.91k | if v3 == I128 { |
11541 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11542 | 0 | let v78 = C::put_in_regs(ctx, v38.0); |
11543 | 0 | let v80 = constructor_value_regs_get_gpr(ctx, v78, 0x0); |
11544 | 0 | let v82 = constructor_value_regs_get_gpr(ctx, v78, 0x1); |
11545 | 0 | let v83 = C::put_in_regs(ctx, v38.1); |
11546 | 0 | let v84 = constructor_value_regs_get_gpr(ctx, v83, 0x0); |
11547 | 0 | let v85 = constructor_value_regs_get_gpr(ctx, v83, 0x1); |
11548 | 0 | let v86 = &C::gpr_to_gpr_mem_imm(ctx, v84); |
11549 | 0 | let v203 = constructor_x64_xor(ctx, I64, v80, v86); |
11550 | 0 | let v88 = &C::gpr_to_gpr_mem_imm(ctx, v85); |
11551 | 0 | let v204 = constructor_x64_xor(ctx, I64, v82, v88); |
11552 | 0 | let v205 = constructor_value_gprs(ctx, v203, v204); |
11553 | 0 | let v206 = C::output(ctx, v205); |
11554 | 0 | // Rule at src/isa/x64/lower.isle line 359. |
11555 | 0 | return Some(v206); |
11556 | 1.91k | } |
11557 | 1.91k | let v64 = C::multi_lane(ctx, v3); |
11558 | 1.91k | if let Some(v650 ) = v64 { |
11559 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11560 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11561 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
11562 | 0 | let v201 = constructor_x64_xor_vector(ctx, v3, v68, v69); |
11563 | 0 | let v202 = constructor_output_xmm(ctx, v201); |
11564 | 0 | // Rule at src/isa/x64/lower.isle line 354. |
11565 | 0 | return Some(v202); |
11566 | 1.91k | } |
11567 | 1.91k | let v144 = C::ty_scalar_float(ctx, v3); |
11568 | 1.91k | if let Some(v1450 ) = v144 { |
11569 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11570 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11571 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
11572 | 0 | let v199 = constructor_x64_xor_vector(ctx, v145, v68, v69); |
11573 | 0 | let v200 = constructor_output_xmm(ctx, v199); |
11574 | 0 | // Rule at src/isa/x64/lower.isle line 349. |
11575 | 0 | return Some(v200); |
11576 | 1.91k | } |
11577 | 1.91k | let v134 = C::ty_int_ref_scalar_64(ctx, v3); |
11578 | 1.91k | if let Some(v135) = v134 { |
11579 | 1.91k | let v38 = C::unpack_value_array_2(ctx, v37); |
11580 | 1.91k | let v140 = &C::simm32_from_value(ctx, v38.0); |
11581 | 1.91k | if let Some(v1410 ) = v140 { |
11582 | 0 | let v60 = constructor_put_in_gpr(ctx, v38.1); |
11583 | 0 | let v197 = constructor_x64_xor(ctx, v3, v60, v141); |
11584 | 0 | let v198 = constructor_output_gpr(ctx, v197); |
11585 | 0 | // Rule at src/isa/x64/lower.isle line 343. |
11586 | 0 | return Some(v198); |
11587 | 1.91k | } |
11588 | 1.91k | let v58 = &C::sinkable_load(ctx, v38.0); |
11589 | 1.91k | if let Some(v592 ) = v58 { |
11590 | 2 | let v60 = constructor_put_in_gpr(ctx, v38.1); |
11591 | 2 | let v61 = &constructor_sink_load_to_gpr_mem_imm(ctx, v59); |
11592 | 2 | let v195 = constructor_x64_xor(ctx, v3, v60, v61); |
11593 | 2 | let v196 = constructor_output_gpr(ctx, v195); |
11594 | 2 | // Rule at src/isa/x64/lower.isle line 339. |
11595 | 2 | return Some(v196); |
11596 | 1.91k | } |
11597 | 1.91k | let v41 = constructor_put_in_gpr(ctx, v38.0); |
11598 | 1.91k | let v42 = &constructor_put_in_gpr_mem_imm(ctx, v38.1); |
11599 | 1.91k | let v193 = constructor_x64_xor(ctx, v3, v41, v42); |
11600 | 1.91k | let v194 = constructor_output_gpr(ctx, v193); |
11601 | 1.91k | // Rule at src/isa/x64/lower.isle line 332. |
11602 | 1.91k | return Some(v194); |
11603 | 0 | } |
11604 | 0 | } |
11605 | | } |
11606 | | &Opcode::Rotl => { |
11607 | 687 | let v1 = C::first_result(ctx, arg0); |
11608 | 687 | if let Some(v2) = v1 { |
11609 | 687 | let v3 = C::value_type(ctx, v2); |
11610 | 687 | if v3 == I128 { |
11611 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11612 | 0 | let v78 = C::put_in_regs(ctx, v38.0); |
11613 | 0 | let v284 = constructor_lo_gpr(ctx, v38.1); |
11614 | 0 | let v285 = constructor_shl_i128(ctx, v78, v284); |
11615 | 0 | let v287 = constructor_imm(ctx, I64, 0x80); |
11616 | 0 | let v288 = C::gpr_new(ctx, v287); |
11617 | 0 | let v289 = &C::gpr_to_gpr_mem_imm(ctx, v284); |
11618 | 0 | let v290 = constructor_x64_sub(ctx, I64, v288, v289); |
11619 | 0 | let v291 = constructor_shr_i128(ctx, v78, v290); |
11620 | 0 | let v292 = constructor_or_i128(ctx, v285, v291); |
11621 | 0 | let v293 = C::output(ctx, v292); |
11622 | 0 | // Rule at src/isa/x64/lower.isle line 716. |
11623 | 0 | return Some(v293); |
11624 | 687 | } |
11625 | 687 | let v4 = C::fits_in_64(ctx, v3); |
11626 | 687 | if let Some(v5) = v4 { |
11627 | 687 | let v38 = C::unpack_value_array_2(ctx, v37); |
11628 | 687 | let v41 = constructor_put_in_gpr(ctx, v38.0); |
11629 | 687 | let v207 = &constructor_put_masked_in_imm8_gpr(ctx, v38.1, v5); |
11630 | 687 | let v282 = constructor_x64_rotl(ctx, v5, v41, v207); |
11631 | 687 | let v283 = constructor_output_gpr(ctx, v282); |
11632 | 687 | // Rule at src/isa/x64/lower.isle line 710. |
11633 | 687 | return Some(v283); |
11634 | 0 | } |
11635 | 0 | } |
11636 | | } |
11637 | | &Opcode::Rotr => { |
11638 | 1 | let v1 = C::first_result(ctx, arg0); |
11639 | 1 | if let Some(v2) = v1 { |
11640 | 1 | let v3 = C::value_type(ctx, v2); |
11641 | 1 | if v3 == I128 { |
11642 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11643 | 0 | let v78 = C::put_in_regs(ctx, v38.0); |
11644 | 0 | let v284 = constructor_lo_gpr(ctx, v38.1); |
11645 | 0 | let v296 = constructor_shr_i128(ctx, v78, v284); |
11646 | 0 | let v287 = constructor_imm(ctx, I64, 0x80); |
11647 | 0 | let v288 = C::gpr_new(ctx, v287); |
11648 | 0 | let v289 = &C::gpr_to_gpr_mem_imm(ctx, v284); |
11649 | 0 | let v290 = constructor_x64_sub(ctx, I64, v288, v289); |
11650 | 0 | let v297 = constructor_shl_i128(ctx, v78, v290); |
11651 | 0 | let v298 = constructor_or_i128(ctx, v296, v297); |
11652 | 0 | let v299 = C::output(ctx, v298); |
11653 | 0 | // Rule at src/isa/x64/lower.isle line 737. |
11654 | 0 | return Some(v299); |
11655 | 1 | } |
11656 | 1 | let v4 = C::fits_in_64(ctx, v3); |
11657 | 1 | if let Some(v5) = v4 { |
11658 | 1 | let v38 = C::unpack_value_array_2(ctx, v37); |
11659 | 1 | let v41 = constructor_put_in_gpr(ctx, v38.0); |
11660 | 1 | let v207 = &constructor_put_masked_in_imm8_gpr(ctx, v38.1, v5); |
11661 | 1 | let v294 = constructor_x64_rotr(ctx, v5, v41, v207); |
11662 | 1 | let v295 = constructor_output_gpr(ctx, v294); |
11663 | 1 | // Rule at src/isa/x64/lower.isle line 731. |
11664 | 1 | return Some(v295); |
11665 | 0 | } |
11666 | 0 | } |
11667 | | } |
11668 | | &Opcode::Ishl => { |
11669 | 8.29k | let v1 = C::first_result(ctx, arg0); |
11670 | 8.29k | if let Some(v2) = v1 { |
11671 | 8.29k | let v3 = C::value_type(ctx, v2); |
11672 | 8.29k | match v3 { |
11673 | | I128 => { |
11674 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11675 | 0 | let v210 = constructor_lo_gpr(ctx, v38.1); |
11676 | 0 | let v211 = C::put_in_regs(ctx, v38.0); |
11677 | 0 | let v212 = constructor_shl_i128(ctx, v211, v210); |
11678 | 0 | let v213 = C::output(ctx, v212); |
11679 | 0 | // Rule at src/isa/x64/lower.isle line 412. |
11680 | 0 | return Some(v213); |
11681 | | } |
11682 | | I8X16 => { |
11683 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11684 | 0 | let v214 = &constructor_mask_xmm_shift(ctx, v3, v38.1); |
11685 | 0 | let v215 = constructor_put_in_xmm(ctx, v38.0); |
11686 | 0 | let v216 = &constructor_mov_rmi_to_xmm(ctx, v214); |
11687 | 0 | let v217 = constructor_x64_psllw(ctx, v215, v216); |
11688 | 0 | let v218 = &constructor_ishl_i8x16_mask(ctx, v214); |
11689 | 0 | let v221 = constructor_x64_load(ctx, I8X16, v218, &ExtKind::None); |
11690 | 0 | let v222 = RegMem::Reg { |
11691 | 0 | reg: v221, |
11692 | 0 | }; |
11693 | 0 | let v223 = &C::reg_mem_to_xmm_mem(ctx, &v222); |
11694 | 0 | let v224 = constructor_sse_and(ctx, I8X16, v217, v223); |
11695 | 0 | let v225 = constructor_output_xmm(ctx, v224); |
11696 | 0 | // Rule at src/isa/x64/lower.isle line 424. |
11697 | 0 | return Some(v225); |
11698 | | } |
11699 | | I16X8 => { |
11700 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11701 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11702 | 0 | let v226 = &constructor_mask_xmm_shift(ctx, v3, v38.1); |
11703 | 0 | let v227 = &constructor_mov_rmi_to_xmm(ctx, v226); |
11704 | 0 | let v228 = constructor_x64_psllw(ctx, v68, v227); |
11705 | 0 | let v229 = constructor_output_xmm(ctx, v228); |
11706 | 0 | // Rule at src/isa/x64/lower.isle line 469. |
11707 | 0 | return Some(v229); |
11708 | | } |
11709 | | I32X4 => { |
11710 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11711 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11712 | 0 | let v226 = &constructor_mask_xmm_shift(ctx, v3, v38.1); |
11713 | 0 | let v227 = &constructor_mov_rmi_to_xmm(ctx, v226); |
11714 | 0 | let v230 = constructor_x64_pslld(ctx, v68, v227); |
11715 | 0 | let v231 = constructor_output_xmm(ctx, v230); |
11716 | 0 | // Rule at src/isa/x64/lower.isle line 472. |
11717 | 0 | return Some(v231); |
11718 | | } |
11719 | | I64X2 => { |
11720 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11721 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11722 | 0 | let v226 = &constructor_mask_xmm_shift(ctx, v3, v38.1); |
11723 | 0 | let v227 = &constructor_mov_rmi_to_xmm(ctx, v226); |
11724 | 0 | let v232 = constructor_x64_psllq(ctx, v68, v227); |
11725 | 0 | let v233 = constructor_output_xmm(ctx, v232); |
11726 | 0 | // Rule at src/isa/x64/lower.isle line 475. |
11727 | 0 | return Some(v233); |
11728 | | } |
11729 | 8.29k | _ => {} |
11730 | 8.29k | } |
11731 | 8.29k | let v4 = C::fits_in_64(ctx, v3); |
11732 | 8.29k | if let Some(v5) = v4 { |
11733 | 8.29k | let v38 = C::unpack_value_array_2(ctx, v37); |
11734 | 8.29k | let v41 = constructor_put_in_gpr(ctx, v38.0); |
11735 | 8.29k | let v207 = &constructor_put_masked_in_imm8_gpr(ctx, v38.1, v5); |
11736 | 8.29k | let v208 = constructor_x64_shl(ctx, v5, v41, v207); |
11737 | 8.29k | let v209 = constructor_output_gpr(ctx, v208); |
11738 | 8.29k | // Rule at src/isa/x64/lower.isle line 373. |
11739 | 8.29k | return Some(v209); |
11740 | 0 | } |
11741 | 0 | } |
11742 | | } |
11743 | | &Opcode::Ushr => { |
11744 | 6.64k | let v1 = C::first_result(ctx, arg0); |
11745 | 6.64k | if let Some(v2) = v1 { |
11746 | 6.64k | let v3 = C::value_type(ctx, v2); |
11747 | 6.64k | match v3 { |
11748 | | I128 => { |
11749 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11750 | 0 | let v210 = constructor_lo_gpr(ctx, v38.1); |
11751 | 0 | let v211 = C::put_in_regs(ctx, v38.0); |
11752 | 0 | let v238 = constructor_shr_i128(ctx, v211, v210); |
11753 | 0 | let v239 = C::output(ctx, v238); |
11754 | 0 | // Rule at src/isa/x64/lower.isle line 519. |
11755 | 0 | return Some(v239); |
11756 | | } |
11757 | | I8X16 => { |
11758 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11759 | 0 | let v214 = &constructor_mask_xmm_shift(ctx, v3, v38.1); |
11760 | 0 | let v215 = constructor_put_in_xmm(ctx, v38.0); |
11761 | 0 | let v216 = &constructor_mov_rmi_to_xmm(ctx, v214); |
11762 | 0 | let v240 = constructor_x64_psrlw(ctx, v215, v216); |
11763 | 0 | let v241 = &constructor_ushr_i8x16_mask(ctx, v214); |
11764 | 0 | let v242 = &constructor_synthetic_amode_to_xmm_mem(ctx, v241); |
11765 | 0 | let v243 = constructor_sse_and(ctx, I8X16, v240, v242); |
11766 | 0 | let v244 = constructor_output_xmm(ctx, v243); |
11767 | 0 | // Rule at src/isa/x64/lower.isle line 529. |
11768 | 0 | return Some(v244); |
11769 | | } |
11770 | | I16X8 => { |
11771 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11772 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11773 | 0 | let v226 = &constructor_mask_xmm_shift(ctx, v3, v38.1); |
11774 | 0 | let v227 = &constructor_mov_rmi_to_xmm(ctx, v226); |
11775 | 0 | let v245 = constructor_x64_psrlw(ctx, v68, v227); |
11776 | 0 | let v246 = constructor_output_xmm(ctx, v245); |
11777 | 0 | // Rule at src/isa/x64/lower.isle line 575. |
11778 | 0 | return Some(v246); |
11779 | | } |
11780 | | I32X4 => { |
11781 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11782 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11783 | 0 | let v226 = &constructor_mask_xmm_shift(ctx, v3, v38.1); |
11784 | 0 | let v227 = &constructor_mov_rmi_to_xmm(ctx, v226); |
11785 | 0 | let v247 = constructor_x64_psrld(ctx, v68, v227); |
11786 | 0 | let v248 = constructor_output_xmm(ctx, v247); |
11787 | 0 | // Rule at src/isa/x64/lower.isle line 578. |
11788 | 0 | return Some(v248); |
11789 | | } |
11790 | | I64X2 => { |
11791 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11792 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11793 | 0 | let v226 = &constructor_mask_xmm_shift(ctx, v3, v38.1); |
11794 | 0 | let v227 = &constructor_mov_rmi_to_xmm(ctx, v226); |
11795 | 0 | let v249 = constructor_x64_psrlq(ctx, v68, v227); |
11796 | 0 | let v250 = constructor_output_xmm(ctx, v249); |
11797 | 0 | // Rule at src/isa/x64/lower.isle line 581. |
11798 | 0 | return Some(v250); |
11799 | | } |
11800 | 6.64k | _ => {} |
11801 | 6.64k | } |
11802 | 6.64k | let v4 = C::fits_in_64(ctx, v3); |
11803 | 6.64k | if let Some(v5) = v4 { |
11804 | 6.64k | let v38 = C::unpack_value_array_2(ctx, v37); |
11805 | 6.64k | let v235 = constructor_extend_to_gpr(ctx, v38.0, v5, &ExtendKind::Zero); |
11806 | 6.64k | let v207 = &constructor_put_masked_in_imm8_gpr(ctx, v38.1, v5); |
11807 | 6.64k | let v236 = constructor_x64_shr(ctx, v5, v235, v207); |
11808 | 6.64k | let v237 = constructor_output_gpr(ctx, v236); |
11809 | 6.64k | // Rule at src/isa/x64/lower.isle line 482. |
11810 | 6.64k | return Some(v237); |
11811 | 0 | } |
11812 | 0 | } |
11813 | | } |
11814 | | &Opcode::Sshr => { |
11815 | 143 | let v1 = C::first_result(ctx, arg0); |
11816 | 143 | if let Some(v2) = v1 { |
11817 | 143 | let v3 = C::value_type(ctx, v2); |
11818 | 143 | match v3 { |
11819 | | I128 => { |
11820 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11821 | 0 | let v210 = constructor_lo_gpr(ctx, v38.1); |
11822 | 0 | let v211 = C::put_in_regs(ctx, v38.0); |
11823 | 0 | let v255 = constructor_sar_i128(ctx, v211, v210); |
11824 | 0 | let v256 = C::output(ctx, v255); |
11825 | 0 | // Rule at src/isa/x64/lower.isle line 631. |
11826 | 0 | return Some(v256); |
11827 | | } |
11828 | | I8X16 => { |
11829 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11830 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11831 | 0 | let v226 = &constructor_mask_xmm_shift(ctx, v3, v38.1); |
11832 | 0 | let v257 = &C::xmm_to_xmm_mem(ctx, v68); |
11833 | 0 | let v258 = constructor_x64_punpcklbw(ctx, v68, v257); |
11834 | 0 | let v259 = &C::xmm_to_xmm_mem(ctx, v68); |
11835 | 0 | let v260 = constructor_x64_punpckhbw(ctx, v68, v259); |
11836 | 0 | let v92 = C::value_type(ctx, v38.1); |
11837 | 0 | let v261 = &constructor_sshr_i8x16_bigger_shift(ctx, v92, v226); |
11838 | 0 | let v262 = constructor_x64_psraw(ctx, v258, v261); |
11839 | 0 | let v263 = constructor_x64_psraw(ctx, v260, v261); |
11840 | 0 | let v264 = &C::xmm_to_xmm_mem(ctx, v263); |
11841 | 0 | let v265 = constructor_x64_packsswb(ctx, v262, v264); |
11842 | 0 | let v266 = constructor_output_xmm(ctx, v265); |
11843 | 0 | // Rule at src/isa/x64/lower.isle line 652. |
11844 | 0 | return Some(v266); |
11845 | | } |
11846 | | I16X8 => { |
11847 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11848 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11849 | 0 | let v226 = &constructor_mask_xmm_shift(ctx, v3, v38.1); |
11850 | 0 | let v227 = &constructor_mov_rmi_to_xmm(ctx, v226); |
11851 | 0 | let v267 = constructor_x64_psraw(ctx, v68, v227); |
11852 | 0 | let v268 = constructor_output_xmm(ctx, v267); |
11853 | 0 | // Rule at src/isa/x64/lower.isle line 681. |
11854 | 0 | return Some(v268); |
11855 | | } |
11856 | | I32X4 => { |
11857 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11858 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11859 | 0 | let v226 = &constructor_mask_xmm_shift(ctx, v3, v38.1); |
11860 | 0 | let v227 = &constructor_mov_rmi_to_xmm(ctx, v226); |
11861 | 0 | let v269 = constructor_x64_psrad(ctx, v68, v227); |
11862 | 0 | let v270 = constructor_output_xmm(ctx, v269); |
11863 | 0 | // Rule at src/isa/x64/lower.isle line 684. |
11864 | 0 | return Some(v270); |
11865 | | } |
11866 | | I64X2 => { |
11867 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11868 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11869 | 0 | let v272 = constructor_x64_pextrq(ctx, v68, 0x0); |
11870 | 0 | let v274 = constructor_x64_pextrq(ctx, v68, 0x1); |
11871 | 0 | let v275 = &constructor_put_masked_in_imm8_gpr(ctx, v38.1, I64); |
11872 | 0 | let v276 = constructor_x64_sar(ctx, I64, v272, v275); |
11873 | 0 | let v277 = constructor_x64_sar(ctx, I64, v274, v275); |
11874 | 0 | let v278 = &C::gpr_to_gpr_mem(ctx, v276); |
11875 | 0 | let v279 = &C::gpr_to_gpr_mem(ctx, v277); |
11876 | 0 | let v280 = constructor_make_i64x2_from_lanes(ctx, v278, v279); |
11877 | 0 | let v281 = constructor_output_xmm(ctx, v280); |
11878 | 0 | // Rule at src/isa/x64/lower.isle line 695. |
11879 | 0 | return Some(v281); |
11880 | | } |
11881 | 143 | _ => {} |
11882 | 143 | } |
11883 | 143 | let v4 = C::fits_in_64(ctx, v3); |
11884 | 143 | if let Some(v5) = v4 { |
11885 | 143 | let v38 = C::unpack_value_array_2(ctx, v37); |
11886 | 143 | let v252 = constructor_extend_to_gpr(ctx, v38.0, v5, &ExtendKind::Sign); |
11887 | 143 | let v207 = &constructor_put_masked_in_imm8_gpr(ctx, v38.1, v5); |
11888 | 143 | let v253 = constructor_x64_sar(ctx, v5, v252, v207); |
11889 | 143 | let v254 = constructor_output_gpr(ctx, v253); |
11890 | 143 | // Rule at src/isa/x64/lower.isle line 594. |
11891 | 143 | return Some(v254); |
11892 | 0 | } |
11893 | 0 | } |
11894 | | } |
11895 | | &Opcode::Fadd => { |
11896 | 0 | let v1 = C::first_result(ctx, arg0); |
11897 | 0 | if let Some(v2) = v1 { |
11898 | 0 | let v3 = C::value_type(ctx, v2); |
11899 | 0 | match v3 { |
11900 | | F32 => { |
11901 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11902 | 0 | let v58 = &C::sinkable_load(ctx, v38.0); |
11903 | 0 | if let Some(v59) = v58 { |
11904 | 0 | let v1013 = constructor_put_in_xmm(ctx, v38.1); |
11905 | 0 | let v1024 = &constructor_sink_load_to_xmm_mem(ctx, v59); |
11906 | 0 | let v1025 = constructor_x64_addss(ctx, v1013, v1024); |
11907 | 0 | let v1026 = constructor_output_xmm(ctx, v1025); |
11908 | 0 | // Rule at src/isa/x64/lower.isle line 2041. |
11909 | 0 | return Some(v1026); |
11910 | 0 | } |
11911 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11912 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
11913 | 0 | let v1016 = constructor_x64_addss(ctx, v68, v69); |
11914 | 0 | let v1017 = constructor_output_xmm(ctx, v1016); |
11915 | 0 | // Rule at src/isa/x64/lower.isle line 2030. |
11916 | 0 | return Some(v1017); |
11917 | | } |
11918 | | F64 => { |
11919 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11920 | 0 | let v58 = &C::sinkable_load(ctx, v38.0); |
11921 | 0 | if let Some(v59) = v58 { |
11922 | 0 | let v1013 = constructor_put_in_xmm(ctx, v38.1); |
11923 | 0 | let v1024 = &constructor_sink_load_to_xmm_mem(ctx, v59); |
11924 | 0 | let v1027 = constructor_x64_addsd(ctx, v1013, v1024); |
11925 | 0 | let v1028 = constructor_output_xmm(ctx, v1027); |
11926 | 0 | // Rule at src/isa/x64/lower.isle line 2043. |
11927 | 0 | return Some(v1028); |
11928 | 0 | } |
11929 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11930 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
11931 | 0 | let v1018 = constructor_x64_addsd(ctx, v68, v69); |
11932 | 0 | let v1019 = constructor_output_xmm(ctx, v1018); |
11933 | 0 | // Rule at src/isa/x64/lower.isle line 2032. |
11934 | 0 | return Some(v1019); |
11935 | | } |
11936 | | F32X4 => { |
11937 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11938 | 0 | let v58 = &C::sinkable_load(ctx, v38.0); |
11939 | 0 | if let Some(v59) = v58 { |
11940 | 0 | let v1013 = constructor_put_in_xmm(ctx, v38.1); |
11941 | 0 | let v1024 = &constructor_sink_load_to_xmm_mem(ctx, v59); |
11942 | 0 | let v1029 = constructor_x64_addps(ctx, v1013, v1024); |
11943 | 0 | let v1030 = constructor_output_xmm(ctx, v1029); |
11944 | 0 | // Rule at src/isa/x64/lower.isle line 2045. |
11945 | 0 | return Some(v1030); |
11946 | 0 | } |
11947 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11948 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
11949 | 0 | let v1020 = constructor_x64_addps(ctx, v68, v69); |
11950 | 0 | let v1021 = constructor_output_xmm(ctx, v1020); |
11951 | 0 | // Rule at src/isa/x64/lower.isle line 2034. |
11952 | 0 | return Some(v1021); |
11953 | | } |
11954 | | F64X2 => { |
11955 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11956 | 0 | let v58 = &C::sinkable_load(ctx, v38.0); |
11957 | 0 | if let Some(v59) = v58 { |
11958 | 0 | let v1013 = constructor_put_in_xmm(ctx, v38.1); |
11959 | 0 | let v1024 = &constructor_sink_load_to_xmm_mem(ctx, v59); |
11960 | 0 | let v1031 = constructor_x64_addpd(ctx, v1013, v1024); |
11961 | 0 | let v1032 = constructor_output_xmm(ctx, v1031); |
11962 | 0 | // Rule at src/isa/x64/lower.isle line 2047. |
11963 | 0 | return Some(v1032); |
11964 | 0 | } |
11965 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11966 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
11967 | 0 | let v1022 = constructor_x64_addpd(ctx, v68, v69); |
11968 | 0 | let v1023 = constructor_output_xmm(ctx, v1022); |
11969 | 0 | // Rule at src/isa/x64/lower.isle line 2036. |
11970 | 0 | return Some(v1023); |
11971 | | } |
11972 | 0 | _ => {} |
11973 | | } |
11974 | 0 | } |
11975 | | } |
11976 | | &Opcode::Fsub => { |
11977 | 0 | let v1 = C::first_result(ctx, arg0); |
11978 | 0 | if let Some(v2) = v1 { |
11979 | 0 | let v3 = C::value_type(ctx, v2); |
11980 | 0 | match v3 { |
11981 | | F32 => { |
11982 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11983 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11984 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
11985 | 0 | let v1033 = constructor_x64_subss(ctx, v68, v69); |
11986 | 0 | let v1034 = constructor_output_xmm(ctx, v1033); |
11987 | 0 | // Rule at src/isa/x64/lower.isle line 2052. |
11988 | 0 | return Some(v1034); |
11989 | | } |
11990 | | F64 => { |
11991 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
11992 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
11993 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
11994 | 0 | let v1035 = constructor_x64_subsd(ctx, v68, v69); |
11995 | 0 | let v1036 = constructor_output_xmm(ctx, v1035); |
11996 | 0 | // Rule at src/isa/x64/lower.isle line 2054. |
11997 | 0 | return Some(v1036); |
11998 | | } |
11999 | | F32X4 => { |
12000 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12001 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
12002 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
12003 | 0 | let v1037 = constructor_x64_subps(ctx, v68, v69); |
12004 | 0 | let v1038 = constructor_output_xmm(ctx, v1037); |
12005 | 0 | // Rule at src/isa/x64/lower.isle line 2056. |
12006 | 0 | return Some(v1038); |
12007 | | } |
12008 | | F64X2 => { |
12009 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12010 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
12011 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
12012 | 0 | let v1039 = constructor_x64_subpd(ctx, v68, v69); |
12013 | 0 | let v1040 = constructor_output_xmm(ctx, v1039); |
12014 | 0 | // Rule at src/isa/x64/lower.isle line 2058. |
12015 | 0 | return Some(v1040); |
12016 | | } |
12017 | 0 | _ => {} |
12018 | | } |
12019 | 0 | } |
12020 | | } |
12021 | | &Opcode::Fmul => { |
12022 | 0 | let v1 = C::first_result(ctx, arg0); |
12023 | 0 | if let Some(v2) = v1 { |
12024 | 0 | let v3 = C::value_type(ctx, v2); |
12025 | 0 | match v3 { |
12026 | | F32 => { |
12027 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12028 | 0 | let v58 = &C::sinkable_load(ctx, v38.0); |
12029 | 0 | if let Some(v59) = v58 { |
12030 | 0 | let v1013 = constructor_put_in_xmm(ctx, v38.1); |
12031 | 0 | let v1024 = &constructor_sink_load_to_xmm_mem(ctx, v59); |
12032 | 0 | let v1049 = constructor_x64_mulss(ctx, v1013, v1024); |
12033 | 0 | let v1050 = constructor_output_xmm(ctx, v1049); |
12034 | 0 | // Rule at src/isa/x64/lower.isle line 2074. |
12035 | 0 | return Some(v1050); |
12036 | 0 | } |
12037 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
12038 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
12039 | 0 | let v1041 = constructor_x64_mulss(ctx, v68, v69); |
12040 | 0 | let v1042 = constructor_output_xmm(ctx, v1041); |
12041 | 0 | // Rule at src/isa/x64/lower.isle line 2063. |
12042 | 0 | return Some(v1042); |
12043 | | } |
12044 | | F64 => { |
12045 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12046 | 0 | let v58 = &C::sinkable_load(ctx, v38.0); |
12047 | 0 | if let Some(v59) = v58 { |
12048 | 0 | let v1013 = constructor_put_in_xmm(ctx, v38.1); |
12049 | 0 | let v1024 = &constructor_sink_load_to_xmm_mem(ctx, v59); |
12050 | 0 | let v1051 = constructor_x64_mulsd(ctx, v1013, v1024); |
12051 | 0 | let v1052 = constructor_output_xmm(ctx, v1051); |
12052 | 0 | // Rule at src/isa/x64/lower.isle line 2076. |
12053 | 0 | return Some(v1052); |
12054 | 0 | } |
12055 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
12056 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
12057 | 0 | let v1043 = constructor_x64_mulsd(ctx, v68, v69); |
12058 | 0 | let v1044 = constructor_output_xmm(ctx, v1043); |
12059 | 0 | // Rule at src/isa/x64/lower.isle line 2065. |
12060 | 0 | return Some(v1044); |
12061 | | } |
12062 | | F32X4 => { |
12063 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12064 | 0 | let v58 = &C::sinkable_load(ctx, v38.0); |
12065 | 0 | if let Some(v59) = v58 { |
12066 | 0 | let v1013 = constructor_put_in_xmm(ctx, v38.1); |
12067 | 0 | let v1024 = &constructor_sink_load_to_xmm_mem(ctx, v59); |
12068 | 0 | let v1053 = constructor_x64_mulps(ctx, v1013, v1024); |
12069 | 0 | let v1054 = constructor_output_xmm(ctx, v1053); |
12070 | 0 | // Rule at src/isa/x64/lower.isle line 2078. |
12071 | 0 | return Some(v1054); |
12072 | 0 | } |
12073 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
12074 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
12075 | 0 | let v1045 = constructor_x64_mulps(ctx, v68, v69); |
12076 | 0 | let v1046 = constructor_output_xmm(ctx, v1045); |
12077 | 0 | // Rule at src/isa/x64/lower.isle line 2067. |
12078 | 0 | return Some(v1046); |
12079 | | } |
12080 | | F64X2 => { |
12081 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12082 | 0 | let v58 = &C::sinkable_load(ctx, v38.0); |
12083 | 0 | if let Some(v59) = v58 { |
12084 | 0 | let v1013 = constructor_put_in_xmm(ctx, v38.1); |
12085 | 0 | let v1024 = &constructor_sink_load_to_xmm_mem(ctx, v59); |
12086 | 0 | let v1055 = constructor_x64_mulpd(ctx, v1013, v1024); |
12087 | 0 | let v1056 = constructor_output_xmm(ctx, v1055); |
12088 | 0 | // Rule at src/isa/x64/lower.isle line 2080. |
12089 | 0 | return Some(v1056); |
12090 | 0 | } |
12091 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
12092 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
12093 | 0 | let v1047 = constructor_x64_mulpd(ctx, v68, v69); |
12094 | 0 | let v1048 = constructor_output_xmm(ctx, v1047); |
12095 | 0 | // Rule at src/isa/x64/lower.isle line 2069. |
12096 | 0 | return Some(v1048); |
12097 | | } |
12098 | 0 | _ => {} |
12099 | | } |
12100 | 0 | } |
12101 | | } |
12102 | | &Opcode::Fdiv => { |
12103 | 0 | let v1 = C::first_result(ctx, arg0); |
12104 | 0 | if let Some(v2) = v1 { |
12105 | 0 | let v3 = C::value_type(ctx, v2); |
12106 | 0 | match v3 { |
12107 | | F32 => { |
12108 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12109 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
12110 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
12111 | 0 | let v1057 = constructor_x64_divss(ctx, v68, v69); |
12112 | 0 | let v1058 = constructor_output_xmm(ctx, v1057); |
12113 | 0 | // Rule at src/isa/x64/lower.isle line 2085. |
12114 | 0 | return Some(v1058); |
12115 | | } |
12116 | | F64 => { |
12117 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12118 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
12119 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
12120 | 0 | let v1059 = constructor_x64_divsd(ctx, v68, v69); |
12121 | 0 | let v1060 = constructor_output_xmm(ctx, v1059); |
12122 | 0 | // Rule at src/isa/x64/lower.isle line 2087. |
12123 | 0 | return Some(v1060); |
12124 | | } |
12125 | | F32X4 => { |
12126 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12127 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
12128 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
12129 | 0 | let v1061 = constructor_x64_divps(ctx, v68, v69); |
12130 | 0 | let v1062 = constructor_output_xmm(ctx, v1061); |
12131 | 0 | // Rule at src/isa/x64/lower.isle line 2089. |
12132 | 0 | return Some(v1062); |
12133 | | } |
12134 | | F64X2 => { |
12135 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12136 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
12137 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
12138 | 0 | let v1063 = constructor_x64_divpd(ctx, v68, v69); |
12139 | 0 | let v1064 = constructor_output_xmm(ctx, v1063); |
12140 | 0 | // Rule at src/isa/x64/lower.isle line 2091. |
12141 | 0 | return Some(v1064); |
12142 | | } |
12143 | 0 | _ => {} |
12144 | | } |
12145 | 0 | } |
12146 | | } |
12147 | | &Opcode::Fcopysign => { |
12148 | 0 | let v1 = C::first_result(ctx, arg0); |
12149 | 0 | if let Some(v2) = v1 { |
12150 | 0 | let v3 = C::value_type(ctx, v2); |
12151 | 0 | match v3 { |
12152 | | F32 => { |
12153 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12154 | 0 | let v1756 = C::value_type(ctx, v38.0); |
12155 | 0 | if v1756 == F32 { |
12156 | 0 | let v1798 = constructor_imm(ctx, F32, 0x80000000); |
12157 | 0 | let v1799 = C::xmm_new(ctx, v1798); |
12158 | 0 | let v1800 = &C::put_in_xmm_mem(ctx, v38.0); |
12159 | 0 | let v1801 = constructor_x64_andnps(ctx, v1799, v1800); |
12160 | 0 | let v1802 = &C::put_in_xmm_mem(ctx, v38.1); |
12161 | 0 | let v1803 = constructor_x64_andps(ctx, v1799, v1802); |
12162 | 0 | let v1804 = &C::xmm_to_xmm_mem(ctx, v1803); |
12163 | 0 | let v1805 = constructor_x64_orps(ctx, v1801, v1804); |
12164 | 0 | let v1806 = constructor_output_xmm(ctx, v1805); |
12165 | 0 | // Rule at src/isa/x64/lower.isle line 3275. |
12166 | 0 | return Some(v1806); |
12167 | 0 | } |
12168 | | } |
12169 | | F64 => { |
12170 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12171 | 0 | let v1756 = C::value_type(ctx, v38.0); |
12172 | 0 | if v1756 == F64 { |
12173 | 0 | let v1807 = constructor_imm(ctx, F64, 0x8000000000000000); |
12174 | 0 | let v1808 = C::xmm_new(ctx, v1807); |
12175 | 0 | let v1800 = &C::put_in_xmm_mem(ctx, v38.0); |
12176 | 0 | let v1809 = constructor_x64_andnpd(ctx, v1808, v1800); |
12177 | 0 | let v1802 = &C::put_in_xmm_mem(ctx, v38.1); |
12178 | 0 | let v1810 = constructor_x64_andpd(ctx, v1808, v1802); |
12179 | 0 | let v1811 = &C::xmm_to_xmm_mem(ctx, v1810); |
12180 | 0 | let v1812 = constructor_x64_orpd(ctx, v1809, v1811); |
12181 | 0 | let v1813 = constructor_output_xmm(ctx, v1812); |
12182 | 0 | // Rule at src/isa/x64/lower.isle line 3281. |
12183 | 0 | return Some(v1813); |
12184 | 0 | } |
12185 | | } |
12186 | 0 | _ => {} |
12187 | | } |
12188 | 0 | } |
12189 | | } |
12190 | | &Opcode::Fmin => { |
12191 | 0 | let v1 = C::first_result(ctx, arg0); |
12192 | 0 | if let Some(v2) = v1 { |
12193 | 0 | let v3 = C::value_type(ctx, v2); |
12194 | 0 | match v3 { |
12195 | | F32 => { |
12196 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12197 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
12198 | 0 | let v366 = constructor_put_in_xmm(ctx, v38.1); |
12199 | 0 | let v1083 = constructor_xmm_min_max_seq(ctx, F32, true, v68, v366); |
12200 | 0 | let v1084 = constructor_output_xmm(ctx, v1083); |
12201 | 0 | // Rule at src/isa/x64/lower.isle line 2122. |
12202 | 0 | return Some(v1084); |
12203 | | } |
12204 | | F64 => { |
12205 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12206 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
12207 | 0 | let v366 = constructor_put_in_xmm(ctx, v38.1); |
12208 | 0 | let v1085 = constructor_xmm_min_max_seq(ctx, F64, true, v68, v366); |
12209 | 0 | let v1086 = constructor_output_xmm(ctx, v1085); |
12210 | 0 | // Rule at src/isa/x64/lower.isle line 2124. |
12211 | 0 | return Some(v1086); |
12212 | | } |
12213 | | F32X4 => { |
12214 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12215 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
12216 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
12217 | 0 | let v1087 = constructor_x64_minps(ctx, v68, v69); |
12218 | 0 | let v1088 = constructor_put_in_xmm(ctx, v38.1); |
12219 | 0 | let v1089 = &C::put_in_xmm_mem(ctx, v38.0); |
12220 | 0 | let v1090 = constructor_x64_minps(ctx, v1088, v1089); |
12221 | 0 | let v1091 = &C::xmm_to_xmm_mem(ctx, v1090); |
12222 | 0 | let v1092 = constructor_x64_orps(ctx, v1087, v1091); |
12223 | 0 | let v1093 = &C::xmm_to_xmm_mem(ctx, v1090); |
12224 | 0 | let v1094 = constructor_x64_cmpps(ctx, v1092, v1093, &FcmpImm::Unordered); |
12225 | 0 | let v1095 = &C::xmm_to_xmm_mem(ctx, v1094); |
12226 | 0 | let v1096 = constructor_x64_orps(ctx, v1092, v1095); |
12227 | 0 | let v1098 = &C::xmi_imm(ctx, 0xA); |
12228 | 0 | let v1099 = constructor_x64_psrld(ctx, v1094, v1098); |
12229 | 0 | let v1100 = &C::xmm_to_xmm_mem(ctx, v1096); |
12230 | 0 | let v1101 = constructor_x64_andnps(ctx, v1099, v1100); |
12231 | 0 | let v1102 = constructor_output_xmm(ctx, v1101); |
12232 | 0 | // Rule at src/isa/x64/lower.isle line 2139. |
12233 | 0 | return Some(v1102); |
12234 | | } |
12235 | | F64X2 => { |
12236 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12237 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
12238 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
12239 | 0 | let v1103 = constructor_x64_minpd(ctx, v68, v69); |
12240 | 0 | let v1088 = constructor_put_in_xmm(ctx, v38.1); |
12241 | 0 | let v1089 = &C::put_in_xmm_mem(ctx, v38.0); |
12242 | 0 | let v1104 = constructor_x64_minpd(ctx, v1088, v1089); |
12243 | 0 | let v1105 = &C::xmm_to_xmm_mem(ctx, v1104); |
12244 | 0 | let v1106 = constructor_x64_orpd(ctx, v1103, v1105); |
12245 | 0 | let v1107 = &C::xmm_to_xmm_mem(ctx, v1104); |
12246 | 0 | let v1108 = constructor_x64_cmppd(ctx, v1103, v1107, &FcmpImm::Unordered); |
12247 | 0 | let v1109 = &C::xmm_to_xmm_mem(ctx, v1108); |
12248 | 0 | let v1110 = constructor_x64_orpd(ctx, v1106, v1109); |
12249 | 0 | let v1112 = &C::xmi_imm(ctx, 0xD); |
12250 | 0 | let v1113 = constructor_x64_psrlq(ctx, v1108, v1112); |
12251 | 0 | let v1114 = &C::xmm_to_xmm_mem(ctx, v1110); |
12252 | 0 | let v1115 = constructor_x64_andnpd(ctx, v1113, v1114); |
12253 | 0 | let v1116 = constructor_output_xmm(ctx, v1115); |
12254 | 0 | // Rule at src/isa/x64/lower.isle line 2182. |
12255 | 0 | return Some(v1116); |
12256 | | } |
12257 | 0 | _ => {} |
12258 | | } |
12259 | 0 | } |
12260 | | } |
12261 | | &Opcode::FminPseudo => { |
12262 | 0 | let v1 = C::first_result(ctx, arg0); |
12263 | 0 | if let Some(v2) = v1 { |
12264 | 0 | let v3 = C::value_type(ctx, v2); |
12265 | 0 | match v3 { |
12266 | | F32 => { |
12267 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12268 | 0 | let v1013 = constructor_put_in_xmm(ctx, v38.1); |
12269 | 0 | let v160 = &C::put_in_xmm_mem(ctx, v38.0); |
12270 | 0 | let v1152 = constructor_x64_minss(ctx, v1013, v160); |
12271 | 0 | let v1153 = constructor_output_xmm(ctx, v1152); |
12272 | 0 | // Rule at src/isa/x64/lower.isle line 2291. |
12273 | 0 | return Some(v1153); |
12274 | | } |
12275 | | F64 => { |
12276 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12277 | 0 | let v1013 = constructor_put_in_xmm(ctx, v38.1); |
12278 | 0 | let v160 = &C::put_in_xmm_mem(ctx, v38.0); |
12279 | 0 | let v1154 = constructor_x64_minsd(ctx, v1013, v160); |
12280 | 0 | let v1155 = constructor_output_xmm(ctx, v1154); |
12281 | 0 | // Rule at src/isa/x64/lower.isle line 2293. |
12282 | 0 | return Some(v1155); |
12283 | | } |
12284 | | F32X4 => { |
12285 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12286 | 0 | let v1013 = constructor_put_in_xmm(ctx, v38.1); |
12287 | 0 | let v160 = &C::put_in_xmm_mem(ctx, v38.0); |
12288 | 0 | let v1156 = constructor_x64_minps(ctx, v1013, v160); |
12289 | 0 | let v1157 = constructor_output_xmm(ctx, v1156); |
12290 | 0 | // Rule at src/isa/x64/lower.isle line 2295. |
12291 | 0 | return Some(v1157); |
12292 | | } |
12293 | | F64X2 => { |
12294 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12295 | 0 | let v1013 = constructor_put_in_xmm(ctx, v38.1); |
12296 | 0 | let v160 = &C::put_in_xmm_mem(ctx, v38.0); |
12297 | 0 | let v1158 = constructor_x64_minpd(ctx, v1013, v160); |
12298 | 0 | let v1159 = constructor_output_xmm(ctx, v1158); |
12299 | 0 | // Rule at src/isa/x64/lower.isle line 2297. |
12300 | 0 | return Some(v1159); |
12301 | | } |
12302 | 0 | _ => {} |
12303 | | } |
12304 | 0 | } |
12305 | | } |
12306 | | &Opcode::Fmax => { |
12307 | 0 | let v1 = C::first_result(ctx, arg0); |
12308 | 0 | if let Some(v2) = v1 { |
12309 | 0 | let v3 = C::value_type(ctx, v2); |
12310 | 0 | match v3 { |
12311 | | F32 => { |
12312 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12313 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
12314 | 0 | let v366 = constructor_put_in_xmm(ctx, v38.1); |
12315 | 0 | let v1118 = constructor_xmm_min_max_seq(ctx, F32, false, v68, v366); |
12316 | 0 | let v1119 = constructor_output_xmm(ctx, v1118); |
12317 | 0 | // Rule at src/isa/x64/lower.isle line 2194. |
12318 | 0 | return Some(v1119); |
12319 | | } |
12320 | | F64 => { |
12321 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12322 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
12323 | 0 | let v366 = constructor_put_in_xmm(ctx, v38.1); |
12324 | 0 | let v1120 = constructor_xmm_min_max_seq(ctx, F64, false, v68, v366); |
12325 | 0 | let v1121 = constructor_output_xmm(ctx, v1120); |
12326 | 0 | // Rule at src/isa/x64/lower.isle line 2196. |
12327 | 0 | return Some(v1121); |
12328 | | } |
12329 | | F32X4 => { |
12330 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12331 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
12332 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
12333 | 0 | let v1122 = constructor_x64_maxps(ctx, v68, v69); |
12334 | 0 | let v1088 = constructor_put_in_xmm(ctx, v38.1); |
12335 | 0 | let v1089 = &C::put_in_xmm_mem(ctx, v38.0); |
12336 | 0 | let v1123 = constructor_x64_maxps(ctx, v1088, v1089); |
12337 | 0 | let v1124 = &C::xmm_to_xmm_mem(ctx, v1123); |
12338 | 0 | let v1125 = constructor_x64_xorps(ctx, v1122, v1124); |
12339 | 0 | let v1126 = &C::xmm_to_xmm_mem(ctx, v1125); |
12340 | 0 | let v1127 = constructor_x64_orps(ctx, v1122, v1126); |
12341 | 0 | let v1128 = &C::xmm_to_xmm_mem(ctx, v1125); |
12342 | 0 | let v1129 = constructor_x64_subps(ctx, v1127, v1128); |
12343 | 0 | let v1130 = &C::xmm_to_xmm_mem(ctx, v1127); |
12344 | 0 | let v1131 = constructor_x64_cmpps(ctx, v1127, v1130, &FcmpImm::Unordered); |
12345 | 0 | let v1132 = &C::xmi_imm(ctx, 0xA); |
12346 | 0 | let v1133 = constructor_x64_psrld(ctx, v1131, v1132); |
12347 | 0 | let v1134 = &C::xmm_to_xmm_mem(ctx, v1129); |
12348 | 0 | let v1135 = constructor_x64_andnps(ctx, v1133, v1134); |
12349 | 0 | let v1136 = constructor_output_xmm(ctx, v1135); |
12350 | 0 | // Rule at src/isa/x64/lower.isle line 2202. |
12351 | 0 | return Some(v1136); |
12352 | | } |
12353 | | F64X2 => { |
12354 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12355 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
12356 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
12357 | 0 | let v1137 = constructor_x64_maxpd(ctx, v68, v69); |
12358 | 0 | let v1088 = constructor_put_in_xmm(ctx, v38.1); |
12359 | 0 | let v1089 = &C::put_in_xmm_mem(ctx, v38.0); |
12360 | 0 | let v1138 = constructor_x64_maxpd(ctx, v1088, v1089); |
12361 | 0 | let v1139 = &C::xmm_to_xmm_mem(ctx, v1138); |
12362 | 0 | let v1140 = constructor_x64_xorpd(ctx, v1137, v1139); |
12363 | 0 | let v1141 = &C::xmm_to_xmm_mem(ctx, v1140); |
12364 | 0 | let v1142 = constructor_x64_orpd(ctx, v1137, v1141); |
12365 | 0 | let v1143 = &C::xmm_to_xmm_mem(ctx, v1140); |
12366 | 0 | let v1144 = constructor_x64_subpd(ctx, v1142, v1143); |
12367 | 0 | let v1145 = &C::xmm_to_xmm_mem(ctx, v1142); |
12368 | 0 | let v1146 = constructor_x64_cmppd(ctx, v1142, v1145, &FcmpImm::Unordered); |
12369 | 0 | let v1147 = &C::xmi_imm(ctx, 0xD); |
12370 | 0 | let v1148 = constructor_x64_psrlq(ctx, v1146, v1147); |
12371 | 0 | let v1149 = &C::xmm_to_xmm_mem(ctx, v1144); |
12372 | 0 | let v1150 = constructor_x64_andnpd(ctx, v1148, v1149); |
12373 | 0 | let v1151 = constructor_output_xmm(ctx, v1150); |
12374 | 0 | // Rule at src/isa/x64/lower.isle line 2245. |
12375 | 0 | return Some(v1151); |
12376 | | } |
12377 | 0 | _ => {} |
12378 | | } |
12379 | 0 | } |
12380 | | } |
12381 | | &Opcode::FmaxPseudo => { |
12382 | 0 | let v1 = C::first_result(ctx, arg0); |
12383 | 0 | if let Some(v2) = v1 { |
12384 | 0 | let v3 = C::value_type(ctx, v2); |
12385 | 0 | match v3 { |
12386 | | F32 => { |
12387 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12388 | 0 | let v1013 = constructor_put_in_xmm(ctx, v38.1); |
12389 | 0 | let v160 = &C::put_in_xmm_mem(ctx, v38.0); |
12390 | 0 | let v1160 = constructor_x64_maxss(ctx, v1013, v160); |
12391 | 0 | let v1161 = constructor_output_xmm(ctx, v1160); |
12392 | 0 | // Rule at src/isa/x64/lower.isle line 2302. |
12393 | 0 | return Some(v1161); |
12394 | | } |
12395 | | F64 => { |
12396 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12397 | 0 | let v1013 = constructor_put_in_xmm(ctx, v38.1); |
12398 | 0 | let v160 = &C::put_in_xmm_mem(ctx, v38.0); |
12399 | 0 | let v1162 = constructor_x64_maxsd(ctx, v1013, v160); |
12400 | 0 | let v1163 = constructor_output_xmm(ctx, v1162); |
12401 | 0 | // Rule at src/isa/x64/lower.isle line 2304. |
12402 | 0 | return Some(v1163); |
12403 | | } |
12404 | | F32X4 => { |
12405 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12406 | 0 | let v1013 = constructor_put_in_xmm(ctx, v38.1); |
12407 | 0 | let v160 = &C::put_in_xmm_mem(ctx, v38.0); |
12408 | 0 | let v1164 = constructor_x64_maxps(ctx, v1013, v160); |
12409 | 0 | let v1165 = constructor_output_xmm(ctx, v1164); |
12410 | 0 | // Rule at src/isa/x64/lower.isle line 2306. |
12411 | 0 | return Some(v1165); |
12412 | | } |
12413 | | F64X2 => { |
12414 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12415 | 0 | let v1013 = constructor_put_in_xmm(ctx, v38.1); |
12416 | 0 | let v160 = &C::put_in_xmm_mem(ctx, v38.0); |
12417 | 0 | let v1166 = constructor_x64_maxpd(ctx, v1013, v160); |
12418 | 0 | let v1167 = constructor_output_xmm(ctx, v1166); |
12419 | 0 | // Rule at src/isa/x64/lower.isle line 2308. |
12420 | 0 | return Some(v1167); |
12421 | | } |
12422 | 0 | _ => {} |
12423 | | } |
12424 | 0 | } |
12425 | | } |
12426 | | &Opcode::Snarrow => { |
12427 | 0 | let v1 = C::first_result(ctx, arg0); |
12428 | 0 | if let Some(v2) = v1 { |
12429 | 0 | let v3 = C::value_type(ctx, v2); |
12430 | 0 | match v3 { |
12431 | | I8X16 => { |
12432 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12433 | 0 | let v1756 = C::value_type(ctx, v38.0); |
12434 | 0 | if v1756 == I16X8 { |
12435 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
12436 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
12437 | 0 | let v1757 = constructor_x64_packsswb(ctx, v68, v69); |
12438 | 0 | let v1758 = constructor_output_xmm(ctx, v1757); |
12439 | 0 | // Rule at src/isa/x64/lower.isle line 3202. |
12440 | 0 | return Some(v1758); |
12441 | 0 | } |
12442 | | } |
12443 | | I16X8 => { |
12444 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12445 | 0 | let v1756 = C::value_type(ctx, v38.0); |
12446 | 0 | if v1756 == I32X4 { |
12447 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
12448 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
12449 | 0 | let v1759 = constructor_x64_packssdw(ctx, v68, v69); |
12450 | 0 | let v1760 = constructor_output_xmm(ctx, v1759); |
12451 | 0 | // Rule at src/isa/x64/lower.isle line 3205. |
12452 | 0 | return Some(v1760); |
12453 | 0 | } |
12454 | | } |
12455 | | I32X4 => { |
12456 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12457 | 0 | let v154 = C::def_inst(ctx, v38.1); |
12458 | 0 | if let Some(v155) = v154 { |
12459 | 0 | let v156 = &C::inst_data(ctx, v155); |
12460 | | if let &InstructionData::UnaryConst { |
12461 | 0 | opcode: ref v1764, |
12462 | 0 | constant_handle: v1765, |
12463 | 0 | } = v156 { |
12464 | 0 | if let &Opcode::Vconst = v1764 { |
12465 | 0 | let v163 = C::def_inst(ctx, v38.0); |
12466 | 0 | if let Some(v164) = v163 { |
12467 | 0 | let v165 = &C::inst_data(ctx, v164); |
12468 | | if let &InstructionData::Unary { |
12469 | 0 | opcode: ref v166, |
12470 | 0 | arg: v167, |
12471 | 0 | } = v165 { |
12472 | 0 | match v166 { |
12473 | | &Opcode::FcvtToSintSat => { |
12474 | 0 | let v1761 = C::first_result(ctx, v164); |
12475 | 0 | if let Some(v1762) = v1761 { |
12476 | 0 | let v1763 = C::value_type(ctx, v1762); |
12477 | 0 | if v1763 == I64X2 { |
12478 | 0 | let v1766 = C::u128_from_constant(ctx, v1765); |
12479 | 0 | if let Some(v1767) = v1766 { |
12480 | 0 | if v1767 == 0x0 { |
12481 | 0 | let v168 = constructor_put_in_xmm(ctx, v167); |
12482 | 0 | let v397 = &C::xmm_to_xmm_mem(ctx, v168); |
12483 | 0 | let v1768 = constructor_x64_cmppd(ctx, v168, v397, &FcmpImm::Equal); |
12484 | 0 | let v1769 = C::snarrow_umax_mask(ctx); |
12485 | 0 | let v1770 = &constructor_const_to_xmm_mem(ctx, v1769); |
12486 | 0 | let v1771 = constructor_x64_andps(ctx, v1768, v1770); |
12487 | 0 | let v1772 = &C::xmm_to_xmm_mem(ctx, v1771); |
12488 | 0 | let v1773 = constructor_x64_minpd(ctx, v168, v1772); |
12489 | 0 | let v1774 = &C::xmm_to_xmm_mem(ctx, v1773); |
12490 | 0 | let v1775 = constructor_x64_cvttpd2dq(ctx, v1774); |
12491 | 0 | let v1776 = constructor_output_xmm(ctx, v1775); |
12492 | 0 | // Rule at src/isa/x64/lower.isle line 3214. |
12493 | 0 | return Some(v1776); |
12494 | 0 | } |
12495 | 0 | } |
12496 | 0 | } |
12497 | 0 | } |
12498 | | } |
12499 | | &Opcode::X86Cvtt2dq => { |
12500 | 0 | let v1761 = C::first_result(ctx, v164); |
12501 | 0 | if let Some(v1762) = v1761 { |
12502 | 0 | let v1763 = C::value_type(ctx, v1762); |
12503 | 0 | if v1763 == I64X2 { |
12504 | 0 | let v1766 = C::u128_from_constant(ctx, v1765); |
12505 | 0 | if let Some(v1767) = v1766 { |
12506 | 0 | if v1767 == 0x0 { |
12507 | 0 | let v418 = &C::put_in_xmm_mem(ctx, v167); |
12508 | 0 | let v1777 = constructor_x64_cvttpd2dq(ctx, v418); |
12509 | 0 | let v1778 = constructor_output_xmm(ctx, v1777); |
12510 | 0 | // Rule at src/isa/x64/lower.isle line 3236. |
12511 | 0 | return Some(v1778); |
12512 | 0 | } |
12513 | 0 | } |
12514 | 0 | } |
12515 | 0 | } |
12516 | | } |
12517 | 0 | _ => {} |
12518 | | } |
12519 | 0 | } |
12520 | 0 | } |
12521 | 0 | } |
12522 | 0 | } |
12523 | 0 | } |
12524 | | } |
12525 | 0 | _ => {} |
12526 | | } |
12527 | 0 | } |
12528 | | } |
12529 | | &Opcode::Unarrow => { |
12530 | 0 | let v1 = C::first_result(ctx, arg0); |
12531 | 0 | if let Some(v2) = v1 { |
12532 | 0 | let v3 = C::value_type(ctx, v2); |
12533 | 0 | match v3 { |
12534 | | I8X16 => { |
12535 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12536 | 0 | let v1756 = C::value_type(ctx, v38.0); |
12537 | 0 | if v1756 == I16X8 { |
12538 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
12539 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
12540 | 0 | let v1779 = constructor_x64_packuswb(ctx, v68, v69); |
12541 | 0 | let v1780 = constructor_output_xmm(ctx, v1779); |
12542 | 0 | // Rule at src/isa/x64/lower.isle line 3242. |
12543 | 0 | return Some(v1780); |
12544 | 0 | } |
12545 | | } |
12546 | | I16X8 => { |
12547 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12548 | 0 | let v1756 = C::value_type(ctx, v38.0); |
12549 | 0 | if v1756 == I32X4 { |
12550 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
12551 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
12552 | 0 | let v1781 = constructor_x64_packusdw(ctx, v68, v69); |
12553 | 0 | let v1782 = constructor_output_xmm(ctx, v1781); |
12554 | 0 | // Rule at src/isa/x64/lower.isle line 3245. |
12555 | 0 | return Some(v1782); |
12556 | 0 | } |
12557 | | } |
12558 | 0 | _ => {} |
12559 | | } |
12560 | 0 | } |
12561 | | } |
12562 | | &Opcode::Uunarrow => { |
12563 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12564 | 0 | let v154 = C::def_inst(ctx, v38.1); |
12565 | 0 | if let Some(v155) = v154 { |
12566 | 0 | let v156 = &C::inst_data(ctx, v155); |
12567 | | if let &InstructionData::UnaryConst { |
12568 | 0 | opcode: ref v1764, |
12569 | 0 | constant_handle: v1765, |
12570 | 0 | } = v156 { |
12571 | 0 | if let &Opcode::Vconst = v1764 { |
12572 | 0 | let v163 = C::def_inst(ctx, v38.0); |
12573 | 0 | if let Some(v164) = v163 { |
12574 | 0 | let v165 = &C::inst_data(ctx, v164); |
12575 | | if let &InstructionData::Unary { |
12576 | 0 | opcode: ref v166, |
12577 | 0 | arg: v167, |
12578 | 0 | } = v165 { |
12579 | 0 | if let &Opcode::FcvtToUintSat = v166 { |
12580 | 0 | let v387 = C::value_type(ctx, v167); |
12581 | 0 | if v387 == F64X2 { |
12582 | 0 | let v1766 = C::u128_from_constant(ctx, v1765); |
12583 | 0 | if let Some(v1767) = v1766 { |
12584 | 0 | if v1767 == 0x0 { |
12585 | 0 | let v168 = constructor_put_in_xmm(ctx, v167); |
12586 | 0 | let v2232 = constructor_xmm_zero(ctx, F64X2); |
12587 | 0 | let v2233 = &C::xmm_to_xmm_mem(ctx, v2232); |
12588 | 0 | let v2234 = constructor_x64_maxpd(ctx, v168, v2233); |
12589 | 0 | let v2235 = C::uunarrow_umax_mask(ctx); |
12590 | 0 | let v2236 = &constructor_const_to_xmm_mem(ctx, v2235); |
12591 | 0 | let v2237 = constructor_x64_minpd(ctx, v2234, v2236); |
12592 | 0 | let v2238 = &C::xmm_to_xmm_mem(ctx, v2237); |
12593 | 0 | let v2239 = constructor_x64_roundpd(ctx, v2238, &RoundImm::RoundZero); |
12594 | 0 | let v2240 = C::uunarrow_uint_mask(ctx); |
12595 | 0 | let v2241 = &constructor_const_to_xmm_mem(ctx, v2240); |
12596 | 0 | let v2242 = constructor_x64_addpd(ctx, v2239, v2241); |
12597 | 0 | let v2243 = &C::xmm_to_xmm_mem(ctx, v2232); |
12598 | 0 | let v2245 = constructor_x64_shufps(ctx, v2242, v2243, 0x88); |
12599 | 0 | let v2246 = constructor_output_xmm(ctx, v2245); |
12600 | 0 | // Rule at src/isa/x64/lower.isle line 3957. |
12601 | 0 | return Some(v2246); |
12602 | 0 | } |
12603 | 0 | } |
12604 | 0 | } |
12605 | 0 | } |
12606 | 0 | } |
12607 | 0 | } |
12608 | 0 | } |
12609 | 0 | } |
12610 | 0 | } |
12611 | | } |
12612 | | &Opcode::IaddPairwise => { |
12613 | 0 | let v1 = C::first_result(ctx, arg0); |
12614 | 0 | if let Some(v2) = v1 { |
12615 | 0 | let v3 = C::value_type(ctx, v2); |
12616 | 0 | match v3 { |
12617 | | I16X8 => { |
12618 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12619 | 0 | let v154 = C::def_inst(ctx, v38.1); |
12620 | 0 | if let Some(v155) = v154 { |
12621 | 0 | let v156 = &C::inst_data(ctx, v155); |
12622 | | if let &InstructionData::Unary { |
12623 | 0 | opcode: ref v157, |
12624 | 0 | arg: v158, |
12625 | 0 | } = v156 { |
12626 | 0 | match v157 { |
12627 | | &Opcode::SwidenHigh => { |
12628 | 0 | let v163 = C::def_inst(ctx, v38.0); |
12629 | 0 | if let Some(v164) = v163 { |
12630 | 0 | let v165 = &C::inst_data(ctx, v164); |
12631 | | if let &InstructionData::Unary { |
12632 | 0 | opcode: ref v166, |
12633 | 0 | arg: v167, |
12634 | 0 | } = v165 { |
12635 | 0 | if let &Opcode::SwidenLow = v166 { |
12636 | 0 | if v158 == v167 { |
12637 | 0 | let v387 = C::value_type(ctx, v167); |
12638 | 0 | if v387 == I8X16 { |
12639 | 0 | let v1671 = C::iadd_pairwise_mul_const_16(ctx); |
12640 | 0 | let v1672 = constructor_x64_xmm_load_const(ctx, I8X16, v1671); |
12641 | 0 | let v1673 = &C::put_in_xmm_mem(ctx, v167); |
12642 | 0 | let v1674 = constructor_x64_pmaddubsw(ctx, v1672, v1673); |
12643 | 0 | let v1675 = constructor_output_xmm(ctx, v1674); |
12644 | 0 | // Rule at src/isa/x64/lower.isle line 3108. |
12645 | 0 | return Some(v1675); |
12646 | 0 | } |
12647 | 0 | } |
12648 | 0 | } |
12649 | 0 | } |
12650 | 0 | } |
12651 | | } |
12652 | | &Opcode::UwidenHigh => { |
12653 | 0 | let v163 = C::def_inst(ctx, v38.0); |
12654 | 0 | if let Some(v164) = v163 { |
12655 | 0 | let v165 = &C::inst_data(ctx, v164); |
12656 | | if let &InstructionData::Unary { |
12657 | 0 | opcode: ref v166, |
12658 | 0 | arg: v167, |
12659 | 0 | } = v165 { |
12660 | 0 | if let &Opcode::UwidenLow = v166 { |
12661 | 0 | if v158 == v167 { |
12662 | 0 | let v387 = C::value_type(ctx, v167); |
12663 | 0 | if v387 == I8X16 { |
12664 | 0 | let v1671 = C::iadd_pairwise_mul_const_16(ctx); |
12665 | 0 | let v1681 = &constructor_const_to_xmm_mem(ctx, v1671); |
12666 | 0 | let v1678 = constructor_put_in_xmm(ctx, v167); |
12667 | 0 | let v1682 = constructor_x64_pmaddubsw(ctx, v1678, v1681); |
12668 | 0 | let v1683 = constructor_output_xmm(ctx, v1682); |
12669 | 0 | // Rule at src/isa/x64/lower.isle line 3124. |
12670 | 0 | return Some(v1683); |
12671 | 0 | } |
12672 | 0 | } |
12673 | 0 | } |
12674 | 0 | } |
12675 | 0 | } |
12676 | | } |
12677 | 0 | _ => {} |
12678 | | } |
12679 | 0 | } |
12680 | 0 | } |
12681 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
12682 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
12683 | 0 | let v1667 = constructor_x64_phaddw(ctx, v68, v69); |
12684 | 0 | let v1668 = constructor_output_xmm(ctx, v1667); |
12685 | 0 | // Rule at src/isa/x64/lower.isle line 3101. |
12686 | 0 | return Some(v1668); |
12687 | | } |
12688 | | I32X4 => { |
12689 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12690 | 0 | let v154 = C::def_inst(ctx, v38.1); |
12691 | 0 | if let Some(v155) = v154 { |
12692 | 0 | let v156 = &C::inst_data(ctx, v155); |
12693 | 0 | match v156 { |
12694 | | &InstructionData::Binary { |
12695 | 0 | opcode: ref v1709, |
12696 | 0 | args: ref v1710, |
12697 | 0 | } => { |
12698 | 0 | if let &Opcode::Imul = v1709 { |
12699 | 0 | let v163 = C::def_inst(ctx, v38.0); |
12700 | 0 | if let Some(v164) = v163 { |
12701 | 0 | let v165 = &C::inst_data(ctx, v164); |
12702 | | if let &InstructionData::Binary { |
12703 | 0 | opcode: ref v1694, |
12704 | 0 | args: ref v1695, |
12705 | 0 | } = v165 { |
12706 | 0 | if let &Opcode::Imul = v1694 { |
12707 | 0 | let v1696 = C::unpack_value_array_2(ctx, v1695); |
12708 | 0 | let v1699 = C::def_inst(ctx, v1696.0); |
12709 | 0 | if let Some(v1700) = v1699 { |
12710 | 0 | let v1701 = &C::inst_data(ctx, v1700); |
12711 | | if let &InstructionData::Unary { |
12712 | 0 | opcode: ref v1702, |
12713 | 0 | arg: v1703, |
12714 | 0 | } = v1701 { |
12715 | 0 | if let &Opcode::SwidenLow = v1702 { |
12716 | 0 | let v1704 = C::def_inst(ctx, v1696.1); |
12717 | 0 | if let Some(v1705) = v1704 { |
12718 | 0 | let v1706 = &C::inst_data(ctx, v1705); |
12719 | | if let &InstructionData::Unary { |
12720 | 0 | opcode: ref v1707, |
12721 | 0 | arg: v1708, |
12722 | 0 | } = v1706 { |
12723 | 0 | if let &Opcode::SwidenLow = v1707 { |
12724 | 0 | let v1711 = C::unpack_value_array_2(ctx, v1710); |
12725 | 0 | let v1714 = C::def_inst(ctx, v1711.0); |
12726 | 0 | if let Some(v1715) = v1714 { |
12727 | 0 | let v1716 = &C::inst_data(ctx, v1715); |
12728 | | if let &InstructionData::Unary { |
12729 | 0 | opcode: ref v1717, |
12730 | 0 | arg: v1718, |
12731 | 0 | } = v1716 { |
12732 | 0 | if let &Opcode::SwidenHigh = v1717 { |
12733 | 0 | if v1703 == v1718 { |
12734 | 0 | let v1719 = C::def_inst(ctx, v1711.1); |
12735 | 0 | if let Some(v1720) = v1719 { |
12736 | 0 | let v1721 = &C::inst_data(ctx, v1720); |
12737 | | if let &InstructionData::Unary { |
12738 | 0 | opcode: ref v1722, |
12739 | 0 | arg: v1723, |
12740 | 0 | } = v1721 { |
12741 | 0 | if let &Opcode::SwidenHigh = v1722 { |
12742 | 0 | if v1708 == v1723 { |
12743 | 0 | let v1724 = constructor_put_in_xmm(ctx, v1703); |
12744 | 0 | let v1725 = &C::put_in_xmm_mem(ctx, v1708); |
12745 | 0 | let v1726 = constructor_x64_pmaddwd(ctx, v1724, v1725); |
12746 | 0 | let v1727 = constructor_output_xmm(ctx, v1726); |
12747 | 0 | // Rule at src/isa/x64/lower.isle line 3146. |
12748 | 0 | return Some(v1727); |
12749 | 0 | } |
12750 | 0 | } |
12751 | 0 | } |
12752 | 0 | } |
12753 | 0 | } |
12754 | 0 | } |
12755 | 0 | } |
12756 | 0 | } |
12757 | 0 | } |
12758 | 0 | } |
12759 | 0 | } |
12760 | 0 | } |
12761 | 0 | } |
12762 | 0 | } |
12763 | 0 | } |
12764 | 0 | } |
12765 | 0 | } |
12766 | 0 | } |
12767 | | } |
12768 | | &InstructionData::Unary { |
12769 | 0 | opcode: ref v157, |
12770 | 0 | arg: v158, |
12771 | 0 | } => { |
12772 | 0 | match v157 { |
12773 | | &Opcode::SwidenHigh => { |
12774 | 0 | let v163 = C::def_inst(ctx, v38.0); |
12775 | 0 | if let Some(v164) = v163 { |
12776 | 0 | let v165 = &C::inst_data(ctx, v164); |
12777 | | if let &InstructionData::Unary { |
12778 | 0 | opcode: ref v166, |
12779 | 0 | arg: v167, |
12780 | 0 | } = v165 { |
12781 | 0 | if let &Opcode::SwidenLow = v166 { |
12782 | 0 | if v158 == v167 { |
12783 | 0 | let v387 = C::value_type(ctx, v167); |
12784 | 0 | if v387 == I16X8 { |
12785 | 0 | let v1676 = C::iadd_pairwise_mul_const_32(ctx); |
12786 | 0 | let v1677 = &constructor_const_to_xmm_mem(ctx, v1676); |
12787 | 0 | let v1678 = constructor_put_in_xmm(ctx, v167); |
12788 | 0 | let v1679 = constructor_x64_pmaddwd(ctx, v1678, v1677); |
12789 | 0 | let v1680 = constructor_output_xmm(ctx, v1679); |
12790 | 0 | // Rule at src/isa/x64/lower.isle line 3116. |
12791 | 0 | return Some(v1680); |
12792 | 0 | } |
12793 | 0 | } |
12794 | 0 | } |
12795 | 0 | } |
12796 | 0 | } |
12797 | | } |
12798 | | &Opcode::UwidenHigh => { |
12799 | 0 | let v163 = C::def_inst(ctx, v38.0); |
12800 | 0 | if let Some(v164) = v163 { |
12801 | 0 | let v165 = &C::inst_data(ctx, v164); |
12802 | | if let &InstructionData::Unary { |
12803 | 0 | opcode: ref v166, |
12804 | 0 | arg: v167, |
12805 | 0 | } = v165 { |
12806 | 0 | if let &Opcode::UwidenLow = v166 { |
12807 | 0 | if v158 == v167 { |
12808 | 0 | let v387 = C::value_type(ctx, v167); |
12809 | 0 | if v387 == I16X8 { |
12810 | 0 | let v1684 = C::iadd_pairwise_xor_const_32(ctx); |
12811 | 0 | let v1685 = &constructor_const_to_xmm_mem(ctx, v1684); |
12812 | 0 | let v1678 = constructor_put_in_xmm(ctx, v167); |
12813 | 0 | let v1686 = constructor_x64_pxor(ctx, v1678, v1685); |
12814 | 0 | let v1687 = C::iadd_pairwise_mul_const_32(ctx); |
12815 | 0 | let v1688 = &constructor_const_to_xmm_mem(ctx, v1687); |
12816 | 0 | let v1689 = constructor_x64_pmaddwd(ctx, v1686, v1688); |
12817 | 0 | let v1690 = C::iadd_pairwise_addd_const_32(ctx); |
12818 | 0 | let v1691 = &constructor_const_to_xmm_mem(ctx, v1690); |
12819 | 0 | let v1692 = constructor_x64_paddd(ctx, v1689, v1691); |
12820 | 0 | let v1693 = constructor_output_xmm(ctx, v1692); |
12821 | 0 | // Rule at src/isa/x64/lower.isle line 3132. |
12822 | 0 | return Some(v1693); |
12823 | 0 | } |
12824 | 0 | } |
12825 | 0 | } |
12826 | 0 | } |
12827 | 0 | } |
12828 | | } |
12829 | 0 | _ => {} |
12830 | | } |
12831 | | } |
12832 | 0 | _ => {} |
12833 | | } |
12834 | 0 | } |
12835 | 0 | let v68 = constructor_put_in_xmm(ctx, v38.0); |
12836 | 0 | let v69 = &C::put_in_xmm_mem(ctx, v38.1); |
12837 | 0 | let v1669 = constructor_x64_phaddd(ctx, v68, v69); |
12838 | 0 | let v1670 = constructor_output_xmm(ctx, v1669); |
12839 | 0 | // Rule at src/isa/x64/lower.isle line 3104. |
12840 | 0 | return Some(v1670); |
12841 | | } |
12842 | 0 | _ => {} |
12843 | | } |
12844 | 0 | } |
12845 | | } |
12846 | | &Opcode::X86Pmaddubsw => { |
12847 | 0 | let v1 = C::first_result(ctx, arg0); |
12848 | 0 | if let Some(v2) = v1 { |
12849 | 0 | let v3 = C::value_type(ctx, v2); |
12850 | 0 | if v3 == I16X8 { |
12851 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12852 | 0 | let v1013 = constructor_put_in_xmm(ctx, v38.1); |
12853 | 0 | let v160 = &C::put_in_xmm_mem(ctx, v38.0); |
12854 | 0 | let v1014 = constructor_x64_pmaddubsw(ctx, v1013, v160); |
12855 | 0 | let v1015 = constructor_output_xmm(ctx, v1014); |
12856 | 0 | // Rule at src/isa/x64/lower.isle line 2025. |
12857 | 0 | return Some(v1015); |
12858 | 0 | } |
12859 | 0 | } |
12860 | | } |
12861 | | &Opcode::Iconcat => { |
12862 | 0 | let v38 = C::unpack_value_array_2(ctx, v37); |
12863 | 0 | let v1756 = C::value_type(ctx, v38.0); |
12864 | 0 | if v1756 == I64 { |
12865 | 0 | let v2207 = C::put_in_reg(ctx, v38.0); |
12866 | 0 | let v2208 = C::put_in_reg(ctx, v38.1); |
12867 | 0 | let v2209 = C::value_regs(ctx, v2207, v2208); |
12868 | 0 | let v2210 = C::output(ctx, v2209); |
12869 | 0 | // Rule at src/isa/x64/lower.isle line 3905. |
12870 | 0 | return Some(v2210); |
12871 | 0 | } |
12872 | | } |
12873 | 0 | _ => {} |
12874 | | } |
12875 | | } |
12876 | | &InstructionData::BinaryImm8 { |
12877 | 0 | opcode: ref v2081, |
12878 | 0 | arg: v2082, |
12879 | 0 | imm: v2083, |
12880 | 0 | } => { |
12881 | 0 | if let &Opcode::Extractlane = v2081 { |
12882 | 0 | let v1 = C::first_result(ctx, arg0); |
12883 | 0 | if let Some(v2) = v1 { |
12884 | 0 | let v2084 = C::u8_from_uimm8(ctx, v2083); |
12885 | 0 | match v2084 { |
12886 | | 0x0 => { |
12887 | 0 | let v3 = C::value_type(ctx, v2); |
12888 | 0 | let v144 = C::ty_scalar_float(ctx, v3); |
12889 | 0 | if let Some(v145) = v144 { |
12890 | 0 | let v2085 = constructor_output_value(ctx, v2082); |
12891 | 0 | // Rule at src/isa/x64/lower.isle line 3716. |
12892 | 0 | return Some(v2085); |
12893 | 0 | } |
12894 | | } |
12895 | | 0x1 => { |
12896 | 0 | let v3 = C::value_type(ctx, v2); |
12897 | 0 | if v3 == F64 { |
12898 | 0 | let v2086 = C::value_type(ctx, v2082); |
12899 | 0 | let v2087 = C::ty_vec128(ctx, v2086); |
12900 | 0 | if let Some(v2088) = v2087 { |
12901 | 0 | let v2089 = &C::put_in_xmm_mem(ctx, v2082); |
12902 | 0 | let v2092 = constructor_x64_pshufd(ctx, v2089, 0xEE); |
12903 | 0 | let v2093 = constructor_output_xmm(ctx, v2092); |
12904 | 0 | // Rule at src/isa/x64/lower.isle line 3725. |
12905 | 0 | return Some(v2093); |
12906 | 0 | } |
12907 | 0 | } |
12908 | | } |
12909 | 0 | _ => {} |
12910 | | } |
12911 | 0 | let v3 = C::value_type(ctx, v2); |
12912 | 0 | if v3 == F32 { |
12913 | 0 | let v2086 = C::value_type(ctx, v2082); |
12914 | 0 | let v2087 = C::ty_vec128(ctx, v2086); |
12915 | 0 | if let Some(v2088) = v2087 { |
12916 | 0 | let v2089 = &C::put_in_xmm_mem(ctx, v2082); |
12917 | 0 | let v2090 = constructor_x64_pshufd(ctx, v2089, v2084); |
12918 | 0 | let v2091 = constructor_output_xmm(ctx, v2090); |
12919 | 0 | // Rule at src/isa/x64/lower.isle line 3720. |
12920 | 0 | return Some(v2091); |
12921 | 0 | } |
12922 | 0 | } |
12923 | 0 | } |
12924 | 0 | let v2086 = C::value_type(ctx, v2082); |
12925 | 0 | let v2094 = C::multi_lane(ctx, v2086); |
12926 | 0 | if let Some(v2095) = v2094 { |
12927 | 0 | match v2095.0 { |
12928 | | 0x8 => { |
12929 | 0 | if v2095.1 == 0x10 { |
12930 | 0 | let v2098 = constructor_put_in_xmm(ctx, v2082); |
12931 | 0 | let v2084 = C::u8_from_uimm8(ctx, v2083); |
12932 | 0 | let v2099 = constructor_x64_pextrb(ctx, v2098, v2084); |
12933 | 0 | let v2100 = constructor_output_gpr(ctx, v2099); |
12934 | 0 | // Rule at src/isa/x64/lower.isle line 3734. |
12935 | 0 | return Some(v2100); |
12936 | 0 | } |
12937 | | } |
12938 | | 0x10 => { |
12939 | 0 | if v2095.1 == 0x8 { |
12940 | 0 | let v2098 = constructor_put_in_xmm(ctx, v2082); |
12941 | 0 | let v2084 = C::u8_from_uimm8(ctx, v2083); |
12942 | 0 | let v2101 = constructor_x64_pextrw(ctx, v2098, v2084); |
12943 | 0 | let v2102 = constructor_output_gpr(ctx, v2101); |
12944 | 0 | // Rule at src/isa/x64/lower.isle line 3739. |
12945 | 0 | return Some(v2102); |
12946 | 0 | } |
12947 | | } |
12948 | | 0x20 => { |
12949 | 0 | if v2095.1 == 0x4 { |
12950 | 0 | let v2098 = constructor_put_in_xmm(ctx, v2082); |
12951 | 0 | let v2084 = C::u8_from_uimm8(ctx, v2083); |
12952 | 0 | let v2103 = constructor_x64_pextrd(ctx, v2098, v2084); |
12953 | 0 | let v2104 = constructor_output_gpr(ctx, v2103); |
12954 | 0 | // Rule at src/isa/x64/lower.isle line 3744. |
12955 | 0 | return Some(v2104); |
12956 | 0 | } |
12957 | | } |
12958 | | 0x40 => { |
12959 | 0 | if v2095.1 == 0x2 { |
12960 | 0 | let v2098 = constructor_put_in_xmm(ctx, v2082); |
12961 | 0 | let v2084 = C::u8_from_uimm8(ctx, v2083); |
12962 | 0 | let v2105 = constructor_x64_pextrq(ctx, v2098, v2084); |
12963 | 0 | let v2106 = constructor_output_gpr(ctx, v2105); |
12964 | 0 | // Rule at src/isa/x64/lower.isle line 3747. |
12965 | 0 | return Some(v2106); |
12966 | 0 | } |
12967 | | } |
12968 | 0 | _ => {} |
12969 | | } |
12970 | 0 | } |
12971 | 0 | } |
12972 | | } |
12973 | | &InstructionData::Call { |
12974 | 103k | opcode: ref v1515, |
12975 | 103k | args: v1516, |
12976 | 103k | func_ref: v1517, |
12977 | 103k | } => { |
12978 | 103k | if let &Opcode::Call = v1515 { |
12979 | 103k | let v1519 = C::func_ref_data(ctx, v1517); |
12980 | 103k | let v1518 = C::value_list_slice(ctx, v1516); |
12981 | 103k | let v1523 = C::gen_call(ctx, v1519.0, v1519.1, v1519.2, v1518); |
12982 | 103k | // Rule at src/isa/x64/lower.isle line 2771. |
12983 | 103k | return Some(v1523); |
12984 | 0 | } |
12985 | | } |
12986 | | &InstructionData::CallIndirect { |
12987 | 49.9k | opcode: ref v1524, |
12988 | 49.9k | args: v1525, |
12989 | 49.9k | sig_ref: v1526, |
12990 | 49.9k | } => { |
12991 | 49.9k | if let &Opcode::CallIndirect = v1524 { |
12992 | 49.9k | let v1527 = C::value_list_slice(ctx, v1525); |
12993 | 49.9k | let v1528 = C::value_slice_unwrap(ctx, v1527); |
12994 | 49.9k | if let Some(v1529) = v1528 { |
12995 | 49.9k | let v1532 = C::gen_call_indirect(ctx, v1526, v1529.0, v1529.1); |
12996 | 49.9k | // Rule at src/isa/x64/lower.isle line 2774. |
12997 | 49.9k | return Some(v1532); |
12998 | 0 | } |
12999 | 0 | } |
13000 | | } |
13001 | | &InstructionData::FloatCompare { |
13002 | 0 | opcode: ref v759, |
13003 | 0 | args: ref v760, |
13004 | 0 | cond: ref v761, |
13005 | 0 | } => { |
13006 | 0 | if let &Opcode::Fcmp = v759 { |
13007 | 0 | match v761 { |
13008 | | &FloatCC::Equal => { |
13009 | 0 | let v762 = C::unpack_value_array_2(ctx, v760); |
13010 | 0 | let v765 = C::value_type(ctx, v762.0); |
13011 | 0 | let v771 = C::ty_vec128(ctx, v765); |
13012 | 0 | if let Some(v772) = v771 { |
13013 | 0 | let v773 = constructor_put_in_xmm(ctx, v762.0); |
13014 | 0 | let v774 = &C::put_in_xmm_mem(ctx, v762.1); |
13015 | 0 | let v776 = constructor_x64_cmpp(ctx, v772, v773, v774, &FcmpImm::Equal); |
13016 | 0 | let v777 = constructor_output_xmm(ctx, v776); |
13017 | 0 | // Rule at src/isa/x64/lower.isle line 1538. |
13018 | 0 | return Some(v777); |
13019 | 0 | } |
13020 | | } |
13021 | | &FloatCC::GreaterThan => { |
13022 | 0 | let v762 = C::unpack_value_array_2(ctx, v760); |
13023 | 0 | let v765 = C::value_type(ctx, v762.0); |
13024 | 0 | let v771 = C::ty_vec128(ctx, v765); |
13025 | 0 | if let Some(v772) = v771 { |
13026 | 0 | let v799 = constructor_put_in_xmm(ctx, v762.1); |
13027 | 0 | let v800 = &C::put_in_xmm_mem(ctx, v762.0); |
13028 | 0 | let v801 = constructor_x64_cmpp(ctx, v772, v799, v800, &FcmpImm::LessThan); |
13029 | 0 | let v802 = constructor_output_xmm(ctx, v801); |
13030 | 0 | // Rule at src/isa/x64/lower.isle line 1558. |
13031 | 0 | return Some(v802); |
13032 | 0 | } |
13033 | | } |
13034 | | &FloatCC::GreaterThanOrEqual => { |
13035 | 0 | let v762 = C::unpack_value_array_2(ctx, v760); |
13036 | 0 | let v765 = C::value_type(ctx, v762.0); |
13037 | 0 | let v771 = C::ty_vec128(ctx, v765); |
13038 | 0 | if let Some(v772) = v771 { |
13039 | 0 | let v799 = constructor_put_in_xmm(ctx, v762.1); |
13040 | 0 | let v800 = &C::put_in_xmm_mem(ctx, v762.0); |
13041 | 0 | let v803 = constructor_x64_cmpp(ctx, v772, v799, v800, &FcmpImm::LessThanOrEqual); |
13042 | 0 | let v804 = constructor_output_xmm(ctx, v803); |
13043 | 0 | // Rule at src/isa/x64/lower.isle line 1560. |
13044 | 0 | return Some(v804); |
13045 | 0 | } |
13046 | | } |
13047 | | &FloatCC::LessThan => { |
13048 | 0 | let v762 = C::unpack_value_array_2(ctx, v760); |
13049 | 0 | let v765 = C::value_type(ctx, v762.0); |
13050 | 0 | let v771 = C::ty_vec128(ctx, v765); |
13051 | 0 | if let Some(v772) = v771 { |
13052 | 0 | let v773 = constructor_put_in_xmm(ctx, v762.0); |
13053 | 0 | let v774 = &C::put_in_xmm_mem(ctx, v762.1); |
13054 | 0 | let v782 = constructor_x64_cmpp(ctx, v772, v773, v774, &FcmpImm::LessThan); |
13055 | 0 | let v783 = constructor_output_xmm(ctx, v782); |
13056 | 0 | // Rule at src/isa/x64/lower.isle line 1542. |
13057 | 0 | return Some(v783); |
13058 | 0 | } |
13059 | | } |
13060 | | &FloatCC::LessThanOrEqual => { |
13061 | 0 | let v762 = C::unpack_value_array_2(ctx, v760); |
13062 | 0 | let v765 = C::value_type(ctx, v762.0); |
13063 | 0 | let v771 = C::ty_vec128(ctx, v765); |
13064 | 0 | if let Some(v772) = v771 { |
13065 | 0 | let v773 = constructor_put_in_xmm(ctx, v762.0); |
13066 | 0 | let v774 = &C::put_in_xmm_mem(ctx, v762.1); |
13067 | 0 | let v785 = constructor_x64_cmpp(ctx, v772, v773, v774, &FcmpImm::LessThanOrEqual); |
13068 | 0 | let v786 = constructor_output_xmm(ctx, v785); |
13069 | 0 | // Rule at src/isa/x64/lower.isle line 1544. |
13070 | 0 | return Some(v786); |
13071 | 0 | } |
13072 | | } |
13073 | | &FloatCC::NotEqual => { |
13074 | 0 | let v762 = C::unpack_value_array_2(ctx, v760); |
13075 | 0 | let v765 = C::value_type(ctx, v762.0); |
13076 | 0 | let v771 = C::ty_vec128(ctx, v765); |
13077 | 0 | if let Some(v772) = v771 { |
13078 | 0 | let v773 = constructor_put_in_xmm(ctx, v762.0); |
13079 | 0 | let v774 = &C::put_in_xmm_mem(ctx, v762.1); |
13080 | 0 | let v779 = constructor_x64_cmpp(ctx, v772, v773, v774, &FcmpImm::NotEqual); |
13081 | 0 | let v780 = constructor_output_xmm(ctx, v779); |
13082 | 0 | // Rule at src/isa/x64/lower.isle line 1540. |
13083 | 0 | return Some(v780); |
13084 | 0 | } |
13085 | | } |
13086 | | &FloatCC::Ordered => { |
13087 | 0 | let v762 = C::unpack_value_array_2(ctx, v760); |
13088 | 0 | let v765 = C::value_type(ctx, v762.0); |
13089 | 0 | let v771 = C::ty_vec128(ctx, v765); |
13090 | 0 | if let Some(v772) = v771 { |
13091 | 0 | let v773 = constructor_put_in_xmm(ctx, v762.0); |
13092 | 0 | let v774 = &C::put_in_xmm_mem(ctx, v762.1); |
13093 | 0 | let v788 = constructor_x64_cmpp(ctx, v772, v773, v774, &FcmpImm::Ordered); |
13094 | 0 | let v789 = constructor_output_xmm(ctx, v788); |
13095 | 0 | // Rule at src/isa/x64/lower.isle line 1546. |
13096 | 0 | return Some(v789); |
13097 | 0 | } |
13098 | | } |
13099 | | &FloatCC::Unordered => { |
13100 | 0 | let v762 = C::unpack_value_array_2(ctx, v760); |
13101 | 0 | let v765 = C::value_type(ctx, v762.0); |
13102 | 0 | let v771 = C::ty_vec128(ctx, v765); |
13103 | 0 | if let Some(v772) = v771 { |
13104 | 0 | let v773 = constructor_put_in_xmm(ctx, v762.0); |
13105 | 0 | let v774 = &C::put_in_xmm_mem(ctx, v762.1); |
13106 | 0 | let v791 = constructor_x64_cmpp(ctx, v772, v773, v774, &FcmpImm::Unordered); |
13107 | 0 | let v792 = constructor_output_xmm(ctx, v791); |
13108 | 0 | // Rule at src/isa/x64/lower.isle line 1548. |
13109 | 0 | return Some(v792); |
13110 | 0 | } |
13111 | | } |
13112 | | &FloatCC::UnorderedOrGreaterThan => { |
13113 | 0 | let v762 = C::unpack_value_array_2(ctx, v760); |
13114 | 0 | let v765 = C::value_type(ctx, v762.0); |
13115 | 0 | let v771 = C::ty_vec128(ctx, v765); |
13116 | 0 | if let Some(v772) = v771 { |
13117 | 0 | let v773 = constructor_put_in_xmm(ctx, v762.0); |
13118 | 0 | let v774 = &C::put_in_xmm_mem(ctx, v762.1); |
13119 | 0 | let v794 = constructor_x64_cmpp(ctx, v772, v773, v774, &FcmpImm::UnorderedOrGreaterThan); |
13120 | 0 | let v795 = constructor_output_xmm(ctx, v794); |
13121 | 0 | // Rule at src/isa/x64/lower.isle line 1550. |
13122 | 0 | return Some(v795); |
13123 | 0 | } |
13124 | | } |
13125 | | &FloatCC::UnorderedOrGreaterThanOrEqual => { |
13126 | 0 | let v762 = C::unpack_value_array_2(ctx, v760); |
13127 | 0 | let v765 = C::value_type(ctx, v762.0); |
13128 | 0 | let v771 = C::ty_vec128(ctx, v765); |
13129 | 0 | if let Some(v772) = v771 { |
13130 | 0 | let v773 = constructor_put_in_xmm(ctx, v762.0); |
13131 | 0 | let v774 = &C::put_in_xmm_mem(ctx, v762.1); |
13132 | 0 | let v797 = constructor_x64_cmpp(ctx, v772, v773, v774, &FcmpImm::UnorderedOrGreaterThanOrEqual); |
13133 | 0 | let v798 = constructor_output_xmm(ctx, v797); |
13134 | 0 | // Rule at src/isa/x64/lower.isle line 1552. |
13135 | 0 | return Some(v798); |
13136 | 0 | } |
13137 | | } |
13138 | | &FloatCC::UnorderedOrLessThan => { |
13139 | 0 | let v762 = C::unpack_value_array_2(ctx, v760); |
13140 | 0 | let v765 = C::value_type(ctx, v762.0); |
13141 | 0 | let v771 = C::ty_vec128(ctx, v765); |
13142 | 0 | if let Some(v772) = v771 { |
13143 | 0 | let v799 = constructor_put_in_xmm(ctx, v762.1); |
13144 | 0 | let v800 = &C::put_in_xmm_mem(ctx, v762.0); |
13145 | 0 | let v805 = constructor_x64_cmpp(ctx, v772, v799, v800, &FcmpImm::UnorderedOrGreaterThan); |
13146 | 0 | let v806 = constructor_output_xmm(ctx, v805); |
13147 | 0 | // Rule at src/isa/x64/lower.isle line 1562. |
13148 | 0 | return Some(v806); |
13149 | 0 | } |
13150 | | } |
13151 | | &FloatCC::UnorderedOrLessThanOrEqual => { |
13152 | 0 | let v762 = C::unpack_value_array_2(ctx, v760); |
13153 | 0 | let v765 = C::value_type(ctx, v762.0); |
13154 | 0 | let v771 = C::ty_vec128(ctx, v765); |
13155 | 0 | if let Some(v772) = v771 { |
13156 | 0 | let v799 = constructor_put_in_xmm(ctx, v762.1); |
13157 | 0 | let v800 = &C::put_in_xmm_mem(ctx, v762.0); |
13158 | 0 | let v807 = constructor_x64_cmpp(ctx, v772, v799, v800, &FcmpImm::UnorderedOrGreaterThanOrEqual); |
13159 | 0 | let v808 = constructor_output_xmm(ctx, v807); |
13160 | 0 | // Rule at src/isa/x64/lower.isle line 1564. |
13161 | 0 | return Some(v808); |
13162 | 0 | } |
13163 | | } |
13164 | 0 | _ => {} |
13165 | | } |
13166 | 0 | let v762 = C::unpack_value_array_2(ctx, v760); |
13167 | 0 | let v765 = C::value_type(ctx, v762.0); |
13168 | 0 | let v766 = C::ty_scalar_float(ctx, v765); |
13169 | 0 | if let Some(v767) = v766 { |
13170 | 0 | let v768 = &constructor_emit_fcmp(ctx, v761, v762.0, v762.1); |
13171 | 0 | let v769 = constructor_lower_fcmp_bool(ctx, v768); |
13172 | 0 | let v770 = C::output(ctx, v769); |
13173 | 0 | // Rule at src/isa/x64/lower.isle line 1531. |
13174 | 0 | return Some(v770); |
13175 | 0 | } |
13176 | 0 | } |
13177 | | } |
13178 | | &InstructionData::FuncAddr { |
13179 | 0 | opcode: ref v1439, |
13180 | 0 | func_ref: v1440, |
13181 | 0 | } => { |
13182 | 0 | if let &Opcode::FuncAddr = v1439 { |
13183 | 0 | let v1441 = C::func_ref_data(ctx, v1440); |
13184 | 0 | let v1446 = constructor_load_ext_name(ctx, v1441.1, 0x0); |
13185 | 0 | let v1447 = constructor_output_reg(ctx, v1446); |
13186 | 0 | // Rule at src/isa/x64/lower.isle line 2713. |
13187 | 0 | return Some(v1447); |
13188 | 0 | } |
13189 | | } |
13190 | | &InstructionData::IntAddTrap { |
13191 | 0 | opcode: ref v622, |
13192 | 0 | args: ref v623, |
13193 | 0 | code: ref v624, |
13194 | 0 | } => { |
13195 | 0 | if let &Opcode::UaddOverflowTrap = v622 { |
13196 | 0 | let v1 = C::first_result(ctx, arg0); |
13197 | 0 | if let Some(v2) = v1 { |
13198 | 0 | let v3 = C::value_type(ctx, v2); |
13199 | 0 | let v4 = C::fits_in_64(ctx, v3); |
13200 | 0 | if let Some(v5) = v4 { |
13201 | 0 | let v625 = C::unpack_value_array_2(ctx, v623); |
13202 | 0 | let v641 = &C::sinkable_load(ctx, v625.0); |
13203 | 0 | if let Some(v642) = v641 { |
13204 | 0 | let v636 = constructor_put_in_gpr(ctx, v625.1); |
13205 | 0 | let v643 = &constructor_sink_load_to_gpr_mem_imm(ctx, v642); |
13206 | 0 | let v644 = &constructor_x64_add_with_flags_paired(ctx, v5, v636, v643); |
13207 | 0 | let v631 = &constructor_trap_if(ctx, &CC::B, v624); |
13208 | 0 | let v645 = constructor_with_flags(ctx, v644, v631); |
13209 | 0 | let v646 = C::output(ctx, v645); |
13210 | 0 | // Rule at src/isa/x64/lower.isle line 1384. |
13211 | 0 | return Some(v646); |
13212 | 0 | } |
13213 | 0 | let v634 = &C::simm32_from_value(ctx, v625.0); |
13214 | 0 | if let Some(v635) = v634 { |
13215 | 0 | let v636 = constructor_put_in_gpr(ctx, v625.1); |
13216 | 0 | let v637 = &constructor_x64_add_with_flags_paired(ctx, v5, v636, v635); |
13217 | 0 | let v638 = &constructor_trap_if(ctx, &CC::B, v624); |
13218 | 0 | let v639 = constructor_with_flags(ctx, v637, v638); |
13219 | 0 | let v640 = C::output(ctx, v639); |
13220 | 0 | // Rule at src/isa/x64/lower.isle line 1378. |
13221 | 0 | return Some(v640); |
13222 | 0 | } |
13223 | 0 | let v628 = constructor_put_in_gpr(ctx, v625.0); |
13224 | 0 | let v629 = &constructor_put_in_gpr_mem_imm(ctx, v625.1); |
13225 | 0 | let v630 = &constructor_x64_add_with_flags_paired(ctx, v5, v628, v629); |
13226 | 0 | let v631 = &constructor_trap_if(ctx, &CC::B, v624); |
13227 | 0 | let v632 = constructor_with_flags(ctx, v630, v631); |
13228 | 0 | let v633 = C::output(ctx, v632); |
13229 | 0 | // Rule at src/isa/x64/lower.isle line 1370. |
13230 | 0 | return Some(v633); |
13231 | 0 | } |
13232 | 0 | } |
13233 | 0 | } |
13234 | | } |
13235 | | &InstructionData::IntCompare { |
13236 | 8.50k | opcode: ref v653, |
13237 | 8.50k | args: ref v654, |
13238 | 8.50k | cond: ref v655, |
13239 | 8.50k | } => { |
13240 | 8.50k | if let &Opcode::Icmp = v653 { |
13241 | 8.50k | match v655 { |
13242 | | &IntCC::Equal => { |
13243 | 1.34k | let v656 = C::unpack_value_array_2(ctx, v654); |
13244 | 1.34k | let v659 = C::value_type(ctx, v656.0); |
13245 | 1.34k | let v707 = C::ty_vec128(ctx, v659); |
13246 | 1.34k | if let Some(v7080 ) = v707 { |
13247 | 0 | let v709 = constructor_put_in_xmm(ctx, v656.0); |
13248 | 0 | let v710 = &C::put_in_xmm_mem(ctx, v656.1); |
13249 | 0 | let v711 = constructor_x64_pcmpeq(ctx, v708, v709, v710); |
13250 | 0 | let v712 = constructor_output_xmm(ctx, v711); |
13251 | 0 | // Rule at src/isa/x64/lower.isle line 1446. |
13252 | 0 | return Some(v712); |
13253 | 1.34k | } |
13254 | | } |
13255 | | &IntCC::NotEqual => { |
13256 | 1.64k | let v656 = C::unpack_value_array_2(ctx, v654); |
13257 | 1.64k | let v659 = C::value_type(ctx, v656.0); |
13258 | 1.64k | let v707 = C::ty_vec128(ctx, v659); |
13259 | 1.64k | if let Some(v7080 ) = v707 { |
13260 | 0 | let v709 = constructor_put_in_xmm(ctx, v656.0); |
13261 | 0 | let v710 = &C::put_in_xmm_mem(ctx, v656.1); |
13262 | 0 | let v711 = constructor_x64_pcmpeq(ctx, v708, v709, v710); |
13263 | 0 | let v713 = constructor_vector_all_ones(ctx); |
13264 | 0 | let v714 = &C::xmm_to_xmm_mem(ctx, v713); |
13265 | 0 | let v715 = constructor_x64_pxor(ctx, v711, v714); |
13266 | 0 | let v716 = constructor_output_xmm(ctx, v715); |
13267 | 0 | // Rule at src/isa/x64/lower.isle line 1451. |
13268 | 0 | return Some(v716); |
13269 | 1.64k | } |
13270 | | } |
13271 | | &IntCC::SignedGreaterThan => { |
13272 | 35 | let v1 = C::first_result(ctx, arg0); |
13273 | 35 | if let Some(v2) = v1 { |
13274 | 35 | let v3 = C::value_type(ctx, v2); |
13275 | 35 | if v3 == I8 { |
13276 | 35 | let v656 = C::unpack_value_array_2(ctx, v654); |
13277 | 35 | let v677 = C::def_inst(ctx, v656.0); |
13278 | 35 | if let Some(v678) = v677 { |
13279 | 35 | let v679 = &C::inst_data(ctx, v678); |
13280 | | if let &InstructionData::UnaryImm { |
13281 | 0 | opcode: ref v680, |
13282 | 0 | imm: v681, |
13283 | 35 | } = v679 { |
13284 | 0 | if let &Opcode::Iconst = v680 { |
13285 | 0 | let v682 = C::u64_from_imm64(ctx, v681); |
13286 | 0 | if v682 == 0x0 { |
13287 | 0 | let v683 = C::value_type(ctx, v656.1); |
13288 | 0 | match v683 { |
13289 | | I32 => { |
13290 | 0 | let v684 = constructor_put_in_gpr(ctx, v656.1); |
13291 | 0 | let v696 = Imm8Reg::Imm8 { |
13292 | 0 | imm: 0x1F, |
13293 | 0 | }; |
13294 | 0 | let v697 = &C::imm8_reg_to_imm8_gpr(ctx, &v696); |
13295 | 0 | let v700 = constructor_x64_shr(ctx, I32, v684, v697); |
13296 | 0 | let v701 = constructor_output_gpr(ctx, v700); |
13297 | 0 | // Rule at src/isa/x64/lower.isle line 1430. |
13298 | 0 | return Some(v701); |
13299 | | } |
13300 | | I64 => { |
13301 | 0 | let v684 = constructor_put_in_gpr(ctx, v656.1); |
13302 | 0 | let v673 = Imm8Reg::Imm8 { |
13303 | 0 | imm: 0x3F, |
13304 | 0 | }; |
13305 | 0 | let v674 = &C::imm8_reg_to_imm8_gpr(ctx, &v673); |
13306 | 0 | let v685 = constructor_x64_shr(ctx, I64, v684, v674); |
13307 | 0 | let v686 = constructor_output_gpr(ctx, v685); |
13308 | 0 | // Rule at src/isa/x64/lower.isle line 1414. |
13309 | 0 | return Some(v686); |
13310 | | } |
13311 | 0 | _ => {} |
13312 | | } |
13313 | 0 | } |
13314 | 0 | } |
13315 | 35 | } |
13316 | 0 | } |
13317 | 0 | } |
13318 | 0 | } |
13319 | 35 | let v656 = C::unpack_value_array_2(ctx, v654); |
13320 | 35 | let v659 = C::value_type(ctx, v656.0); |
13321 | 35 | let v707 = C::ty_vec128(ctx, v659); |
13322 | 35 | if let Some(v7080 ) = v707 { |
13323 | 0 | let v709 = constructor_put_in_xmm(ctx, v656.0); |
13324 | 0 | let v710 = &C::put_in_xmm_mem(ctx, v656.1); |
13325 | 0 | let v717 = constructor_x64_pcmpgt(ctx, v708, v709, v710); |
13326 | 0 | let v718 = constructor_output_xmm(ctx, v717); |
13327 | 0 | // Rule at src/isa/x64/lower.isle line 1458. |
13328 | 0 | return Some(v718); |
13329 | 35 | } |
13330 | | } |
13331 | | &IntCC::SignedGreaterThanOrEqual => { |
13332 | 0 | let v656 = C::unpack_value_array_2(ctx, v654); |
13333 | 0 | let v659 = C::value_type(ctx, v656.0); |
13334 | 0 | match v659 { |
13335 | | I32 => { |
13336 | 0 | let v1 = C::first_result(ctx, arg0); |
13337 | 0 | if let Some(v2) = v1 { |
13338 | 0 | let v3 = C::value_type(ctx, v2); |
13339 | 0 | if v3 == I8 { |
13340 | 0 | let v665 = C::def_inst(ctx, v656.1); |
13341 | 0 | if let Some(v666) = v665 { |
13342 | 0 | let v667 = &C::inst_data(ctx, v666); |
13343 | | if let &InstructionData::UnaryImm { |
13344 | 0 | opcode: ref v668, |
13345 | 0 | imm: v669, |
13346 | 0 | } = v667 { |
13347 | 0 | if let &Opcode::Iconst = v668 { |
13348 | 0 | let v670 = C::u64_from_imm64(ctx, v669); |
13349 | 0 | if v670 == 0x0 { |
13350 | 0 | let v671 = constructor_put_in_gpr(ctx, v656.0); |
13351 | 0 | let v691 = constructor_x64_not(ctx, I64, v671); |
13352 | 0 | let v696 = Imm8Reg::Imm8 { |
13353 | 0 | imm: 0x1F, |
13354 | 0 | }; |
13355 | 0 | let v702 = &C::imm8_reg_to_imm8_gpr(ctx, &v696); |
13356 | 0 | let v705 = constructor_x64_shr(ctx, I32, v691, v702); |
13357 | 0 | let v706 = constructor_output_gpr(ctx, v705); |
13358 | 0 | // Rule at src/isa/x64/lower.isle line 1438. |
13359 | 0 | return Some(v706); |
13360 | 0 | } |
13361 | 0 | } |
13362 | 0 | } |
13363 | 0 | } |
13364 | 0 | } |
13365 | 0 | } |
13366 | | } |
13367 | | I64 => { |
13368 | 0 | let v1 = C::first_result(ctx, arg0); |
13369 | 0 | if let Some(v2) = v1 { |
13370 | 0 | let v3 = C::value_type(ctx, v2); |
13371 | 0 | if v3 == I8 { |
13372 | 0 | let v665 = C::def_inst(ctx, v656.1); |
13373 | 0 | if let Some(v666) = v665 { |
13374 | 0 | let v667 = &C::inst_data(ctx, v666); |
13375 | | if let &InstructionData::UnaryImm { |
13376 | 0 | opcode: ref v668, |
13377 | 0 | imm: v669, |
13378 | 0 | } = v667 { |
13379 | 0 | if let &Opcode::Iconst = v668 { |
13380 | 0 | let v670 = C::u64_from_imm64(ctx, v669); |
13381 | 0 | if v670 == 0x0 { |
13382 | 0 | let v671 = constructor_put_in_gpr(ctx, v656.0); |
13383 | 0 | let v691 = constructor_x64_not(ctx, I64, v671); |
13384 | 0 | let v673 = Imm8Reg::Imm8 { |
13385 | 0 | imm: 0x3F, |
13386 | 0 | }; |
13387 | 0 | let v688 = &C::imm8_reg_to_imm8_gpr(ctx, &v673); |
13388 | 0 | let v692 = constructor_x64_shr(ctx, I64, v691, v688); |
13389 | 0 | let v693 = constructor_output_gpr(ctx, v692); |
13390 | 0 | // Rule at src/isa/x64/lower.isle line 1422. |
13391 | 0 | return Some(v693); |
13392 | 0 | } |
13393 | 0 | } |
13394 | 0 | } |
13395 | 0 | } |
13396 | 0 | } |
13397 | 0 | } |
13398 | | } |
13399 | | I64X2 => { |
13400 | 0 | let v719 = constructor_put_in_xmm(ctx, v656.1); |
13401 | 0 | let v720 = &C::put_in_xmm_mem(ctx, v656.0); |
13402 | 0 | let v753 = constructor_x64_pcmpgt(ctx, I64X2, v719, v720); |
13403 | 0 | let v713 = constructor_vector_all_ones(ctx); |
13404 | 0 | let v714 = &C::xmm_to_xmm_mem(ctx, v713); |
13405 | 0 | let v754 = constructor_x64_pxor(ctx, v753, v714); |
13406 | 0 | let v755 = constructor_output_xmm(ctx, v754); |
13407 | 0 | // Rule at src/isa/x64/lower.isle line 1498. |
13408 | 0 | return Some(v755); |
13409 | | } |
13410 | 0 | _ => {} |
13411 | | } |
13412 | 0 | let v707 = C::ty_vec128(ctx, v659); |
13413 | 0 | if let Some(v708) = v707 { |
13414 | 0 | let v709 = constructor_put_in_xmm(ctx, v656.0); |
13415 | 0 | let v710 = &C::put_in_xmm_mem(ctx, v656.1); |
13416 | 0 | let v736 = constructor_x64_pmaxs(ctx, v708, v709, v710); |
13417 | 0 | let v737 = constructor_put_in_xmm(ctx, v656.0); |
13418 | 0 | let v738 = &C::xmm_to_xmm_mem(ctx, v736); |
13419 | 0 | let v739 = constructor_x64_pcmpeq(ctx, v708, v737, v738); |
13420 | 0 | let v740 = constructor_output_xmm(ctx, v739); |
13421 | 0 | // Rule at src/isa/x64/lower.isle line 1483. |
13422 | 0 | return Some(v740); |
13423 | 0 | } |
13424 | | } |
13425 | | &IntCC::SignedLessThan => { |
13426 | 15 | let v1 = C::first_result(ctx, arg0); |
13427 | 15 | if let Some(v2) = v1 { |
13428 | 15 | let v3 = C::value_type(ctx, v2); |
13429 | 15 | if v3 == I8 { |
13430 | 15 | let v656 = C::unpack_value_array_2(ctx, v654); |
13431 | 15 | let v659 = C::value_type(ctx, v656.0); |
13432 | 15 | match v659 { |
13433 | | I32 => { |
13434 | 15 | let v665 = C::def_inst(ctx, v656.1); |
13435 | 15 | if let Some(v66614 ) = v665 { |
13436 | 14 | let v667 = &C::inst_data(ctx, v666); |
13437 | | if let &InstructionData::UnaryImm { |
13438 | 8 | opcode: ref v668, |
13439 | 8 | imm: v669, |
13440 | 14 | } = v667 { |
13441 | 8 | if let &Opcode::Iconst = v668 { |
13442 | 8 | let v670 = C::u64_from_imm64(ctx, v669); |
13443 | 8 | if v670 == 0x0 { |
13444 | 8 | let v671 = constructor_put_in_gpr(ctx, v656.0); |
13445 | 8 | let v696 = Imm8Reg::Imm8 { |
13446 | 8 | imm: 0x1F, |
13447 | 8 | }; |
13448 | 8 | let v697 = &C::imm8_reg_to_imm8_gpr(ctx, &v696); |
13449 | 8 | let v698 = constructor_x64_shr(ctx, I32, v671, v697); |
13450 | 8 | let v699 = constructor_output_gpr(ctx, v698); |
13451 | 8 | // Rule at src/isa/x64/lower.isle line 1426. |
13452 | 8 | return Some(v699); |
13453 | 0 | } |
13454 | 0 | } |
13455 | 6 | } |
13456 | 1 | } |
13457 | | } |
13458 | | I64 => { |
13459 | 0 | let v665 = C::def_inst(ctx, v656.1); |
13460 | 0 | if let Some(v666) = v665 { |
13461 | 0 | let v667 = &C::inst_data(ctx, v666); |
13462 | | if let &InstructionData::UnaryImm { |
13463 | 0 | opcode: ref v668, |
13464 | 0 | imm: v669, |
13465 | 0 | } = v667 { |
13466 | 0 | if let &Opcode::Iconst = v668 { |
13467 | 0 | let v670 = C::u64_from_imm64(ctx, v669); |
13468 | 0 | if v670 == 0x0 { |
13469 | 0 | let v671 = constructor_put_in_gpr(ctx, v656.0); |
13470 | 0 | let v673 = Imm8Reg::Imm8 { |
13471 | 0 | imm: 0x3F, |
13472 | 0 | }; |
13473 | 0 | let v674 = &C::imm8_reg_to_imm8_gpr(ctx, &v673); |
13474 | 0 | let v675 = constructor_x64_shr(ctx, I64, v671, v674); |
13475 | 0 | let v676 = constructor_output_gpr(ctx, v675); |
13476 | 0 | // Rule at src/isa/x64/lower.isle line 1410. |
13477 | 0 | return Some(v676); |
13478 | 0 | } |
13479 | 0 | } |
13480 | 0 | } |
13481 | 0 | } |
13482 | | } |
13483 | 0 | _ => {} |
13484 | | } |
13485 | 0 | } |
13486 | 0 | } |
13487 | 7 | let v656 = C::unpack_value_array_2(ctx, v654); |
13488 | 7 | let v659 = C::value_type(ctx, v656.0); |
13489 | 7 | let v707 = C::ty_vec128(ctx, v659); |
13490 | 7 | if let Some(v7080 ) = v707 { |
13491 | 0 | let v719 = constructor_put_in_xmm(ctx, v656.1); |
13492 | 0 | let v720 = &C::put_in_xmm_mem(ctx, v656.0); |
13493 | 0 | let v721 = constructor_x64_pcmpgt(ctx, v708, v719, v720); |
13494 | 0 | let v722 = constructor_output_xmm(ctx, v721); |
13495 | 0 | // Rule at src/isa/x64/lower.isle line 1460. |
13496 | 0 | return Some(v722); |
13497 | 7 | } |
13498 | | } |
13499 | | &IntCC::SignedLessThanOrEqual => { |
13500 | 0 | let v1 = C::first_result(ctx, arg0); |
13501 | 0 | if let Some(v2) = v1 { |
13502 | 0 | let v3 = C::value_type(ctx, v2); |
13503 | 0 | if v3 == I8 { |
13504 | 0 | let v656 = C::unpack_value_array_2(ctx, v654); |
13505 | 0 | let v677 = C::def_inst(ctx, v656.0); |
13506 | 0 | if let Some(v678) = v677 { |
13507 | 0 | let v679 = &C::inst_data(ctx, v678); |
13508 | | if let &InstructionData::UnaryImm { |
13509 | 0 | opcode: ref v680, |
13510 | 0 | imm: v681, |
13511 | 0 | } = v679 { |
13512 | 0 | if let &Opcode::Iconst = v680 { |
13513 | 0 | let v682 = C::u64_from_imm64(ctx, v681); |
13514 | 0 | if v682 == 0x0 { |
13515 | 0 | let v683 = C::value_type(ctx, v656.1); |
13516 | 0 | match v683 { |
13517 | | I32 => { |
13518 | 0 | let v684 = constructor_put_in_gpr(ctx, v656.1); |
13519 | 0 | let v687 = constructor_x64_not(ctx, I64, v684); |
13520 | 0 | let v696 = Imm8Reg::Imm8 { |
13521 | 0 | imm: 0x1F, |
13522 | 0 | }; |
13523 | 0 | let v702 = &C::imm8_reg_to_imm8_gpr(ctx, &v696); |
13524 | 0 | let v703 = constructor_x64_shr(ctx, I32, v687, v702); |
13525 | 0 | let v704 = constructor_output_gpr(ctx, v703); |
13526 | 0 | // Rule at src/isa/x64/lower.isle line 1434. |
13527 | 0 | return Some(v704); |
13528 | | } |
13529 | | I64 => { |
13530 | 0 | let v684 = constructor_put_in_gpr(ctx, v656.1); |
13531 | 0 | let v687 = constructor_x64_not(ctx, I64, v684); |
13532 | 0 | let v673 = Imm8Reg::Imm8 { |
13533 | 0 | imm: 0x3F, |
13534 | 0 | }; |
13535 | 0 | let v688 = &C::imm8_reg_to_imm8_gpr(ctx, &v673); |
13536 | 0 | let v689 = constructor_x64_shr(ctx, I64, v687, v688); |
13537 | 0 | let v690 = constructor_output_gpr(ctx, v689); |
13538 | 0 | // Rule at src/isa/x64/lower.isle line 1418. |
13539 | 0 | return Some(v690); |
13540 | | } |
13541 | 0 | _ => {} |
13542 | | } |
13543 | 0 | } |
13544 | 0 | } |
13545 | 0 | } |
13546 | 0 | } |
13547 | 0 | } |
13548 | 0 | } |
13549 | 0 | let v656 = C::unpack_value_array_2(ctx, v654); |
13550 | 0 | let v659 = C::value_type(ctx, v656.0); |
13551 | 0 | if v659 == I64X2 { |
13552 | 0 | let v709 = constructor_put_in_xmm(ctx, v656.0); |
13553 | 0 | let v710 = &C::put_in_xmm_mem(ctx, v656.1); |
13554 | 0 | let v756 = constructor_x64_pcmpgt(ctx, I64X2, v709, v710); |
13555 | 0 | let v713 = constructor_vector_all_ones(ctx); |
13556 | 0 | let v714 = &C::xmm_to_xmm_mem(ctx, v713); |
13557 | 0 | let v757 = constructor_x64_pxor(ctx, v756, v714); |
13558 | 0 | let v758 = constructor_output_xmm(ctx, v757); |
13559 | 0 | // Rule at src/isa/x64/lower.isle line 1502. |
13560 | 0 | return Some(v758); |
13561 | 0 | } |
13562 | 0 | let v707 = C::ty_vec128(ctx, v659); |
13563 | 0 | if let Some(v708) = v707 { |
13564 | 0 | let v709 = constructor_put_in_xmm(ctx, v656.0); |
13565 | 0 | let v710 = &C::put_in_xmm_mem(ctx, v656.1); |
13566 | 0 | let v741 = constructor_x64_pmins(ctx, v708, v709, v710); |
13567 | 0 | let v737 = constructor_put_in_xmm(ctx, v656.0); |
13568 | 0 | let v742 = &C::xmm_to_xmm_mem(ctx, v741); |
13569 | 0 | let v743 = constructor_x64_pcmpeq(ctx, v708, v737, v742); |
13570 | 0 | let v744 = constructor_output_xmm(ctx, v743); |
13571 | 0 | // Rule at src/isa/x64/lower.isle line 1486. |
13572 | 0 | return Some(v744); |
13573 | 0 | } |
13574 | | } |
13575 | | &IntCC::UnsignedGreaterThan => { |
13576 | 1.24k | let v656 = C::unpack_value_array_2(ctx, v654); |
13577 | 1.24k | let v659 = C::value_type(ctx, v656.0); |
13578 | 1.24k | let v707 = C::ty_vec128(ctx, v659); |
13579 | 1.24k | if let Some(v7080 ) = v707 { |
13580 | 0 | let v709 = constructor_put_in_xmm(ctx, v656.0); |
13581 | 0 | let v723 = constructor_put_in_xmm(ctx, v656.1); |
13582 | 0 | let v724 = &C::xmm_to_xmm_mem(ctx, v723); |
13583 | 0 | let v725 = constructor_x64_pmaxu(ctx, v708, v709, v724); |
13584 | 0 | let v726 = &C::xmm_to_xmm_mem(ctx, v723); |
13585 | 0 | let v727 = constructor_x64_pcmpeq(ctx, v708, v725, v726); |
13586 | 0 | let v728 = constructor_vector_all_ones(ctx); |
13587 | 0 | let v729 = &C::xmm_to_xmm_mem(ctx, v728); |
13588 | 0 | let v730 = constructor_x64_pxor(ctx, v727, v729); |
13589 | 0 | let v731 = constructor_output_xmm(ctx, v730); |
13590 | 0 | // Rule at src/isa/x64/lower.isle line 1462. |
13591 | 0 | return Some(v731); |
13592 | 1.24k | } |
13593 | | } |
13594 | | &IntCC::UnsignedGreaterThanOrEqual => { |
13595 | 172 | let v656 = C::unpack_value_array_2(ctx, v654); |
13596 | 172 | let v659 = C::value_type(ctx, v656.0); |
13597 | 172 | let v707 = C::ty_vec128(ctx, v659); |
13598 | 172 | if let Some(v7080 ) = v707 { |
13599 | 0 | let v709 = constructor_put_in_xmm(ctx, v656.0); |
13600 | 0 | let v710 = &C::put_in_xmm_mem(ctx, v656.1); |
13601 | 0 | let v745 = constructor_x64_pmaxu(ctx, v708, v709, v710); |
13602 | 0 | let v737 = constructor_put_in_xmm(ctx, v656.0); |
13603 | 0 | let v746 = &C::xmm_to_xmm_mem(ctx, v745); |
13604 | 0 | let v747 = constructor_x64_pcmpeq(ctx, v708, v737, v746); |
13605 | 0 | let v748 = constructor_output_xmm(ctx, v747); |
13606 | 0 | // Rule at src/isa/x64/lower.isle line 1489. |
13607 | 0 | return Some(v748); |
13608 | 172 | } |
13609 | | } |
13610 | | &IntCC::UnsignedLessThan => { |
13611 | 3.87k | let v656 = C::unpack_value_array_2(ctx, v654); |
13612 | 3.87k | let v659 = C::value_type(ctx, v656.0); |
13613 | 3.87k | let v707 = C::ty_vec128(ctx, v659); |
13614 | 3.87k | if let Some(v7080 ) = v707 { |
13615 | 0 | let v709 = constructor_put_in_xmm(ctx, v656.0); |
13616 | 0 | let v723 = constructor_put_in_xmm(ctx, v656.1); |
13617 | 0 | let v724 = &C::xmm_to_xmm_mem(ctx, v723); |
13618 | 0 | let v732 = constructor_x64_pminu(ctx, v708, v709, v724); |
13619 | 0 | let v726 = &C::xmm_to_xmm_mem(ctx, v723); |
13620 | 0 | let v733 = constructor_x64_pcmpeq(ctx, v708, v732, v726); |
13621 | 0 | let v728 = constructor_vector_all_ones(ctx); |
13622 | 0 | let v729 = &C::xmm_to_xmm_mem(ctx, v728); |
13623 | 0 | let v734 = constructor_x64_pxor(ctx, v733, v729); |
13624 | 0 | let v735 = constructor_output_xmm(ctx, v734); |
13625 | 0 | // Rule at src/isa/x64/lower.isle line 1472. |
13626 | 0 | return Some(v735); |
13627 | 3.87k | } |
13628 | | } |
13629 | | &IntCC::UnsignedLessThanOrEqual => { |
13630 | 170 | let v656 = C::unpack_value_array_2(ctx, v654); |
13631 | 170 | let v659 = C::value_type(ctx, v656.0); |
13632 | 170 | let v707 = C::ty_vec128(ctx, v659); |
13633 | 170 | if let Some(v7080 ) = v707 { |
13634 | 0 | let v709 = constructor_put_in_xmm(ctx, v656.0); |
13635 | 0 | let v710 = &C::put_in_xmm_mem(ctx, v656.1); |
13636 | 0 | let v749 = constructor_x64_pminu(ctx, v708, v709, v710); |
13637 | 0 | let v737 = constructor_put_in_xmm(ctx, v656.0); |
13638 | 0 | let v750 = &C::xmm_to_xmm_mem(ctx, v749); |
13639 | 0 | let v751 = constructor_x64_pcmpeq(ctx, v708, v737, v750); |
13640 | 0 | let v752 = constructor_output_xmm(ctx, v751); |
13641 | 0 | // Rule at src/isa/x64/lower.isle line 1492. |
13642 | 0 | return Some(v752); |
13643 | 170 | } |
13644 | | } |
13645 | 0 | _ => {} |
13646 | | } |
13647 | 8.49k | let v656 = C::unpack_value_array_2(ctx, v654); |
13648 | 8.49k | let v659 = C::value_type(ctx, v656.0); |
13649 | 8.49k | if v659 == I128 { |
13650 | 0 | let v662 = &constructor_emit_cmp(ctx, v655, v656.0, v656.1); |
13651 | 0 | let v663 = constructor_lower_icmp_bool(ctx, v662); |
13652 | 0 | let v664 = C::output(ctx, v663); |
13653 | 0 | // Rule at src/isa/x64/lower.isle line 1406. |
13654 | 0 | return Some(v664); |
13655 | 8.49k | } |
13656 | 8.49k | let v660 = C::fits_in_64(ctx, v659); |
13657 | 8.49k | if let Some(v661) = v660 { |
13658 | 8.49k | let v662 = &constructor_emit_cmp(ctx, v655, v656.0, v656.1); |
13659 | 8.49k | let v663 = constructor_lower_icmp_bool(ctx, v662); |
13660 | 8.49k | let v664 = C::output(ctx, v663); |
13661 | 8.49k | // Rule at src/isa/x64/lower.isle line 1403. |
13662 | 8.49k | return Some(v664); |
13663 | 0 | } |
13664 | 0 | } |
13665 | | } |
13666 | | &InstructionData::Load { |
13667 | 623k | opcode: ref v1254, |
13668 | 623k | arg: v1255, |
13669 | 623k | flags: v1256, |
13670 | 623k | offset: v1257, |
13671 | 623k | } => { |
13672 | 623k | match v1254 { |
13673 | | &Opcode::Load => { |
13674 | 588k | let v1 = C::first_result(ctx, arg0); |
13675 | 588k | if let Some(v2) = v1 { |
13676 | 588k | let v3 = C::value_type(ctx, v2); |
13677 | 588k | match v3 { |
13678 | | F32 => { |
13679 | 0 | let v1267 = &constructor_to_amode(ctx, v1256, v1255, v1257); |
13680 | 0 | let v1286 = &C::amode_to_synthetic_amode(ctx, v1267); |
13681 | 0 | let v1287 = constructor_x64_movss_load(ctx, v1286); |
13682 | 0 | let v1288 = constructor_output_xmm(ctx, v1287); |
13683 | 0 | // Rule at src/isa/x64/lower.isle line 2425. |
13684 | 0 | return Some(v1288); |
13685 | | } |
13686 | | F64 => { |
13687 | 0 | let v1267 = &constructor_to_amode(ctx, v1256, v1255, v1257); |
13688 | 0 | let v1286 = &C::amode_to_synthetic_amode(ctx, v1267); |
13689 | 0 | let v1289 = constructor_x64_movsd_load(ctx, v1286); |
13690 | 0 | let v1290 = constructor_output_xmm(ctx, v1289); |
13691 | 0 | // Rule at src/isa/x64/lower.isle line 2427. |
13692 | 0 | return Some(v1290); |
13693 | | } |
13694 | | F32X4 => { |
13695 | 0 | let v1267 = &constructor_to_amode(ctx, v1256, v1255, v1257); |
13696 | 0 | let v1286 = &C::amode_to_synthetic_amode(ctx, v1267); |
13697 | 0 | let v1291 = constructor_x64_movups_load(ctx, v1286); |
13698 | 0 | let v1292 = constructor_output_xmm(ctx, v1291); |
13699 | 0 | // Rule at src/isa/x64/lower.isle line 2429. |
13700 | 0 | return Some(v1292); |
13701 | | } |
13702 | | F64X2 => { |
13703 | 0 | let v1267 = &constructor_to_amode(ctx, v1256, v1255, v1257); |
13704 | 0 | let v1286 = &C::amode_to_synthetic_amode(ctx, v1267); |
13705 | 0 | let v1293 = constructor_x64_movupd_load(ctx, v1286); |
13706 | 0 | let v1294 = constructor_output_xmm(ctx, v1293); |
13707 | 0 | // Rule at src/isa/x64/lower.isle line 2431. |
13708 | 0 | return Some(v1294); |
13709 | | } |
13710 | 588k | _ => {} |
13711 | 588k | } |
13712 | 588k | let v1265 = C::ty_int_ref_64(ctx, v3); |
13713 | 588k | if let Some(v1266297k ) = v1265 { |
13714 | 297k | let v1267 = &constructor_to_amode(ctx, v1256, v1255, v1257); |
13715 | 297k | let v1268 = constructor_x64_mov(ctx, v1267); |
13716 | 297k | let v1269 = constructor_output_reg(ctx, v1268); |
13717 | 297k | // Rule at src/isa/x64/lower.isle line 2403. |
13718 | 297k | return Some(v1269); |
13719 | 290k | } |
13720 | 290k | let v1295 = C::ty_vec128(ctx, v3); |
13721 | 290k | if let Some(v12960 ) = v1295 { |
13722 | 0 | let v1267 = &constructor_to_amode(ctx, v1256, v1255, v1257); |
13723 | 0 | let v1297 = &constructor_amode_to_xmm_mem(ctx, v1267); |
13724 | 0 | let v1298 = constructor_x64_movdqu_load(ctx, v1297); |
13725 | 0 | let v1299 = constructor_output_xmm(ctx, v1298); |
13726 | 0 | // Rule at src/isa/x64/lower.isle line 2433. |
13727 | 0 | return Some(v1299); |
13728 | 290k | } |
13729 | 290k | if v3 == I128 { |
13730 | 0 | let v1267 = &constructor_to_amode(ctx, v1256, v1255, v1257); |
13731 | 0 | let v1301 = &C::amode_offset(ctx, v1267, 0x8); |
13732 | 0 | let v1302 = constructor_x64_mov(ctx, v1267); |
13733 | 0 | let v1303 = constructor_x64_mov(ctx, v1301); |
13734 | 0 | let v1304 = C::value_regs(ctx, v1302, v1303); |
13735 | 0 | let v1305 = C::output(ctx, v1304); |
13736 | 0 | // Rule at src/isa/x64/lower.isle line 2437. |
13737 | 0 | return Some(v1305); |
13738 | 290k | } |
13739 | 290k | let v997 = C::fits_in_32(ctx, v3); |
13740 | 290k | if let Some(v998) = v997 { |
13741 | 290k | let v1251 = &C::type_register_class(ctx, v3); |
13742 | 290k | if let Some(v1252) = v1251 { |
13743 | | if let &RegisterClass::Gpr { |
13744 | 290k | single_register: v1253, |
13745 | 290k | } = v1252 { |
13746 | 290k | let v1258 = C::ty_bits_u16(ctx, v998); |
13747 | 290k | let v1260 = &C::ext_mode(ctx, v1258, 0x40); |
13748 | 290k | let v1261 = &constructor_to_amode(ctx, v1256, v1255, v1257); |
13749 | 290k | let v1262 = &constructor_amode_to_gpr_mem(ctx, v1261); |
13750 | 290k | let v1263 = constructor_x64_movzx(ctx, v1260, v1262); |
13751 | 290k | let v1264 = constructor_output_gpr(ctx, v1263); |
13752 | 290k | // Rule at src/isa/x64/lower.isle line 2399. |
13753 | 290k | return Some(v1264); |
13754 | 0 | } |
13755 | 0 | } |
13756 | 0 | } |
13757 | 0 | } |
13758 | | } |
13759 | | &Opcode::Uload8 => { |
13760 | 24.6k | let v1 = C::first_result(ctx, arg0); |
13761 | 24.6k | if let Some(v2) = v1 { |
13762 | 24.6k | let v3 = C::value_type(ctx, v2); |
13763 | 24.6k | let v1251 = &C::type_register_class(ctx, v3); |
13764 | 24.6k | if let Some(v1252) = v1251 { |
13765 | | if let &RegisterClass::Gpr { |
13766 | 24.6k | single_register: v1253, |
13767 | 24.6k | } = v1252 { |
13768 | 24.6k | let v1267 = &constructor_to_amode(ctx, v1256, v1255, v1257); |
13769 | 24.6k | let v1271 = &constructor_amode_to_gpr_mem(ctx, v1267); |
13770 | 24.6k | let v1272 = constructor_x64_movzx(ctx, &ExtMode::BQ, v1271); |
13771 | 24.6k | let v1273 = constructor_output_gpr(ctx, v1272); |
13772 | 24.6k | // Rule at src/isa/x64/lower.isle line 2408. |
13773 | 24.6k | return Some(v1273); |
13774 | 0 | } |
13775 | 0 | } |
13776 | 0 | } |
13777 | | } |
13778 | | &Opcode::Sload8 => { |
13779 | 99 | let v1 = C::first_result(ctx, arg0); |
13780 | 99 | if let Some(v2) = v1 { |
13781 | 99 | let v3 = C::value_type(ctx, v2); |
13782 | 99 | let v1251 = &C::type_register_class(ctx, v3); |
13783 | 99 | if let Some(v1252) = v1251 { |
13784 | | if let &RegisterClass::Gpr { |
13785 | 99 | single_register: v1253, |
13786 | 99 | } = v1252 { |
13787 | 99 | let v1267 = &constructor_to_amode(ctx, v1256, v1255, v1257); |
13788 | 99 | let v1271 = &constructor_amode_to_gpr_mem(ctx, v1267); |
13789 | 99 | let v1274 = constructor_x64_movsx(ctx, &ExtMode::BQ, v1271); |
13790 | 99 | let v1275 = constructor_output_gpr(ctx, v1274); |
13791 | 99 | // Rule at src/isa/x64/lower.isle line 2410. |
13792 | 99 | return Some(v1275); |
13793 | 0 | } |
13794 | 0 | } |
13795 | 0 | } |
13796 | | } |
13797 | | &Opcode::Uload16 => { |
13798 | 9.23k | let v1 = C::first_result(ctx, arg0); |
13799 | 9.23k | if let Some(v2) = v1 { |
13800 | 9.23k | let v3 = C::value_type(ctx, v2); |
13801 | 9.23k | let v1251 = &C::type_register_class(ctx, v3); |
13802 | 9.23k | if let Some(v1252) = v1251 { |
13803 | | if let &RegisterClass::Gpr { |
13804 | 9.23k | single_register: v1253, |
13805 | 9.23k | } = v1252 { |
13806 | 9.23k | let v1267 = &constructor_to_amode(ctx, v1256, v1255, v1257); |
13807 | 9.23k | let v1271 = &constructor_amode_to_gpr_mem(ctx, v1267); |
13808 | 9.23k | let v1277 = constructor_x64_movzx(ctx, &ExtMode::WQ, v1271); |
13809 | 9.23k | let v1278 = constructor_output_gpr(ctx, v1277); |
13810 | 9.23k | // Rule at src/isa/x64/lower.isle line 2412. |
13811 | 9.23k | return Some(v1278); |
13812 | 0 | } |
13813 | 0 | } |
13814 | 0 | } |
13815 | | } |
13816 | | &Opcode::Sload16 => { |
13817 | 0 | let v1 = C::first_result(ctx, arg0); |
13818 | 0 | if let Some(v2) = v1 { |
13819 | 0 | let v3 = C::value_type(ctx, v2); |
13820 | 0 | let v1251 = &C::type_register_class(ctx, v3); |
13821 | 0 | if let Some(v1252) = v1251 { |
13822 | | if let &RegisterClass::Gpr { |
13823 | 0 | single_register: v1253, |
13824 | 0 | } = v1252 { |
13825 | 0 | let v1267 = &constructor_to_amode(ctx, v1256, v1255, v1257); |
13826 | 0 | let v1271 = &constructor_amode_to_gpr_mem(ctx, v1267); |
13827 | 0 | let v1279 = constructor_x64_movsx(ctx, &ExtMode::WQ, v1271); |
13828 | 0 | let v1280 = constructor_output_gpr(ctx, v1279); |
13829 | 0 | // Rule at src/isa/x64/lower.isle line 2414. |
13830 | 0 | return Some(v1280); |
13831 | 0 | } |
13832 | 0 | } |
13833 | 0 | } |
13834 | | } |
13835 | | &Opcode::Uload32 => { |
13836 | 654 | let v1 = C::first_result(ctx, arg0); |
13837 | 654 | if let Some(v2) = v1 { |
13838 | 654 | let v3 = C::value_type(ctx, v2); |
13839 | 654 | let v1251 = &C::type_register_class(ctx, v3); |
13840 | 654 | if let Some(v1252) = v1251 { |
13841 | | if let &RegisterClass::Gpr { |
13842 | 654 | single_register: v1253, |
13843 | 654 | } = v1252 { |
13844 | 654 | let v1267 = &constructor_to_amode(ctx, v1256, v1255, v1257); |
13845 | 654 | let v1271 = &constructor_amode_to_gpr_mem(ctx, v1267); |
13846 | 654 | let v1282 = constructor_x64_movzx(ctx, &ExtMode::LQ, v1271); |
13847 | 654 | let v1283 = constructor_output_gpr(ctx, v1282); |
13848 | 654 | // Rule at src/isa/x64/lower.isle line 2416. |
13849 | 654 | return Some(v1283); |
13850 | 0 | } |
13851 | 0 | } |
13852 | 0 | } |
13853 | | } |
13854 | | &Opcode::Sload32 => { |
13855 | 0 | let v1 = C::first_result(ctx, arg0); |
13856 | 0 | if let Some(v2) = v1 { |
13857 | 0 | let v3 = C::value_type(ctx, v2); |
13858 | 0 | let v1251 = &C::type_register_class(ctx, v3); |
13859 | 0 | if let Some(v1252) = v1251 { |
13860 | | if let &RegisterClass::Gpr { |
13861 | 0 | single_register: v1253, |
13862 | 0 | } = v1252 { |
13863 | 0 | let v1267 = &constructor_to_amode(ctx, v1256, v1255, v1257); |
13864 | 0 | let v1271 = &constructor_amode_to_gpr_mem(ctx, v1267); |
13865 | 0 | let v1284 = constructor_x64_movsx(ctx, &ExtMode::LQ, v1271); |
13866 | 0 | let v1285 = constructor_output_gpr(ctx, v1284); |
13867 | 0 | // Rule at src/isa/x64/lower.isle line 2418. |
13868 | 0 | return Some(v1285); |
13869 | 0 | } |
13870 | 0 | } |
13871 | 0 | } |
13872 | | } |
13873 | | &Opcode::Uload8x8 => { |
13874 | 0 | let v1 = C::first_result(ctx, arg0); |
13875 | 0 | if let Some(v2) = v1 { |
13876 | 0 | let v3 = C::value_type(ctx, v2); |
13877 | 0 | if v3 == I16X8 { |
13878 | 0 | let v1267 = &constructor_to_amode(ctx, v1256, v1255, v1257); |
13879 | 0 | let v1297 = &constructor_amode_to_xmm_mem(ctx, v1267); |
13880 | 0 | let v1308 = constructor_x64_pmovzxbw(ctx, v1297); |
13881 | 0 | let v1309 = constructor_output_xmm(ctx, v1308); |
13882 | 0 | // Rule at src/isa/x64/lower.isle line 2449. |
13883 | 0 | return Some(v1309); |
13884 | 0 | } |
13885 | 0 | } |
13886 | | } |
13887 | | &Opcode::Sload8x8 => { |
13888 | 0 | let v1 = C::first_result(ctx, arg0); |
13889 | 0 | if let Some(v2) = v1 { |
13890 | 0 | let v3 = C::value_type(ctx, v2); |
13891 | 0 | if v3 == I16X8 { |
13892 | 0 | let v1267 = &constructor_to_amode(ctx, v1256, v1255, v1257); |
13893 | 0 | let v1297 = &constructor_amode_to_xmm_mem(ctx, v1267); |
13894 | 0 | let v1306 = constructor_x64_pmovsxbw(ctx, v1297); |
13895 | 0 | let v1307 = constructor_output_xmm(ctx, v1306); |
13896 | 0 | // Rule at src/isa/x64/lower.isle line 2447. |
13897 | 0 | return Some(v1307); |
13898 | 0 | } |
13899 | 0 | } |
13900 | | } |
13901 | | &Opcode::Uload16x4 => { |
13902 | 0 | let v1 = C::first_result(ctx, arg0); |
13903 | 0 | if let Some(v2) = v1 { |
13904 | 0 | let v3 = C::value_type(ctx, v2); |
13905 | 0 | if v3 == I32X4 { |
13906 | 0 | let v1267 = &constructor_to_amode(ctx, v1256, v1255, v1257); |
13907 | 0 | let v1297 = &constructor_amode_to_xmm_mem(ctx, v1267); |
13908 | 0 | let v1312 = constructor_x64_pmovzxwd(ctx, v1297); |
13909 | 0 | let v1313 = constructor_output_xmm(ctx, v1312); |
13910 | 0 | // Rule at src/isa/x64/lower.isle line 2453. |
13911 | 0 | return Some(v1313); |
13912 | 0 | } |
13913 | 0 | } |
13914 | | } |
13915 | | &Opcode::Sload16x4 => { |
13916 | 0 | let v1 = C::first_result(ctx, arg0); |
13917 | 0 | if let Some(v2) = v1 { |
13918 | 0 | let v3 = C::value_type(ctx, v2); |
13919 | 0 | if v3 == I32X4 { |
13920 | 0 | let v1267 = &constructor_to_amode(ctx, v1256, v1255, v1257); |
13921 | 0 | let v1297 = &constructor_amode_to_xmm_mem(ctx, v1267); |
13922 | 0 | let v1310 = constructor_x64_pmovsxwd(ctx, v1297); |
13923 | 0 | let v1311 = constructor_output_xmm(ctx, v1310); |
13924 | 0 | // Rule at src/isa/x64/lower.isle line 2451. |
13925 | 0 | return Some(v1311); |
13926 | 0 | } |
13927 | 0 | } |
13928 | | } |
13929 | | &Opcode::Uload32x2 => { |
13930 | 0 | let v1 = C::first_result(ctx, arg0); |
13931 | 0 | if let Some(v2) = v1 { |
13932 | 0 | let v3 = C::value_type(ctx, v2); |
13933 | 0 | if v3 == I64X2 { |
13934 | 0 | let v1267 = &constructor_to_amode(ctx, v1256, v1255, v1257); |
13935 | 0 | let v1297 = &constructor_amode_to_xmm_mem(ctx, v1267); |
13936 | 0 | let v1316 = constructor_x64_pmovzxdq(ctx, v1297); |
13937 | 0 | let v1317 = constructor_output_xmm(ctx, v1316); |
13938 | 0 | // Rule at src/isa/x64/lower.isle line 2457. |
13939 | 0 | return Some(v1317); |
13940 | 0 | } |
13941 | 0 | } |
13942 | | } |
13943 | | &Opcode::Sload32x2 => { |
13944 | 0 | let v1 = C::first_result(ctx, arg0); |
13945 | 0 | if let Some(v2) = v1 { |
13946 | 0 | let v3 = C::value_type(ctx, v2); |
13947 | 0 | if v3 == I64X2 { |
13948 | 0 | let v1267 = &constructor_to_amode(ctx, v1256, v1255, v1257); |
13949 | 0 | let v1297 = &constructor_amode_to_xmm_mem(ctx, v1267); |
13950 | 0 | let v1314 = constructor_x64_pmovsxdq(ctx, v1297); |
13951 | 0 | let v1315 = constructor_output_xmm(ctx, v1314); |
13952 | 0 | // Rule at src/isa/x64/lower.isle line 2455. |
13953 | 0 | return Some(v1315); |
13954 | 0 | } |
13955 | 0 | } |
13956 | | } |
13957 | 0 | _ => {} |
13958 | | } |
13959 | | } |
13960 | | &InstructionData::LoadNoOffset { |
13961 | 0 | opcode: ref v1457, |
13962 | 0 | arg: v1458, |
13963 | 0 | flags: v1459, |
13964 | 0 | } => { |
13965 | 0 | match v1457 { |
13966 | | &Opcode::Bitcast => { |
13967 | 0 | let v1 = C::first_result(ctx, arg0); |
13968 | 0 | if let Some(v2) = v1 { |
13969 | 0 | let v3 = C::value_type(ctx, v2); |
13970 | 0 | let v1251 = &C::type_register_class(ctx, v3); |
13971 | 0 | if let Some(v1252) = v1251 { |
13972 | 0 | match v1252 { |
13973 | | &RegisterClass::Gpr { |
13974 | 0 | single_register: v1253, |
13975 | 0 | } => { |
13976 | 0 | let v1783 = C::value_type(ctx, v1458); |
13977 | 0 | let v1794 = &C::type_register_class(ctx, v1783); |
13978 | 0 | if let Some(v1795) = v1794 { |
13979 | | if let &RegisterClass::Gpr { |
13980 | 0 | single_register: v1796, |
13981 | 0 | } = v1795 { |
13982 | 0 | let v1797 = constructor_output_value(ctx, v1458); |
13983 | 0 | // Rule at src/isa/x64/lower.isle line 3266. |
13984 | 0 | return Some(v1797); |
13985 | 0 | } |
13986 | 0 | } |
13987 | | } |
13988 | | &RegisterClass::Xmm => { |
13989 | 0 | let v1783 = C::value_type(ctx, v1458); |
13990 | 0 | let v1794 = &C::type_register_class(ctx, v1783); |
13991 | 0 | if let Some(v1795) = v1794 { |
13992 | 0 | if let &RegisterClass::Xmm = v1795 { |
13993 | 0 | let v1797 = constructor_output_value(ctx, v1458); |
13994 | 0 | // Rule at src/isa/x64/lower.isle line 3270. |
13995 | 0 | return Some(v1797); |
13996 | 0 | } |
13997 | 0 | } |
13998 | | } |
13999 | 0 | _ => {} |
14000 | | } |
14001 | 0 | } |
14002 | 0 | match v3 { |
14003 | | I32 => { |
14004 | 0 | let v1783 = C::value_type(ctx, v1458); |
14005 | 0 | if v1783 == F32 { |
14006 | 0 | let v1784 = constructor_put_in_xmm(ctx, v1458); |
14007 | 0 | let v1785 = constructor_bitcast_xmm_to_gpr(ctx, F32, v1784); |
14008 | 0 | let v1786 = constructor_output_gpr(ctx, v1785); |
14009 | 0 | // Rule at src/isa/x64/lower.isle line 3253. |
14010 | 0 | return Some(v1786); |
14011 | 0 | } |
14012 | | } |
14013 | | I64 => { |
14014 | 0 | let v1783 = C::value_type(ctx, v1458); |
14015 | 0 | if v1783 == F64 { |
14016 | 0 | let v1784 = constructor_put_in_xmm(ctx, v1458); |
14017 | 0 | let v1790 = constructor_bitcast_xmm_to_gpr(ctx, F64, v1784); |
14018 | 0 | let v1791 = constructor_output_gpr(ctx, v1790); |
14019 | 0 | // Rule at src/isa/x64/lower.isle line 3259. |
14020 | 0 | return Some(v1791); |
14021 | 0 | } |
14022 | | } |
14023 | | F32 => { |
14024 | 0 | let v1783 = C::value_type(ctx, v1458); |
14025 | 0 | if v1783 == I32 { |
14026 | 0 | let v1787 = constructor_put_in_gpr(ctx, v1458); |
14027 | 0 | let v1788 = constructor_bitcast_gpr_to_xmm(ctx, I32, v1787); |
14028 | 0 | let v1789 = constructor_output_xmm(ctx, v1788); |
14029 | 0 | // Rule at src/isa/x64/lower.isle line 3256. |
14030 | 0 | return Some(v1789); |
14031 | 0 | } |
14032 | | } |
14033 | | F64 => { |
14034 | 0 | let v1783 = C::value_type(ctx, v1458); |
14035 | 0 | if v1783 == I64 { |
14036 | 0 | let v1787 = constructor_put_in_gpr(ctx, v1458); |
14037 | 0 | let v1792 = constructor_bitcast_gpr_to_xmm(ctx, I64, v1787); |
14038 | 0 | let v1793 = constructor_output_xmm(ctx, v1792); |
14039 | 0 | // Rule at src/isa/x64/lower.isle line 3262. |
14040 | 0 | return Some(v1793); |
14041 | 0 | } |
14042 | | } |
14043 | 0 | _ => {} |
14044 | | } |
14045 | 0 | } |
14046 | | } |
14047 | | &Opcode::AtomicLoad => { |
14048 | 0 | let v1 = C::first_result(ctx, arg0); |
14049 | 0 | if let Some(v2) = v1 { |
14050 | 0 | let v3 = C::value_type(ctx, v2); |
14051 | 0 | if v3 == I64 { |
14052 | 0 | let v48 = C::zero_offset(ctx); |
14053 | 0 | let v1460 = &constructor_to_amode(ctx, v1459, v1458, v48); |
14054 | 0 | let v1461 = constructor_x64_mov(ctx, v1460); |
14055 | 0 | let v1462 = constructor_output_reg(ctx, v1461); |
14056 | 0 | // Rule at src/isa/x64/lower.isle line 2730. |
14057 | 0 | return Some(v1462); |
14058 | 0 | } |
14059 | 0 | let v997 = C::fits_in_32(ctx, v3); |
14060 | 0 | if let Some(v998) = v997 { |
14061 | 0 | let v1463 = C::ty_int(ctx, v3); |
14062 | 0 | if let Some(v1464) = v1463 { |
14063 | 0 | let v1258 = C::ty_bits_u16(ctx, v998); |
14064 | 0 | let v1260 = &C::ext_mode(ctx, v1258, 0x40); |
14065 | 0 | let v1465 = C::zero_offset(ctx); |
14066 | 0 | let v1466 = &constructor_to_amode(ctx, v1459, v1458, v1465); |
14067 | 0 | let v1467 = &constructor_amode_to_gpr_mem(ctx, v1466); |
14068 | 0 | let v1468 = constructor_x64_movzx(ctx, v1260, v1467); |
14069 | 0 | let v1469 = constructor_output_gpr(ctx, v1468); |
14070 | 0 | // Rule at src/isa/x64/lower.isle line 2732. |
14071 | 0 | return Some(v1469); |
14072 | 0 | } |
14073 | 0 | } |
14074 | 0 | } |
14075 | | } |
14076 | 0 | _ => {} |
14077 | | } |
14078 | | } |
14079 | | &InstructionData::MultiAry { |
14080 | 14.3k | opcode: ref v647, |
14081 | 14.3k | args: v648, |
14082 | 14.3k | } => { |
14083 | 14.3k | if let &Opcode::Return = v647 { |
14084 | 14.3k | let v649 = C::value_list_slice(ctx, v648); |
14085 | 14.3k | let v650 = C::value_slice_len(ctx, v649); |
14086 | 14.3k | let v651 = C::range(ctx, 0x0, v650); |
14087 | 14.3k | let v652 = constructor_lower_return(ctx, v651, v649); |
14088 | 14.3k | // Rule at src/isa/x64/lower.isle line 1398. |
14089 | 14.3k | return Some(v652); |
14090 | 0 | } |
14091 | | } |
14092 | | &InstructionData::NullAry { |
14093 | 0 | opcode: ref v31, |
14094 | 0 | } => { |
14095 | 0 | match v31 { |
14096 | | &Opcode::Debugtrap => { |
14097 | 0 | let v1011 = &constructor_x64_hlt(ctx); |
14098 | 0 | let v1012 = constructor_side_effect(ctx, v1011); |
14099 | 0 | // Rule at src/isa/x64/lower.isle line 2020. |
14100 | 0 | return Some(v1012); |
14101 | | } |
14102 | | &Opcode::GetPinnedReg => { |
14103 | 0 | let v1958 = constructor_read_pinned_gpr(ctx); |
14104 | 0 | let v1959 = constructor_output_gpr(ctx, v1958); |
14105 | 0 | // Rule at src/isa/x64/lower.isle line 3538. |
14106 | 0 | return Some(v1959); |
14107 | | } |
14108 | | &Opcode::GetFramePointer => { |
14109 | 0 | let v1533 = constructor_x64_rbp(ctx); |
14110 | 0 | let v1534 = constructor_output_reg(ctx, v1533); |
14111 | 0 | // Rule at src/isa/x64/lower.isle line 2779. |
14112 | 0 | return Some(v1534); |
14113 | | } |
14114 | | &Opcode::GetStackPointer => { |
14115 | 0 | let v1535 = constructor_x64_rsp(ctx); |
14116 | 0 | let v1536 = constructor_output_reg(ctx, v1535); |
14117 | 0 | // Rule at src/isa/x64/lower.isle line 2782. |
14118 | 0 | return Some(v1536); |
14119 | | } |
14120 | | &Opcode::GetReturnAddress => { |
14121 | 0 | let v1533 = constructor_x64_rbp(ctx); |
14122 | 0 | let v47 = C::mem_flags_trusted(ctx); |
14123 | 0 | let v1537 = Amode::ImmReg { |
14124 | 0 | simm32: 0x8, |
14125 | 0 | base: v1533, |
14126 | 0 | flags: v47, |
14127 | 0 | }; |
14128 | 0 | let v1538 = &C::amode_to_synthetic_amode(ctx, &v1537); |
14129 | 0 | let v1539 = constructor_x64_load(ctx, I64, v1538, &ExtKind::None); |
14130 | 0 | let v1540 = constructor_output_reg(ctx, v1539); |
14131 | 0 | // Rule at src/isa/x64/lower.isle line 2785. |
14132 | 0 | return Some(v1540); |
14133 | | } |
14134 | | &Opcode::Null => { |
14135 | 0 | let v1 = C::first_result(ctx, arg0); |
14136 | 0 | if let Some(v2) = v1 { |
14137 | 0 | let v3 = C::value_type(ctx, v2); |
14138 | 0 | let v32 = constructor_imm(ctx, v3, 0x0); |
14139 | 0 | let v33 = constructor_output_reg(ctx, v32); |
14140 | 0 | // Rule at src/isa/x64/lower.isle line 37. |
14141 | 0 | return Some(v33); |
14142 | 0 | } |
14143 | | } |
14144 | | &Opcode::Nop => { |
14145 | 0 | let v2247 = C::invalid_reg(ctx); |
14146 | 0 | let v2248 = constructor_output_reg(ctx, v2247); |
14147 | 0 | // Rule at src/isa/x64/lower.isle line 3983. |
14148 | 0 | return Some(v2248); |
14149 | | } |
14150 | | &Opcode::Fence => { |
14151 | 0 | let v1437 = &constructor_x64_mfence(ctx); |
14152 | 0 | let v1438 = constructor_side_effect(ctx, v1437); |
14153 | 0 | // Rule at src/isa/x64/lower.isle line 2708. |
14154 | 0 | return Some(v1438); |
14155 | | } |
14156 | 0 | _ => {} |
14157 | | } |
14158 | | } |
14159 | | &InstructionData::Shuffle { |
14160 | 0 | opcode: ref v1967, |
14161 | 0 | args: ref v1968, |
14162 | 0 | imm: v1969, |
14163 | 0 | } => { |
14164 | 0 | if let &Opcode::Shuffle = v1967 { |
14165 | 0 | let v1973 = C::pblendw_imm(ctx, v1969); |
14166 | 0 | if let Some(v1974) = v1973 { |
14167 | 0 | let v1970 = C::unpack_value_array_2(ctx, v1968); |
14168 | 0 | let v1975 = constructor_put_in_xmm(ctx, v1970.0); |
14169 | 0 | let v1976 = &C::put_in_xmm_mem(ctx, v1970.1); |
14170 | 0 | let v1977 = constructor_x64_pblendw(ctx, v1975, v1976, v1974); |
14171 | 0 | let v1978 = constructor_output_xmm(ctx, v1977); |
14172 | 0 | // Rule at src/isa/x64/lower.isle line 3558. |
14173 | 0 | return Some(v1978); |
14174 | 0 | } |
14175 | 0 | let v1979 = C::palignr_imm_from_immediate(ctx, v1969); |
14176 | 0 | if let Some(v1980) = v1979 { |
14177 | 0 | let v1970 = C::unpack_value_array_2(ctx, v1968); |
14178 | 0 | let v1981 = constructor_put_in_xmm(ctx, v1970.1); |
14179 | 0 | let v1982 = &C::put_in_xmm_mem(ctx, v1970.0); |
14180 | 0 | let v1983 = constructor_x64_palignr(ctx, v1981, v1982, v1980); |
14181 | 0 | let v1984 = constructor_output_xmm(ctx, v1983); |
14182 | 0 | // Rule at src/isa/x64/lower.isle line 3568. |
14183 | 0 | return Some(v1984); |
14184 | 0 | } |
14185 | 0 | let v1985 = C::pshuflw_lhs_imm(ctx, v1969); |
14186 | 0 | if let Some(v1986) = v1985 { |
14187 | 0 | let v1970 = C::unpack_value_array_2(ctx, v1968); |
14188 | 0 | let v1987 = &C::put_in_xmm_mem(ctx, v1970.0); |
14189 | 0 | let v1988 = constructor_x64_pshuflw(ctx, v1987, v1986); |
14190 | 0 | let v1989 = constructor_output_xmm(ctx, v1988); |
14191 | 0 | // Rule at src/isa/x64/lower.isle line 3579. |
14192 | 0 | return Some(v1989); |
14193 | 0 | } |
14194 | 0 | let v1990 = C::pshuflw_rhs_imm(ctx, v1969); |
14195 | 0 | if let Some(v1991) = v1990 { |
14196 | 0 | let v1970 = C::unpack_value_array_2(ctx, v1968); |
14197 | 0 | let v1992 = &C::put_in_xmm_mem(ctx, v1970.1); |
14198 | 0 | let v1993 = constructor_x64_pshuflw(ctx, v1992, v1991); |
14199 | 0 | let v1994 = constructor_output_xmm(ctx, v1993); |
14200 | 0 | // Rule at src/isa/x64/lower.isle line 3581. |
14201 | 0 | return Some(v1994); |
14202 | 0 | } |
14203 | 0 | let v1995 = C::pshufhw_lhs_imm(ctx, v1969); |
14204 | 0 | if let Some(v1996) = v1995 { |
14205 | 0 | let v1970 = C::unpack_value_array_2(ctx, v1968); |
14206 | 0 | let v1987 = &C::put_in_xmm_mem(ctx, v1970.0); |
14207 | 0 | let v1997 = constructor_x64_pshufhw(ctx, v1987, v1996); |
14208 | 0 | let v1998 = constructor_output_xmm(ctx, v1997); |
14209 | 0 | // Rule at src/isa/x64/lower.isle line 3583. |
14210 | 0 | return Some(v1998); |
14211 | 0 | } |
14212 | 0 | let v1999 = C::pshufhw_rhs_imm(ctx, v1969); |
14213 | 0 | if let Some(v2000) = v1999 { |
14214 | 0 | let v1970 = C::unpack_value_array_2(ctx, v1968); |
14215 | 0 | let v1992 = &C::put_in_xmm_mem(ctx, v1970.1); |
14216 | 0 | let v2001 = constructor_x64_pshufhw(ctx, v1992, v2000); |
14217 | 0 | let v2002 = constructor_output_xmm(ctx, v2001); |
14218 | 0 | // Rule at src/isa/x64/lower.isle line 3585. |
14219 | 0 | return Some(v2002); |
14220 | 0 | } |
14221 | 0 | let v2003 = C::pshufd_lhs_imm(ctx, v1969); |
14222 | 0 | if let Some(v2004) = v2003 { |
14223 | 0 | let v1970 = C::unpack_value_array_2(ctx, v1968); |
14224 | 0 | let v1987 = &C::put_in_xmm_mem(ctx, v1970.0); |
14225 | 0 | let v2005 = constructor_x64_pshufd(ctx, v1987, v2004); |
14226 | 0 | let v2006 = constructor_output_xmm(ctx, v2005); |
14227 | 0 | // Rule at src/isa/x64/lower.isle line 3602. |
14228 | 0 | return Some(v2006); |
14229 | 0 | } |
14230 | 0 | let v2007 = C::pshufd_rhs_imm(ctx, v1969); |
14231 | 0 | if let Some(v2008) = v2007 { |
14232 | 0 | let v1970 = C::unpack_value_array_2(ctx, v1968); |
14233 | 0 | let v1992 = &C::put_in_xmm_mem(ctx, v1970.1); |
14234 | 0 | let v2009 = constructor_x64_pshufd(ctx, v1992, v2008); |
14235 | 0 | let v2010 = constructor_output_xmm(ctx, v2009); |
14236 | 0 | // Rule at src/isa/x64/lower.isle line 3604. |
14237 | 0 | return Some(v2010); |
14238 | 0 | } |
14239 | 0 | let v2011 = C::u128_from_immediate(ctx, v1969); |
14240 | 0 | if let Some(v2012) = v2011 { |
14241 | 0 | match v2012 { |
14242 | | 0x0 => { |
14243 | 0 | let v1970 = C::unpack_value_array_2(ctx, v1968); |
14244 | 0 | let v1975 = constructor_put_in_xmm(ctx, v1970.0); |
14245 | 0 | let v2029 = constructor_xmm_zero(ctx, I8X16); |
14246 | 0 | let v2030 = &C::xmm_to_xmm_mem(ctx, v2029); |
14247 | 0 | let v2031 = constructor_x64_pshufb(ctx, v1975, v2030); |
14248 | 0 | let v2032 = constructor_output_xmm(ctx, v2031); |
14249 | 0 | // Rule at src/isa/x64/lower.isle line 3641. |
14250 | 0 | return Some(v2032); |
14251 | | } |
14252 | | 0x17071606150514041303120211011000 => { |
14253 | 0 | let v1970 = C::unpack_value_array_2(ctx, v1968); |
14254 | 0 | let v1975 = constructor_put_in_xmm(ctx, v1970.0); |
14255 | 0 | let v1976 = &C::put_in_xmm_mem(ctx, v1970.1); |
14256 | 0 | let v2015 = constructor_x64_punpcklbw(ctx, v1975, v1976); |
14257 | 0 | let v2016 = constructor_output_xmm(ctx, v2015); |
14258 | 0 | // Rule at src/isa/x64/lower.isle line 3615. |
14259 | 0 | return Some(v2016); |
14260 | | } |
14261 | | 0x17160706151405041312030211100100 => { |
14262 | 0 | let v1970 = C::unpack_value_array_2(ctx, v1968); |
14263 | 0 | let v1975 = constructor_put_in_xmm(ctx, v1970.0); |
14264 | 0 | let v1976 = &C::put_in_xmm_mem(ctx, v1970.1); |
14265 | 0 | let v2019 = constructor_x64_punpcklwd(ctx, v1975, v1976); |
14266 | 0 | let v2020 = constructor_output_xmm(ctx, v2019); |
14267 | 0 | // Rule at src/isa/x64/lower.isle line 3621. |
14268 | 0 | return Some(v2020); |
14269 | | } |
14270 | | 0x17161514070605041312111003020100 => { |
14271 | 0 | let v1970 = C::unpack_value_array_2(ctx, v1968); |
14272 | 0 | let v1975 = constructor_put_in_xmm(ctx, v1970.0); |
14273 | 0 | let v1976 = &C::put_in_xmm_mem(ctx, v1970.1); |
14274 | 0 | let v2023 = constructor_x64_punpckldq(ctx, v1975, v1976); |
14275 | 0 | let v2024 = constructor_output_xmm(ctx, v2023); |
14276 | 0 | // Rule at src/isa/x64/lower.isle line 3627. |
14277 | 0 | return Some(v2024); |
14278 | | } |
14279 | | 0x17161514131211100706050403020100 => { |
14280 | 0 | let v1970 = C::unpack_value_array_2(ctx, v1968); |
14281 | 0 | let v1975 = constructor_put_in_xmm(ctx, v1970.0); |
14282 | 0 | let v1976 = &C::put_in_xmm_mem(ctx, v1970.1); |
14283 | 0 | let v2027 = constructor_x64_punpcklqdq(ctx, v1975, v1976); |
14284 | 0 | let v2028 = constructor_output_xmm(ctx, v2027); |
14285 | 0 | // Rule at src/isa/x64/lower.isle line 3633. |
14286 | 0 | return Some(v2028); |
14287 | | } |
14288 | | 0x1F0F1E0E1D0D1C0C1B0B1A0A19091808 => { |
14289 | 0 | let v1970 = C::unpack_value_array_2(ctx, v1968); |
14290 | 0 | let v1975 = constructor_put_in_xmm(ctx, v1970.0); |
14291 | 0 | let v1976 = &C::put_in_xmm_mem(ctx, v1970.1); |
14292 | 0 | let v2013 = constructor_x64_punpckhbw(ctx, v1975, v1976); |
14293 | 0 | let v2014 = constructor_output_xmm(ctx, v2013); |
14294 | 0 | // Rule at src/isa/x64/lower.isle line 3613. |
14295 | 0 | return Some(v2014); |
14296 | | } |
14297 | | 0x1F1E0F0E1D1C0D0C1B1A0B0A19180908 => { |
14298 | 0 | let v1970 = C::unpack_value_array_2(ctx, v1968); |
14299 | 0 | let v1975 = constructor_put_in_xmm(ctx, v1970.0); |
14300 | 0 | let v1976 = &C::put_in_xmm_mem(ctx, v1970.1); |
14301 | 0 | let v2017 = constructor_x64_punpckhwd(ctx, v1975, v1976); |
14302 | 0 | let v2018 = constructor_output_xmm(ctx, v2017); |
14303 | 0 | // Rule at src/isa/x64/lower.isle line 3619. |
14304 | 0 | return Some(v2018); |
14305 | | } |
14306 | | 0x1F1E1D1C0F0E0D0C1B1A19180B0A0908 => { |
14307 | 0 | let v1970 = C::unpack_value_array_2(ctx, v1968); |
14308 | 0 | let v1975 = constructor_put_in_xmm(ctx, v1970.0); |
14309 | 0 | let v1976 = &C::put_in_xmm_mem(ctx, v1970.1); |
14310 | 0 | let v2021 = constructor_x64_punpckhdq(ctx, v1975, v1976); |
14311 | 0 | let v2022 = constructor_output_xmm(ctx, v2021); |
14312 | 0 | // Rule at src/isa/x64/lower.isle line 3625. |
14313 | 0 | return Some(v2022); |
14314 | | } |
14315 | | 0x1F1E1D1C1B1A19180F0E0D0C0B0A0908 => { |
14316 | 0 | let v1970 = C::unpack_value_array_2(ctx, v1968); |
14317 | 0 | let v1975 = constructor_put_in_xmm(ctx, v1970.0); |
14318 | 0 | let v1976 = &C::put_in_xmm_mem(ctx, v1970.1); |
14319 | 0 | let v2025 = constructor_x64_punpckhqdq(ctx, v1975, v1976); |
14320 | 0 | let v2026 = constructor_output_xmm(ctx, v2025); |
14321 | 0 | // Rule at src/isa/x64/lower.isle line 3631. |
14322 | 0 | return Some(v2026); |
14323 | | } |
14324 | 0 | _ => {} |
14325 | | } |
14326 | 0 | } |
14327 | 0 | let v2033 = C::shufps_imm(ctx, v1969); |
14328 | 0 | if let Some(v2034) = v2033 { |
14329 | 0 | let v1970 = C::unpack_value_array_2(ctx, v1968); |
14330 | 0 | let v1975 = constructor_put_in_xmm(ctx, v1970.0); |
14331 | 0 | let v1976 = &C::put_in_xmm_mem(ctx, v1970.1); |
14332 | 0 | let v2035 = constructor_x64_shufps(ctx, v1975, v1976, v2034); |
14333 | 0 | let v2036 = constructor_output_xmm(ctx, v2035); |
14334 | 0 | // Rule at src/isa/x64/lower.isle line 3654. |
14335 | 0 | return Some(v2036); |
14336 | 0 | } |
14337 | 0 | let v2037 = C::shufps_rev_imm(ctx, v1969); |
14338 | 0 | if let Some(v2038) = v2037 { |
14339 | 0 | let v1970 = C::unpack_value_array_2(ctx, v1968); |
14340 | 0 | let v1981 = constructor_put_in_xmm(ctx, v1970.1); |
14341 | 0 | let v1982 = &C::put_in_xmm_mem(ctx, v1970.0); |
14342 | 0 | let v2039 = constructor_x64_shufps(ctx, v1981, v1982, v2038); |
14343 | 0 | let v2040 = constructor_output_xmm(ctx, v2039); |
14344 | 0 | // Rule at src/isa/x64/lower.isle line 3656. |
14345 | 0 | return Some(v2040); |
14346 | 0 | } |
14347 | 0 | let v2041 = &C::vec_mask_from_immediate(ctx, v1969); |
14348 | 0 | if let Some(v2042) = v2041 { |
14349 | 0 | let v1970 = C::unpack_value_array_2(ctx, v1968); |
14350 | 0 | if v1970.0 == v1970.1 { |
14351 | 0 | let v1975 = constructor_put_in_xmm(ctx, v1970.0); |
14352 | 0 | let v2043 = C::shuffle_0_31_mask(ctx, v2042); |
14353 | 0 | let v2044 = &constructor_const_to_xmm_mem(ctx, v2043); |
14354 | 0 | let v2045 = constructor_x64_pshufb(ctx, v1975, v2044); |
14355 | 0 | let v2046 = constructor_output_xmm(ctx, v2045); |
14356 | 0 | // Rule at src/isa/x64/lower.isle line 3669. |
14357 | 0 | return Some(v2046); |
14358 | 0 | } |
14359 | 0 | let v1 = C::first_result(ctx, arg0); |
14360 | 0 | if let Some(v2) = v1 { |
14361 | 0 | let v3 = C::value_type(ctx, v2); |
14362 | 0 | let v363 = C::avx512vl_enabled(ctx, v3); |
14363 | 0 | if v363 == true { |
14364 | 0 | let v2047 = C::avx512vbmi_enabled(ctx, v3); |
14365 | 0 | if v2047 == true { |
14366 | 0 | let v2048 = C::perm_from_mask_with_zeros(ctx, v2042); |
14367 | 0 | if let Some(v2049) = v2048 { |
14368 | 0 | let v1981 = constructor_put_in_xmm(ctx, v1970.1); |
14369 | 0 | let v2052 = constructor_put_in_xmm(ctx, v1970.0); |
14370 | 0 | let v2053 = constructor_x64_xmm_load_const(ctx, I8X16, v2049.0); |
14371 | 0 | let v2054 = constructor_x64_vpermi2b(ctx, v1981, v2052, v2053); |
14372 | 0 | let v2055 = &constructor_const_to_xmm_mem(ctx, v2049.1); |
14373 | 0 | let v2056 = constructor_x64_andps(ctx, v2054, v2055); |
14374 | 0 | let v2057 = constructor_output_xmm(ctx, v2056); |
14375 | 0 | // Rule at src/isa/x64/lower.isle line 3675. |
14376 | 0 | return Some(v2057); |
14377 | 0 | } |
14378 | 0 | let v1981 = constructor_put_in_xmm(ctx, v1970.1); |
14379 | 0 | let v2052 = constructor_put_in_xmm(ctx, v1970.0); |
14380 | 0 | let v2058 = C::perm_from_mask(ctx, v2042); |
14381 | 0 | let v2059 = constructor_x64_xmm_load_const(ctx, I8X16, v2058); |
14382 | 0 | let v2060 = constructor_x64_vpermi2b(ctx, v1981, v2052, v2059); |
14383 | 0 | let v2061 = constructor_output_xmm(ctx, v2060); |
14384 | 0 | // Rule at src/isa/x64/lower.isle line 3682. |
14385 | 0 | return Some(v2061); |
14386 | 0 | } |
14387 | 0 | } |
14388 | 0 | } |
14389 | 0 | let v1975 = constructor_put_in_xmm(ctx, v1970.0); |
14390 | 0 | let v2062 = C::shuffle_0_15_mask(ctx, v2042); |
14391 | 0 | let v2063 = &constructor_const_to_xmm_mem(ctx, v2062); |
14392 | 0 | let v2064 = constructor_x64_pshufb(ctx, v1975, v2063); |
14393 | 0 | let v2065 = constructor_put_in_xmm(ctx, v1970.1); |
14394 | 0 | let v2066 = C::shuffle_16_31_mask(ctx, v2042); |
14395 | 0 | let v2067 = &constructor_const_to_xmm_mem(ctx, v2066); |
14396 | 0 | let v2068 = constructor_x64_pshufb(ctx, v2065, v2067); |
14397 | 0 | let v2069 = &C::xmm_to_xmm_mem(ctx, v2068); |
14398 | 0 | let v2070 = constructor_x64_por(ctx, v2064, v2069); |
14399 | 0 | let v2071 = constructor_output_xmm(ctx, v2070); |
14400 | 0 | // Rule at src/isa/x64/lower.isle line 3689. |
14401 | 0 | return Some(v2071); |
14402 | 0 | } |
14403 | 0 | } |
14404 | | } |
14405 | | &InstructionData::StackLoad { |
14406 | 112 | opcode: ref v1876, |
14407 | 112 | stack_slot: v1877, |
14408 | 112 | offset: v1878, |
14409 | 112 | } => { |
14410 | 112 | if let &Opcode::StackAddr = v1876 { |
14411 | 112 | let v1879 = constructor_stack_addr_impl(ctx, v1877, v1878); |
14412 | 112 | let v1880 = constructor_output_gpr(ctx, v1879); |
14413 | 112 | // Rule at src/isa/x64/lower.isle line 3369. |
14414 | 112 | return Some(v1880); |
14415 | 0 | } |
14416 | | } |
14417 | | &InstructionData::Store { |
14418 | 364k | opcode: ref v1318, |
14419 | 364k | args: ref v1319, |
14420 | 364k | flags: v1320, |
14421 | 364k | offset: v1321, |
14422 | 364k | } => { |
14423 | 364k | match v1318 { |
14424 | | &Opcode::Store => { |
14425 | 324k | let v1322 = C::unpack_value_array_2(ctx, v1319); |
14426 | 324k | let v1365 = C::def_inst(ctx, v1322.0); |
14427 | 324k | if let Some(v1366305k ) = v1365 { |
14428 | 305k | let v1367 = C::first_result(ctx, v1366); |
14429 | 305k | if let Some(v1368) = v1367 { |
14430 | 305k | let v1370 = &C::inst_data(ctx, v1366); |
14431 | 305k | match v1370 { |
14432 | | &InstructionData::Binary { |
14433 | 50.3k | opcode: ref v1390, |
14434 | 50.3k | args: ref v1391, |
14435 | 50.3k | } => { |
14436 | 50.3k | match v1390 { |
14437 | | &Opcode::Iadd => { |
14438 | 40.0k | let v1369 = C::value_type(ctx, v1368); |
14439 | 40.0k | let v1388 = C::ty_32_or_64(ctx, v1369); |
14440 | 40.0k | if let Some(v1389) = v1388 { |
14441 | 40.0k | let v1392 = C::unpack_value_array_2(ctx, v1391); |
14442 | 40.0k | let v1395 = &C::sinkable_load(ctx, v1392.0); |
14443 | 40.0k | if let Some(v13961.81k ) = v1395 { |
14444 | 1.81k | let v1397 = C::def_inst(ctx, v1392.0); |
14445 | 1.81k | if let Some(v1398) = v1397 { |
14446 | 1.81k | let v1399 = &C::inst_data(ctx, v1398); |
14447 | | if let &InstructionData::Load { |
14448 | 1.81k | opcode: ref v1400, |
14449 | 1.81k | arg: v1401, |
14450 | 1.81k | flags: v1402, |
14451 | 1.81k | offset: v1403, |
14452 | 1.81k | } = v1399 { |
14453 | 1.81k | if let &Opcode::Load = v1400 { |
14454 | 1.81k | if v1320 == v1402 { |
14455 | 1.81k | if v1321 == v1403 { |
14456 | 1.81k | if v1322.1 == v1401 { |
14457 | 1.43k | let v1404 = &constructor_sink_load_to_reg_mem_imm(ctx, v1396); |
14458 | 1.43k | let v1405 = &constructor_to_amode(ctx, v1402, v1401, v1403); |
14459 | 1.43k | let v1406 = constructor_put_in_gpr(ctx, v1392.1); |
14460 | 1.43k | let v1407 = &constructor_x64_add_mem(ctx, v1389, v1405, v1406); |
14461 | 1.43k | let v1408 = constructor_side_effect(ctx, v1407); |
14462 | 1.43k | // Rule at src/isa/x64/lower.isle line 2581. |
14463 | 1.43k | return Some(v1408); |
14464 | 429 | } |
14465 | 0 | } |
14466 | 0 | } |
14467 | 0 | } |
14468 | 0 | } |
14469 | 0 | } |
14470 | 38.2k | } |
14471 | 38.6k | let v1409 = &C::sinkable_load(ctx, v1392.1); |
14472 | 38.6k | if let Some(v141023 ) = v1409 { |
14473 | 23 | let v1411 = C::def_inst(ctx, v1392.1); |
14474 | 23 | if let Some(v1412) = v1411 { |
14475 | 23 | let v1413 = &C::inst_data(ctx, v1412); |
14476 | | if let &InstructionData::Load { |
14477 | 23 | opcode: ref v1414, |
14478 | 23 | arg: v1415, |
14479 | 23 | flags: v1416, |
14480 | 23 | offset: v1417, |
14481 | 23 | } = v1413 { |
14482 | 23 | if let &Opcode::Load = v1414 { |
14483 | 23 | if v1320 == v1416 { |
14484 | 23 | if v1321 == v1417 { |
14485 | 23 | if v1322.1 == v1415 { |
14486 | 7 | let v1418 = &constructor_sink_load_to_reg_mem_imm(ctx, v1410); |
14487 | 7 | let v1419 = &constructor_to_amode(ctx, v1416, v1415, v1417); |
14488 | 7 | let v1420 = constructor_put_in_gpr(ctx, v1392.0); |
14489 | 7 | let v1421 = &constructor_x64_add_mem(ctx, v1389, v1419, v1420); |
14490 | 7 | let v1422 = constructor_side_effect(ctx, v1421); |
14491 | 7 | // Rule at src/isa/x64/lower.isle line 2595. |
14492 | 7 | return Some(v1422); |
14493 | 17 | } |
14494 | 0 | } |
14495 | 0 | } |
14496 | 0 | } |
14497 | 0 | } |
14498 | 0 | } |
14499 | 38.6k | } |
14500 | 0 | } |
14501 | | } |
14502 | | &Opcode::Isub => { |
14503 | 7.80k | let v1369 = C::value_type(ctx, v1368); |
14504 | 7.80k | let v1388 = C::ty_32_or_64(ctx, v1369); |
14505 | 7.80k | if let Some(v1389) = v1388 { |
14506 | 7.80k | let v1392 = C::unpack_value_array_2(ctx, v1391); |
14507 | 7.80k | let v1395 = &C::sinkable_load(ctx, v1392.0); |
14508 | 7.80k | if let Some(v13965 ) = v1395 { |
14509 | 5 | let v1397 = C::def_inst(ctx, v1392.0); |
14510 | 5 | if let Some(v1398) = v1397 { |
14511 | 5 | let v1399 = &C::inst_data(ctx, v1398); |
14512 | | if let &InstructionData::Load { |
14513 | 5 | opcode: ref v1400, |
14514 | 5 | arg: v1401, |
14515 | 5 | flags: v1402, |
14516 | 5 | offset: v1403, |
14517 | 5 | } = v1399 { |
14518 | 5 | if let &Opcode::Load = v1400 { |
14519 | 5 | if v1320 == v1402 { |
14520 | 5 | if v1321 == v1403 { |
14521 | 5 | if v1322.1 == v1401 { |
14522 | 5 | let v1404 = &constructor_sink_load_to_reg_mem_imm(ctx, v1396); |
14523 | 5 | let v1405 = &constructor_to_amode(ctx, v1402, v1401, v1403); |
14524 | 5 | let v1406 = constructor_put_in_gpr(ctx, v1392.1); |
14525 | 5 | let v1423 = &constructor_x64_sub_mem(ctx, v1389, v1405, v1406); |
14526 | 5 | let v1424 = constructor_side_effect(ctx, v1423); |
14527 | 5 | // Rule at src/isa/x64/lower.isle line 2609. |
14528 | 5 | return Some(v1424); |
14529 | 0 | } |
14530 | 0 | } |
14531 | 0 | } |
14532 | 0 | } |
14533 | 0 | } |
14534 | 0 | } |
14535 | 7.80k | } |
14536 | 0 | } |
14537 | | } |
14538 | | &Opcode::Band => { |
14539 | 364 | let v1369 = C::value_type(ctx, v1368); |
14540 | 364 | let v1388 = C::ty_32_or_64(ctx, v1369); |
14541 | 364 | if let Some(v1389) = v1388 { |
14542 | 364 | let v1392 = C::unpack_value_array_2(ctx, v1391); |
14543 | 364 | let v1395 = &C::sinkable_load(ctx, v1392.0); |
14544 | 364 | if let Some(v13960 ) = v1395 { |
14545 | 0 | let v1397 = C::def_inst(ctx, v1392.0); |
14546 | 0 | if let Some(v1398) = v1397 { |
14547 | 0 | let v1399 = &C::inst_data(ctx, v1398); |
14548 | | if let &InstructionData::Load { |
14549 | 0 | opcode: ref v1400, |
14550 | 0 | arg: v1401, |
14551 | 0 | flags: v1402, |
14552 | 0 | offset: v1403, |
14553 | 0 | } = v1399 { |
14554 | 0 | if let &Opcode::Load = v1400 { |
14555 | 0 | if v1320 == v1402 { |
14556 | 0 | if v1321 == v1403 { |
14557 | 0 | if v1322.1 == v1401 { |
14558 | 0 | let v1404 = &constructor_sink_load_to_reg_mem_imm(ctx, v1396); |
14559 | 0 | let v1405 = &constructor_to_amode(ctx, v1402, v1401, v1403); |
14560 | 0 | let v1406 = constructor_put_in_gpr(ctx, v1392.1); |
14561 | 0 | let v1425 = &constructor_x64_and_mem(ctx, v1389, v1405, v1406); |
14562 | 0 | let v1426 = constructor_side_effect(ctx, v1425); |
14563 | 0 | // Rule at src/isa/x64/lower.isle line 2623. |
14564 | 0 | return Some(v1426); |
14565 | 0 | } |
14566 | 0 | } |
14567 | 0 | } |
14568 | 0 | } |
14569 | 0 | } |
14570 | 0 | } |
14571 | 364 | } |
14572 | 364 | let v1409 = &C::sinkable_load(ctx, v1392.1); |
14573 | 364 | if let Some(v14100 ) = v1409 { |
14574 | 0 | let v1411 = C::def_inst(ctx, v1392.1); |
14575 | 0 | if let Some(v1412) = v1411 { |
14576 | 0 | let v1413 = &C::inst_data(ctx, v1412); |
14577 | | if let &InstructionData::Load { |
14578 | 0 | opcode: ref v1414, |
14579 | 0 | arg: v1415, |
14580 | 0 | flags: v1416, |
14581 | 0 | offset: v1417, |
14582 | 0 | } = v1413 { |
14583 | 0 | if let &Opcode::Load = v1414 { |
14584 | 0 | if v1320 == v1416 { |
14585 | 0 | if v1321 == v1417 { |
14586 | 0 | if v1322.1 == v1415 { |
14587 | 0 | let v1418 = &constructor_sink_load_to_reg_mem_imm(ctx, v1410); |
14588 | 0 | let v1419 = &constructor_to_amode(ctx, v1416, v1415, v1417); |
14589 | 0 | let v1420 = constructor_put_in_gpr(ctx, v1392.0); |
14590 | 0 | let v1427 = &constructor_x64_and_mem(ctx, v1389, v1419, v1420); |
14591 | 0 | let v1428 = constructor_side_effect(ctx, v1427); |
14592 | 0 | // Rule at src/isa/x64/lower.isle line 2637. |
14593 | 0 | return Some(v1428); |
14594 | 0 | } |
14595 | 0 | } |
14596 | 0 | } |
14597 | 0 | } |
14598 | 0 | } |
14599 | 0 | } |
14600 | 364 | } |
14601 | 0 | } |
14602 | | } |
14603 | | &Opcode::Bor => { |
14604 | 698 | let v1369 = C::value_type(ctx, v1368); |
14605 | 698 | let v1388 = C::ty_32_or_64(ctx, v1369); |
14606 | 698 | if let Some(v1389) = v1388 { |
14607 | 698 | let v1392 = C::unpack_value_array_2(ctx, v1391); |
14608 | 698 | let v1395 = &C::sinkable_load(ctx, v1392.0); |
14609 | 698 | if let Some(v13960 ) = v1395 { |
14610 | 0 | let v1397 = C::def_inst(ctx, v1392.0); |
14611 | 0 | if let Some(v1398) = v1397 { |
14612 | 0 | let v1399 = &C::inst_data(ctx, v1398); |
14613 | | if let &InstructionData::Load { |
14614 | 0 | opcode: ref v1400, |
14615 | 0 | arg: v1401, |
14616 | 0 | flags: v1402, |
14617 | 0 | offset: v1403, |
14618 | 0 | } = v1399 { |
14619 | 0 | if let &Opcode::Load = v1400 { |
14620 | 0 | if v1320 == v1402 { |
14621 | 0 | if v1321 == v1403 { |
14622 | 0 | if v1322.1 == v1401 { |
14623 | 0 | let v1404 = &constructor_sink_load_to_reg_mem_imm(ctx, v1396); |
14624 | 0 | let v1405 = &constructor_to_amode(ctx, v1402, v1401, v1403); |
14625 | 0 | let v1406 = constructor_put_in_gpr(ctx, v1392.1); |
14626 | 0 | let v1429 = &constructor_x64_or_mem(ctx, v1389, v1405, v1406); |
14627 | 0 | let v1430 = constructor_side_effect(ctx, v1429); |
14628 | 0 | // Rule at src/isa/x64/lower.isle line 2651. |
14629 | 0 | return Some(v1430); |
14630 | 0 | } |
14631 | 0 | } |
14632 | 0 | } |
14633 | 0 | } |
14634 | 0 | } |
14635 | 0 | } |
14636 | 698 | } |
14637 | 698 | let v1409 = &C::sinkable_load(ctx, v1392.1); |
14638 | 698 | if let Some(v14100 ) = v1409 { |
14639 | 0 | let v1411 = C::def_inst(ctx, v1392.1); |
14640 | 0 | if let Some(v1412) = v1411 { |
14641 | 0 | let v1413 = &C::inst_data(ctx, v1412); |
14642 | | if let &InstructionData::Load { |
14643 | 0 | opcode: ref v1414, |
14644 | 0 | arg: v1415, |
14645 | 0 | flags: v1416, |
14646 | 0 | offset: v1417, |
14647 | 0 | } = v1413 { |
14648 | 0 | if let &Opcode::Load = v1414 { |
14649 | 0 | if v1320 == v1416 { |
14650 | 0 | if v1321 == v1417 { |
14651 | 0 | if v1322.1 == v1415 { |
14652 | 0 | let v1418 = &constructor_sink_load_to_reg_mem_imm(ctx, v1410); |
14653 | 0 | let v1419 = &constructor_to_amode(ctx, v1416, v1415, v1417); |
14654 | 0 | let v1420 = constructor_put_in_gpr(ctx, v1392.0); |
14655 | 0 | let v1431 = &constructor_x64_or_mem(ctx, v1389, v1419, v1420); |
14656 | 0 | let v1432 = constructor_side_effect(ctx, v1431); |
14657 | 0 | // Rule at src/isa/x64/lower.isle line 2665. |
14658 | 0 | return Some(v1432); |
14659 | 0 | } |
14660 | 0 | } |
14661 | 0 | } |
14662 | 0 | } |
14663 | 0 | } |
14664 | 0 | } |
14665 | 698 | } |
14666 | 0 | } |
14667 | | } |
14668 | | &Opcode::Bxor => { |
14669 | 136 | let v1369 = C::value_type(ctx, v1368); |
14670 | 136 | let v1388 = C::ty_32_or_64(ctx, v1369); |
14671 | 136 | if let Some(v1389) = v1388 { |
14672 | 136 | let v1392 = C::unpack_value_array_2(ctx, v1391); |
14673 | 136 | let v1395 = &C::sinkable_load(ctx, v1392.0); |
14674 | 136 | if let Some(v13960 ) = v1395 { |
14675 | 0 | let v1397 = C::def_inst(ctx, v1392.0); |
14676 | 0 | if let Some(v1398) = v1397 { |
14677 | 0 | let v1399 = &C::inst_data(ctx, v1398); |
14678 | | if let &InstructionData::Load { |
14679 | 0 | opcode: ref v1400, |
14680 | 0 | arg: v1401, |
14681 | 0 | flags: v1402, |
14682 | 0 | offset: v1403, |
14683 | 0 | } = v1399 { |
14684 | 0 | if let &Opcode::Load = v1400 { |
14685 | 0 | if v1320 == v1402 { |
14686 | 0 | if v1321 == v1403 { |
14687 | 0 | if v1322.1 == v1401 { |
14688 | 0 | let v1404 = &constructor_sink_load_to_reg_mem_imm(ctx, v1396); |
14689 | 0 | let v1405 = &constructor_to_amode(ctx, v1402, v1401, v1403); |
14690 | 0 | let v1406 = constructor_put_in_gpr(ctx, v1392.1); |
14691 | 0 | let v1433 = &constructor_x64_xor_mem(ctx, v1389, v1405, v1406); |
14692 | 0 | let v1434 = constructor_side_effect(ctx, v1433); |
14693 | 0 | // Rule at src/isa/x64/lower.isle line 2679. |
14694 | 0 | return Some(v1434); |
14695 | 0 | } |
14696 | 0 | } |
14697 | 0 | } |
14698 | 0 | } |
14699 | 0 | } |
14700 | 0 | } |
14701 | 136 | } |
14702 | 136 | let v1409 = &C::sinkable_load(ctx, v1392.1); |
14703 | 136 | if let Some(v14100 ) = v1409 { |
14704 | 0 | let v1411 = C::def_inst(ctx, v1392.1); |
14705 | 0 | if let Some(v1412) = v1411 { |
14706 | 0 | let v1413 = &C::inst_data(ctx, v1412); |
14707 | | if let &InstructionData::Load { |
14708 | 0 | opcode: ref v1414, |
14709 | 0 | arg: v1415, |
14710 | 0 | flags: v1416, |
14711 | 0 | offset: v1417, |
14712 | 0 | } = v1413 { |
14713 | 0 | if let &Opcode::Load = v1414 { |
14714 | 0 | if v1320 == v1416 { |
14715 | 0 | if v1321 == v1417 { |
14716 | 0 | if v1322.1 == v1415 { |
14717 | 0 | let v1418 = &constructor_sink_load_to_reg_mem_imm(ctx, v1410); |
14718 | 0 | let v1419 = &constructor_to_amode(ctx, v1416, v1415, v1417); |
14719 | 0 | let v1420 = constructor_put_in_gpr(ctx, v1392.0); |
14720 | 0 | let v1435 = &constructor_x64_xor_mem(ctx, v1389, v1419, v1420); |
14721 | 0 | let v1436 = constructor_side_effect(ctx, v1435); |
14722 | 0 | // Rule at src/isa/x64/lower.isle line 2693. |
14723 | 0 | return Some(v1436); |
14724 | 0 | } |
14725 | 0 | } |
14726 | 0 | } |
14727 | 0 | } |
14728 | 0 | } |
14729 | 0 | } |
14730 | 136 | } |
14731 | 0 | } |
14732 | | } |
14733 | 1.28k | _ => {} |
14734 | | } |
14735 | | } |
14736 | | &InstructionData::BinaryImm8 { |
14737 | 0 | opcode: ref v1371, |
14738 | 0 | arg: v1372, |
14739 | 0 | imm: v1373, |
14740 | 0 | } => { |
14741 | 0 | if let &Opcode::Extractlane = v1371 { |
14742 | 0 | let v1369 = C::value_type(ctx, v1368); |
14743 | 0 | match v1369 { |
14744 | | I8 => { |
14745 | 0 | let v1329 = &constructor_to_amode(ctx, v1320, v1322.1, v1321); |
14746 | 0 | let v1330 = &C::amode_to_synthetic_amode(ctx, v1329); |
14747 | 0 | let v1375 = constructor_put_in_xmm(ctx, v1372); |
14748 | 0 | let v1374 = C::u8_from_uimm8(ctx, v1373); |
14749 | 0 | let v1380 = &constructor_x64_pextrb_store(ctx, v1330, v1375, v1374); |
14750 | 0 | let v1381 = constructor_side_effect(ctx, v1380); |
14751 | 0 | // Rule at src/isa/x64/lower.isle line 2553. |
14752 | 0 | return Some(v1381); |
14753 | | } |
14754 | | I16 => { |
14755 | 0 | let v1329 = &constructor_to_amode(ctx, v1320, v1322.1, v1321); |
14756 | 0 | let v1330 = &C::amode_to_synthetic_amode(ctx, v1329); |
14757 | 0 | let v1375 = constructor_put_in_xmm(ctx, v1372); |
14758 | 0 | let v1374 = C::u8_from_uimm8(ctx, v1373); |
14759 | 0 | let v1382 = &constructor_x64_pextrw_store(ctx, v1330, v1375, v1374); |
14760 | 0 | let v1383 = constructor_side_effect(ctx, v1382); |
14761 | 0 | // Rule at src/isa/x64/lower.isle line 2559. |
14762 | 0 | return Some(v1383); |
14763 | | } |
14764 | | I32 => { |
14765 | 0 | let v1329 = &constructor_to_amode(ctx, v1320, v1322.1, v1321); |
14766 | 0 | let v1330 = &C::amode_to_synthetic_amode(ctx, v1329); |
14767 | 0 | let v1375 = constructor_put_in_xmm(ctx, v1372); |
14768 | 0 | let v1374 = C::u8_from_uimm8(ctx, v1373); |
14769 | 0 | let v1384 = &constructor_x64_pextrd_store(ctx, v1330, v1375, v1374); |
14770 | 0 | let v1385 = constructor_side_effect(ctx, v1384); |
14771 | 0 | // Rule at src/isa/x64/lower.isle line 2565. |
14772 | 0 | return Some(v1385); |
14773 | | } |
14774 | | I64 => { |
14775 | 0 | let v1329 = &constructor_to_amode(ctx, v1320, v1322.1, v1321); |
14776 | 0 | let v1330 = &C::amode_to_synthetic_amode(ctx, v1329); |
14777 | 0 | let v1375 = constructor_put_in_xmm(ctx, v1372); |
14778 | 0 | let v1374 = C::u8_from_uimm8(ctx, v1373); |
14779 | 0 | let v1386 = &constructor_x64_pextrq_store(ctx, v1330, v1375, v1374); |
14780 | 0 | let v1387 = constructor_side_effect(ctx, v1386); |
14781 | 0 | // Rule at src/isa/x64/lower.isle line 2571. |
14782 | 0 | return Some(v1387); |
14783 | | } |
14784 | | F32 => { |
14785 | 0 | let v1374 = C::u8_from_uimm8(ctx, v1373); |
14786 | 0 | if v1374 == 0x0 { |
14787 | 0 | let v1329 = &constructor_to_amode(ctx, v1320, v1322.1, v1321); |
14788 | 0 | let v1330 = &C::amode_to_synthetic_amode(ctx, v1329); |
14789 | 0 | let v1375 = constructor_put_in_xmm(ctx, v1372); |
14790 | 0 | let v1376 = &constructor_x64_movss_store(ctx, v1330, v1375); |
14791 | 0 | let v1377 = constructor_side_effect(ctx, v1376); |
14792 | 0 | // Rule at src/isa/x64/lower.isle line 2541. |
14793 | 0 | return Some(v1377); |
14794 | 0 | } |
14795 | | } |
14796 | | F64 => { |
14797 | 0 | let v1374 = C::u8_from_uimm8(ctx, v1373); |
14798 | 0 | if v1374 == 0x0 { |
14799 | 0 | let v1329 = &constructor_to_amode(ctx, v1320, v1322.1, v1321); |
14800 | 0 | let v1330 = &C::amode_to_synthetic_amode(ctx, v1329); |
14801 | 0 | let v1375 = constructor_put_in_xmm(ctx, v1372); |
14802 | 0 | let v1378 = &constructor_x64_movsd_store(ctx, v1330, v1375); |
14803 | 0 | let v1379 = constructor_side_effect(ctx, v1378); |
14804 | 0 | // Rule at src/isa/x64/lower.isle line 2547. |
14805 | 0 | return Some(v1379); |
14806 | 0 | } |
14807 | | } |
14808 | 0 | _ => {} |
14809 | | } |
14810 | 0 | } |
14811 | | } |
14812 | 254k | _ => {} |
14813 | | } |
14814 | 0 | } |
14815 | 19.2k | } |
14816 | 323k | let v1325 = C::value_type(ctx, v1322.0); |
14817 | 323k | match v1325 { |
14818 | | I128 => { |
14819 | 0 | let v1354 = C::put_in_regs(ctx, v1322.0); |
14820 | 0 | let v1355 = constructor_value_regs_get_gpr(ctx, v1354, 0x0); |
14821 | 0 | let v1356 = constructor_value_regs_get_gpr(ctx, v1354, 0x1); |
14822 | 0 | let v1357 = &constructor_to_amode(ctx, v1320, v1322.1, v1321); |
14823 | 0 | let v1358 = &C::amode_offset(ctx, v1357, 0x8); |
14824 | 0 | let v1359 = &C::amode_to_synthetic_amode(ctx, v1357); |
14825 | 0 | let v1360 = &constructor_x64_movrm(ctx, I64, v1359, v1355); |
14826 | 0 | let v1361 = &C::amode_to_synthetic_amode(ctx, v1358); |
14827 | 0 | let v1362 = &constructor_x64_movrm(ctx, I64, v1361, v1356); |
14828 | 0 | let v1363 = &constructor_side_effect_concat(ctx, v1360, v1362); |
14829 | 0 | let v1364 = constructor_side_effect(ctx, v1363); |
14830 | 0 | // Rule at src/isa/x64/lower.isle line 2522. |
14831 | 0 | return Some(v1364); |
14832 | | } |
14833 | | F32 => { |
14834 | 0 | let v1329 = &constructor_to_amode(ctx, v1320, v1322.1, v1321); |
14835 | 0 | let v1330 = &C::amode_to_synthetic_amode(ctx, v1329); |
14836 | 0 | let v1341 = constructor_put_in_xmm(ctx, v1322.0); |
14837 | 0 | let v1342 = &constructor_x64_movss_store(ctx, v1330, v1341); |
14838 | 0 | let v1343 = constructor_side_effect(ctx, v1342); |
14839 | 0 | // Rule at src/isa/x64/lower.isle line 2482. |
14840 | 0 | return Some(v1343); |
14841 | | } |
14842 | | F64 => { |
14843 | 1 | let v1329 = &constructor_to_amode(ctx, v1320, v1322.1, v1321); |
14844 | 1 | let v1330 = &C::amode_to_synthetic_amode(ctx, v1329); |
14845 | 1 | let v1341 = constructor_put_in_xmm(ctx, v1322.0); |
14846 | 1 | let v1344 = &constructor_x64_movsd_store(ctx, v1330, v1341); |
14847 | 1 | let v1345 = constructor_side_effect(ctx, v1344); |
14848 | 1 | // Rule at src/isa/x64/lower.isle line 2490. |
14849 | 1 | return Some(v1345); |
14850 | | } |
14851 | | F32X4 => { |
14852 | 0 | let v1329 = &constructor_to_amode(ctx, v1320, v1322.1, v1321); |
14853 | 0 | let v1330 = &C::amode_to_synthetic_amode(ctx, v1329); |
14854 | 0 | let v1341 = constructor_put_in_xmm(ctx, v1322.0); |
14855 | 0 | let v1346 = &constructor_x64_movups_store(ctx, v1330, v1341); |
14856 | 0 | let v1347 = constructor_side_effect(ctx, v1346); |
14857 | 0 | // Rule at src/isa/x64/lower.isle line 2498. |
14858 | 0 | return Some(v1347); |
14859 | | } |
14860 | | F64X2 => { |
14861 | 0 | let v1329 = &constructor_to_amode(ctx, v1320, v1322.1, v1321); |
14862 | 0 | let v1330 = &C::amode_to_synthetic_amode(ctx, v1329); |
14863 | 0 | let v1341 = constructor_put_in_xmm(ctx, v1322.0); |
14864 | 0 | let v1348 = &constructor_x64_movupd_store(ctx, v1330, v1341); |
14865 | 0 | let v1349 = constructor_side_effect(ctx, v1348); |
14866 | 0 | // Rule at src/isa/x64/lower.isle line 2506. |
14867 | 0 | return Some(v1349); |
14868 | | } |
14869 | 323k | _ => {} |
14870 | 323k | } |
14871 | 323k | let v1350 = C::ty_vec128_int(ctx, v1325); |
14872 | 323k | if let Some(v13510 ) = v1350 { |
14873 | 0 | let v1329 = &constructor_to_amode(ctx, v1320, v1322.1, v1321); |
14874 | 0 | let v1330 = &C::amode_to_synthetic_amode(ctx, v1329); |
14875 | 0 | let v1341 = constructor_put_in_xmm(ctx, v1322.0); |
14876 | 0 | let v1352 = &constructor_x64_movdqu_store(ctx, v1330, v1341); |
14877 | 0 | let v1353 = constructor_side_effect(ctx, v1352); |
14878 | 0 | // Rule at src/isa/x64/lower.isle line 2514. |
14879 | 0 | return Some(v1353); |
14880 | 323k | } |
14881 | 323k | let v1326 = &C::type_register_class(ctx, v1325); |
14882 | 323k | if let Some(v1327) = v1326 { |
14883 | | if let &RegisterClass::Gpr { |
14884 | 322k | single_register: v1328, |
14885 | 323k | } = v1327 { |
14886 | 322k | let v1329 = &constructor_to_amode(ctx, v1320, v1322.1, v1321); |
14887 | 322k | let v1330 = &C::amode_to_synthetic_amode(ctx, v1329); |
14888 | 322k | let v1331 = constructor_put_in_gpr(ctx, v1322.0); |
14889 | 322k | let v1332 = &constructor_x64_movrm(ctx, v1325, v1330, v1331); |
14890 | 322k | let v1333 = constructor_side_effect(ctx, v1332); |
14891 | 322k | // Rule at src/isa/x64/lower.isle line 2463. |
14892 | 322k | return Some(v1333); |
14893 | 0 | } |
14894 | 0 | } |
14895 | | } |
14896 | | &Opcode::Istore8 => { |
14897 | 30.3k | let v1322 = C::unpack_value_array_2(ctx, v1319); |
14898 | 30.3k | let v1329 = &constructor_to_amode(ctx, v1320, v1322.1, v1321); |
14899 | 30.3k | let v1330 = &C::amode_to_synthetic_amode(ctx, v1329); |
14900 | 30.3k | let v1331 = constructor_put_in_gpr(ctx, v1322.0); |
14901 | 30.3k | let v1335 = &constructor_x64_movrm(ctx, I8, v1330, v1331); |
14902 | 30.3k | let v1336 = constructor_side_effect(ctx, v1335); |
14903 | 30.3k | // Rule at src/isa/x64/lower.isle line 2471. |
14904 | 30.3k | return Some(v1336); |
14905 | | } |
14906 | | &Opcode::Istore16 => { |
14907 | 9.29k | let v1322 = C::unpack_value_array_2(ctx, v1319); |
14908 | 9.29k | let v1329 = &constructor_to_amode(ctx, v1320, v1322.1, v1321); |
14909 | 9.29k | let v1330 = &C::amode_to_synthetic_amode(ctx, v1329); |
14910 | 9.29k | let v1331 = constructor_put_in_gpr(ctx, v1322.0); |
14911 | 9.29k | let v1337 = &constructor_x64_movrm(ctx, I16, v1330, v1331); |
14912 | 9.29k | let v1338 = constructor_side_effect(ctx, v1337); |
14913 | 9.29k | // Rule at src/isa/x64/lower.isle line 2474. |
14914 | 9.29k | return Some(v1338); |
14915 | | } |
14916 | | &Opcode::Istore32 => { |
14917 | 685 | let v1322 = C::unpack_value_array_2(ctx, v1319); |
14918 | 685 | let v1329 = &constructor_to_amode(ctx, v1320, v1322.1, v1321); |
14919 | 685 | let v1330 = &C::amode_to_synthetic_amode(ctx, v1329); |
14920 | 685 | let v1331 = constructor_put_in_gpr(ctx, v1322.0); |
14921 | 685 | let v1339 = &constructor_x64_movrm(ctx, I32, v1330, v1331); |
14922 | 685 | let v1340 = constructor_side_effect(ctx, v1339); |
14923 | 685 | // Rule at src/isa/x64/lower.isle line 2477. |
14924 | 685 | return Some(v1340); |
14925 | | } |
14926 | 0 | _ => {} |
14927 | | } |
14928 | | } |
14929 | | &InstructionData::StoreNoOffset { |
14930 | 0 | opcode: ref v1470, |
14931 | 0 | args: ref v1471, |
14932 | 0 | flags: v1472, |
14933 | 0 | } => { |
14934 | 0 | if let &Opcode::AtomicStore = v1470 { |
14935 | 0 | let v1473 = C::unpack_value_array_2(ctx, v1471); |
14936 | 0 | let v1476 = C::value_type(ctx, v1473.0); |
14937 | 0 | let v1477 = C::fits_in_64(ctx, v1476); |
14938 | 0 | if let Some(v1478) = v1477 { |
14939 | 0 | let v1479 = C::ty_int(ctx, v1476); |
14940 | 0 | if let Some(v1480) = v1479 { |
14941 | 0 | let v48 = C::zero_offset(ctx); |
14942 | 0 | let v1481 = &constructor_to_amode(ctx, v1472, v1473.1, v48); |
14943 | 0 | let v1482 = &C::amode_to_synthetic_amode(ctx, v1481); |
14944 | 0 | let v1483 = constructor_put_in_gpr(ctx, v1473.0); |
14945 | 0 | let v1484 = &constructor_x64_movrm(ctx, v1478, v1482, v1483); |
14946 | 0 | let v1485 = &constructor_x64_mfence(ctx); |
14947 | 0 | let v1486 = &constructor_side_effect_concat(ctx, v1484, v1485); |
14948 | 0 | let v1487 = constructor_side_effect(ctx, v1486); |
14949 | 0 | // Rule at src/isa/x64/lower.isle line 2740. |
14950 | 0 | return Some(v1487); |
14951 | 0 | } |
14952 | 0 | } |
14953 | 0 | } |
14954 | | } |
14955 | | &InstructionData::Ternary { |
14956 | 33.9k | opcode: ref v541, |
14957 | 33.9k | args: ref v542, |
14958 | 33.9k | } => { |
14959 | 33.9k | match v541 { |
14960 | | &Opcode::Select => { |
14961 | 9.18k | let v1 = C::first_result(ctx, arg0); |
14962 | 9.18k | if let Some(v2) = v1 { |
14963 | 9.18k | let v543 = C::unpack_value_array_3(ctx, v542); |
14964 | 9.18k | let v809 = C::maybe_uextend(ctx, v543.0); |
14965 | 9.18k | if let Some(v810) = v809 { |
14966 | 9.18k | let v811 = C::def_inst(ctx, v810); |
14967 | 9.18k | if let Some(v8128.79k ) = v811 { |
14968 | 8.79k | let v813 = &C::inst_data(ctx, v812); |
14969 | 8.79k | match v813 { |
14970 | | &InstructionData::FloatCompare { |
14971 | 0 | opcode: ref v814, |
14972 | 0 | args: ref v815, |
14973 | 0 | cond: ref v816, |
14974 | 0 | } => { |
14975 | 0 | if let &Opcode::Fcmp = v814 { |
14976 | 0 | if let &FloatCC::Equal = v816 { |
14977 | 0 | let v817 = C::unpack_value_array_2(ctx, v815); |
14978 | 0 | let v823 = &constructor_emit_fcmp(ctx, &FloatCC::NotEqual, v817.0, v817.1); |
14979 | 0 | let v3 = C::value_type(ctx, v2); |
14980 | 0 | let v824 = constructor_lower_select_fcmp(ctx, v3, v823, v543.2, v543.1); |
14981 | 0 | // Rule at src/isa/x64/lower.isle line 1584. |
14982 | 0 | return Some(v824); |
14983 | 0 | } |
14984 | 0 | let v817 = C::unpack_value_array_2(ctx, v815); |
14985 | 0 | let v820 = &constructor_emit_fcmp(ctx, v816, v817.0, v817.1); |
14986 | 0 | let v3 = C::value_type(ctx, v2); |
14987 | 0 | let v821 = constructor_lower_select_fcmp(ctx, v3, v820, v543.1, v543.2); |
14988 | 0 | // Rule at src/isa/x64/lower.isle line 1582. |
14989 | 0 | return Some(v821); |
14990 | 0 | } |
14991 | | } |
14992 | | &InstructionData::IntCompare { |
14993 | 5.83k | opcode: ref v825, |
14994 | 5.83k | args: ref v826, |
14995 | 5.83k | cond: ref v827, |
14996 | 5.83k | } => { |
14997 | 5.83k | if let &Opcode::Icmp = v825 { |
14998 | 5.83k | let v828 = C::unpack_value_array_2(ctx, v826); |
14999 | 5.83k | let v831 = C::value_type(ctx, v828.0); |
15000 | 5.83k | let v832 = C::fits_in_64(ctx, v831); |
15001 | 5.83k | if let Some(v833) = v832 { |
15002 | 5.83k | let v834 = &C::raw_operand_size_of_type(ctx, v833); |
15003 | 5.83k | let v835 = &constructor_put_in_gpr_mem_imm(ctx, v828.1); |
15004 | 5.83k | let v836 = constructor_put_in_gpr(ctx, v828.0); |
15005 | 5.83k | let v837 = &constructor_x64_cmp(ctx, v834, v835, v836); |
15006 | 5.83k | let v838 = &C::intcc_to_cc(ctx, v827); |
15007 | 5.83k | let v3 = C::value_type(ctx, v2); |
15008 | 5.83k | let v839 = &constructor_cmove_from_values(ctx, v3, v838, v543.1, v543.2); |
15009 | 5.83k | let v840 = constructor_with_flags(ctx, v837, v839); |
15010 | 5.83k | let v841 = C::output(ctx, v840); |
15011 | 5.83k | // Rule at src/isa/x64/lower.isle line 1598. |
15012 | 5.83k | return Some(v841); |
15013 | 0 | } |
15014 | 0 | } |
15015 | | } |
15016 | 2.95k | _ => {} |
15017 | | } |
15018 | 393 | } |
15019 | 0 | } |
15020 | 3.35k | let v842 = C::value_type(ctx, v543.0); |
15021 | 3.35k | let v843 = C::fits_in_64(ctx, v842); |
15022 | 3.35k | if let Some(v844) = v843 { |
15023 | 3.35k | let v845 = &C::raw_operand_size_of_type(ctx, v844); |
15024 | 3.35k | let v846 = constructor_put_in_gpr(ctx, v543.0); |
15025 | 3.35k | let v847 = &C::gpr_to_gpr_mem_imm(ctx, v846); |
15026 | 3.35k | let v848 = &constructor_x64_test(ctx, v845, v847, v846); |
15027 | 3.35k | let v3 = C::value_type(ctx, v2); |
15028 | 3.35k | let v850 = &constructor_cmove_from_values(ctx, v3, &CC::NZ, v543.1, v543.2); |
15029 | 3.35k | let v851 = constructor_with_flags(ctx, v848, v850); |
15030 | 3.35k | let v852 = C::output(ctx, v851); |
15031 | 3.35k | // Rule at src/isa/x64/lower.isle line 1605. |
15032 | 3.35k | return Some(v852); |
15033 | 0 | } |
15034 | 0 | if v842 == I128 { |
15035 | 0 | let v854 = C::put_in_regs(ctx, v543.0); |
15036 | 0 | let v855 = &constructor_cmp_zero_i128(ctx, &CC::Z, v854); |
15037 | 0 | let v856 = constructor_select_icmp(ctx, v855, v543.1, v543.2); |
15038 | 0 | let v857 = C::output(ctx, v856); |
15039 | 0 | // Rule at src/isa/x64/lower.isle line 1612. |
15040 | 0 | return Some(v857); |
15041 | 0 | } |
15042 | 0 | } |
15043 | | } |
15044 | | &Opcode::SelectSpectreGuard => { |
15045 | 24.7k | let v543 = C::unpack_value_array_3(ctx, v542); |
15046 | 24.7k | let v1541 = C::def_inst(ctx, v543.0); |
15047 | 24.7k | if let Some(v1542) = v1541 { |
15048 | 24.7k | let v1543 = &C::inst_data(ctx, v1542); |
15049 | | if let &InstructionData::IntCompare { |
15050 | 24.7k | opcode: ref v1544, |
15051 | 24.7k | args: ref v1545, |
15052 | 24.7k | cond: ref v1546, |
15053 | 24.7k | } = v1543 { |
15054 | 24.7k | if let &Opcode::Icmp = v1544 { |
15055 | 24.7k | let v1547 = C::unpack_value_array_2(ctx, v1545); |
15056 | 24.7k | let v1550 = &constructor_emit_cmp(ctx, v1546, v1547.0, v1547.1); |
15057 | 24.7k | let v1551 = constructor_select_icmp(ctx, v1550, v543.1, v543.2); |
15058 | 24.7k | let v1552 = C::output(ctx, v1551); |
15059 | 24.7k | // Rule at src/isa/x64/lower.isle line 2851. |
15060 | 24.7k | return Some(v1552); |
15061 | 0 | } |
15062 | 0 | } |
15063 | 0 | } |
15064 | 0 | let v1 = C::first_result(ctx, arg0); |
15065 | 0 | if let Some(v2) = v1 { |
15066 | 0 | let v842 = C::value_type(ctx, v543.0); |
15067 | 0 | let v843 = C::fits_in_64(ctx, v842); |
15068 | 0 | if let Some(v844) = v843 { |
15069 | 0 | let v845 = &C::raw_operand_size_of_type(ctx, v844); |
15070 | 0 | let v846 = constructor_put_in_gpr(ctx, v543.0); |
15071 | 0 | let v847 = &C::gpr_to_gpr_mem_imm(ctx, v846); |
15072 | 0 | let v848 = &constructor_x64_test(ctx, v845, v847, v846); |
15073 | 0 | let v3 = C::value_type(ctx, v2); |
15074 | 0 | let v850 = &constructor_cmove_from_values(ctx, v3, &CC::NZ, v543.1, v543.2); |
15075 | 0 | let v851 = constructor_with_flags(ctx, v848, v850); |
15076 | 0 | let v852 = C::output(ctx, v851); |
15077 | 0 | // Rule at src/isa/x64/lower.isle line 2854. |
15078 | 0 | return Some(v852); |
15079 | 0 | } |
15080 | 0 | if v842 == I128 { |
15081 | 0 | let v854 = C::put_in_regs(ctx, v543.0); |
15082 | 0 | let v855 = &constructor_cmp_zero_i128(ctx, &CC::Z, v854); |
15083 | 0 | let v856 = constructor_select_icmp(ctx, v855, v543.1, v543.2); |
15084 | 0 | let v857 = C::output(ctx, v856); |
15085 | 0 | // Rule at src/isa/x64/lower.isle line 2859. |
15086 | 0 | return Some(v857); |
15087 | 0 | } |
15088 | 0 | } |
15089 | | } |
15090 | | &Opcode::Bitselect => { |
15091 | 0 | let v1 = C::first_result(ctx, arg0); |
15092 | 0 | if let Some(v2) = v1 { |
15093 | 0 | let v3 = C::value_type(ctx, v2); |
15094 | 0 | let v64 = C::multi_lane(ctx, v3); |
15095 | 0 | if let Some(v65) = v64 { |
15096 | 0 | let v543 = C::unpack_value_array_3(ctx, v542); |
15097 | 0 | let v556 = constructor_all_ones_or_all_zeros(ctx, v543.0); |
15098 | 0 | if let Some(v557) = v556 { |
15099 | 0 | let v547 = constructor_put_in_xmm(ctx, v543.0); |
15100 | 0 | let v558 = &C::put_in_xmm_mem(ctx, v543.1); |
15101 | 0 | let v559 = constructor_put_in_xmm(ctx, v543.2); |
15102 | 0 | let v560 = constructor_x64_blend(ctx, v3, v547, v558, v559); |
15103 | 0 | let v561 = constructor_output_xmm(ctx, v560); |
15104 | 0 | // Rule at src/isa/x64/lower.isle line 1205. |
15105 | 0 | return Some(v561); |
15106 | 0 | } |
15107 | 0 | let v547 = constructor_put_in_xmm(ctx, v543.0); |
15108 | 0 | let v548 = constructor_put_in_xmm(ctx, v543.1); |
15109 | 0 | let v549 = &C::xmm_to_xmm_mem(ctx, v547); |
15110 | 0 | let v550 = constructor_sse_and(ctx, v3, v548, v549); |
15111 | 0 | let v551 = &C::put_in_xmm_mem(ctx, v543.2); |
15112 | 0 | let v552 = constructor_sse_and_not(ctx, v3, v547, v551); |
15113 | 0 | let v553 = &C::xmm_to_xmm_mem(ctx, v550); |
15114 | 0 | let v554 = constructor_sse_or(ctx, v3, v552, v553); |
15115 | 0 | let v555 = constructor_output_xmm(ctx, v554); |
15116 | 0 | // Rule at src/isa/x64/lower.isle line 1191. |
15117 | 0 | return Some(v555); |
15118 | 0 | } |
15119 | 0 | } |
15120 | | } |
15121 | | &Opcode::X86Blendv => { |
15122 | 0 | let v1 = C::first_result(ctx, arg0); |
15123 | 0 | if let Some(v2) = v1 { |
15124 | 0 | let v3 = C::value_type(ctx, v2); |
15125 | 0 | match v3 { |
15126 | | I8X16 => { |
15127 | 0 | let v543 = C::unpack_value_array_3(ctx, v542); |
15128 | 0 | let v562 = constructor_put_in_xmm(ctx, v543.2); |
15129 | 0 | let v558 = &C::put_in_xmm_mem(ctx, v543.1); |
15130 | 0 | let v563 = constructor_put_in_xmm(ctx, v543.0); |
15131 | 0 | let v564 = constructor_x64_pblendvb(ctx, v562, v558, v563); |
15132 | 0 | let v565 = constructor_output_xmm(ctx, v564); |
15133 | 0 | // Rule at src/isa/x64/lower.isle line 1225. |
15134 | 0 | return Some(v565); |
15135 | | } |
15136 | | I32X4 => { |
15137 | 0 | let v543 = C::unpack_value_array_3(ctx, v542); |
15138 | 0 | let v562 = constructor_put_in_xmm(ctx, v543.2); |
15139 | 0 | let v558 = &C::put_in_xmm_mem(ctx, v543.1); |
15140 | 0 | let v563 = constructor_put_in_xmm(ctx, v543.0); |
15141 | 0 | let v566 = constructor_x64_blendvps(ctx, v562, v558, v563); |
15142 | 0 | let v567 = constructor_output_xmm(ctx, v566); |
15143 | 0 | // Rule at src/isa/x64/lower.isle line 1229. |
15144 | 0 | return Some(v567); |
15145 | | } |
15146 | | I64X2 => { |
15147 | 0 | let v543 = C::unpack_value_array_3(ctx, v542); |
15148 | 0 | let v562 = constructor_put_in_xmm(ctx, v543.2); |
15149 | 0 | let v558 = &C::put_in_xmm_mem(ctx, v543.1); |
15150 | 0 | let v563 = constructor_put_in_xmm(ctx, v543.0); |
15151 | 0 | let v568 = constructor_x64_blendvpd(ctx, v562, v558, v563); |
15152 | 0 | let v569 = constructor_output_xmm(ctx, v568); |
15153 | 0 | // Rule at src/isa/x64/lower.isle line 1233. |
15154 | 0 | return Some(v569); |
15155 | | } |
15156 | 0 | _ => {} |
15157 | | } |
15158 | 0 | } |
15159 | | } |
15160 | | &Opcode::Fma => { |
15161 | 0 | let v1 = C::first_result(ctx, arg0); |
15162 | 0 | if let Some(v2) = v1 { |
15163 | 0 | let v1248 = C::use_fma(ctx); |
15164 | 0 | if v1248 == true { |
15165 | 0 | let v3 = C::value_type(ctx, v2); |
15166 | 0 | let v543 = C::unpack_value_array_3(ctx, v542); |
15167 | 0 | let v1249 = constructor_fmadd(ctx, v3, v543.0, v543.1, v543.2); |
15168 | 0 | let v1250 = constructor_output_xmm(ctx, v1249); |
15169 | 0 | // Rule at src/isa/x64/lower.isle line 2361. |
15170 | 0 | return Some(v1250); |
15171 | 0 | } |
15172 | 0 | let v3 = C::value_type(ctx, v2); |
15173 | 0 | match v3 { |
15174 | | F32 => { |
15175 | 0 | let v543 = C::unpack_value_array_3(ctx, v542); |
15176 | 0 | let v1169 = C::put_in_reg(ctx, v543.0); |
15177 | 0 | let v1170 = C::put_in_reg(ctx, v543.1); |
15178 | 0 | let v1171 = C::put_in_reg(ctx, v543.2); |
15179 | 0 | let v1172 = C::libcall_3(ctx, &LibCall::FmaF32, v1169, v1170, v1171); |
15180 | 0 | let v1173 = constructor_output_reg(ctx, v1172); |
15181 | 0 | // Rule at src/isa/x64/lower.isle line 2316. |
15182 | 0 | return Some(v1173); |
15183 | | } |
15184 | | F64 => { |
15185 | 0 | let v543 = C::unpack_value_array_3(ctx, v542); |
15186 | 0 | let v1169 = C::put_in_reg(ctx, v543.0); |
15187 | 0 | let v1170 = C::put_in_reg(ctx, v543.1); |
15188 | 0 | let v1171 = C::put_in_reg(ctx, v543.2); |
15189 | 0 | let v1175 = C::libcall_3(ctx, &LibCall::FmaF64, v1169, v1170, v1171); |
15190 | 0 | let v1176 = constructor_output_reg(ctx, v1175); |
15191 | 0 | // Rule at src/isa/x64/lower.isle line 2318. |
15192 | 0 | return Some(v1176); |
15193 | | } |
15194 | | F32X4 => { |
15195 | 0 | let v543 = C::unpack_value_array_3(ctx, v542); |
15196 | 0 | let v547 = constructor_put_in_xmm(ctx, v543.0); |
15197 | 0 | let v548 = constructor_put_in_xmm(ctx, v543.1); |
15198 | 0 | let v559 = constructor_put_in_xmm(ctx, v543.2); |
15199 | 0 | let v1177 = C::xmm_to_reg(ctx, v547); |
15200 | 0 | let v1178 = C::xmm_to_reg(ctx, v548); |
15201 | 0 | let v1179 = C::xmm_to_reg(ctx, v559); |
15202 | 0 | let v1180 = C::libcall_3(ctx, &LibCall::FmaF32, v1177, v1178, v1179); |
15203 | 0 | let v1181 = C::xmm_new(ctx, v1180); |
15204 | 0 | let v1182 = &C::xmm_to_xmm_mem(ctx, v547); |
15205 | 0 | let v1183 = constructor_x64_pshufd(ctx, v1182, 0x1); |
15206 | 0 | let v1184 = C::xmm_to_reg(ctx, v1183); |
15207 | 0 | let v1185 = &C::xmm_to_xmm_mem(ctx, v548); |
15208 | 0 | let v1186 = constructor_x64_pshufd(ctx, v1185, 0x1); |
15209 | 0 | let v1187 = C::xmm_to_reg(ctx, v1186); |
15210 | 0 | let v1188 = &C::xmm_to_xmm_mem(ctx, v559); |
15211 | 0 | let v1189 = constructor_x64_pshufd(ctx, v1188, 0x1); |
15212 | 0 | let v1190 = C::xmm_to_reg(ctx, v1189); |
15213 | 0 | let v1191 = C::libcall_3(ctx, &LibCall::FmaF32, v1184, v1187, v1190); |
15214 | 0 | let v1192 = C::xmm_new(ctx, v1191); |
15215 | 0 | let v1193 = &C::xmm_to_xmm_mem(ctx, v547); |
15216 | 0 | let v1195 = constructor_x64_pshufd(ctx, v1193, 0x2); |
15217 | 0 | let v1196 = C::xmm_to_reg(ctx, v1195); |
15218 | 0 | let v1197 = &C::xmm_to_xmm_mem(ctx, v548); |
15219 | 0 | let v1198 = constructor_x64_pshufd(ctx, v1197, 0x2); |
15220 | 0 | let v1199 = C::xmm_to_reg(ctx, v1198); |
15221 | 0 | let v1200 = &C::xmm_to_xmm_mem(ctx, v559); |
15222 | 0 | let v1201 = constructor_x64_pshufd(ctx, v1200, 0x2); |
15223 | 0 | let v1202 = C::xmm_to_reg(ctx, v1201); |
15224 | 0 | let v1203 = C::libcall_3(ctx, &LibCall::FmaF32, v1196, v1199, v1202); |
15225 | 0 | let v1204 = C::xmm_new(ctx, v1203); |
15226 | 0 | let v1205 = &C::xmm_to_xmm_mem(ctx, v547); |
15227 | 0 | let v1207 = constructor_x64_pshufd(ctx, v1205, 0x3); |
15228 | 0 | let v1208 = C::xmm_to_reg(ctx, v1207); |
15229 | 0 | let v1209 = &C::xmm_to_xmm_mem(ctx, v548); |
15230 | 0 | let v1210 = constructor_x64_pshufd(ctx, v1209, 0x3); |
15231 | 0 | let v1211 = C::xmm_to_reg(ctx, v1210); |
15232 | 0 | let v1212 = &C::xmm_to_xmm_mem(ctx, v559); |
15233 | 0 | let v1213 = constructor_x64_pshufd(ctx, v1212, 0x3); |
15234 | 0 | let v1214 = C::xmm_to_reg(ctx, v1213); |
15235 | 0 | let v1215 = C::libcall_3(ctx, &LibCall::FmaF32, v1208, v1211, v1214); |
15236 | 0 | let v1216 = C::xmm_new(ctx, v1215); |
15237 | 0 | let v1218 = C::xmm_to_reg(ctx, v1192); |
15238 | 0 | let v1219 = &constructor_xmm_to_reg_mem(ctx, v1218); |
15239 | 0 | let v1220 = &C::xmm_mem_to_reg_mem(ctx, v1219); |
15240 | 0 | let v1221 = constructor_vec_insert_lane(ctx, F32X4, v1181, v1220, 0x1); |
15241 | 0 | let v1222 = C::xmm_to_reg(ctx, v1204); |
15242 | 0 | let v1223 = &constructor_xmm_to_reg_mem(ctx, v1222); |
15243 | 0 | let v1224 = &C::xmm_mem_to_reg_mem(ctx, v1223); |
15244 | 0 | let v1225 = constructor_vec_insert_lane(ctx, F32X4, v1221, v1224, 0x2); |
15245 | 0 | let v1226 = C::xmm_to_reg(ctx, v1216); |
15246 | 0 | let v1227 = &constructor_xmm_to_reg_mem(ctx, v1226); |
15247 | 0 | let v1228 = &C::xmm_mem_to_reg_mem(ctx, v1227); |
15248 | 0 | let v1229 = constructor_vec_insert_lane(ctx, F32X4, v1225, v1228, 0x3); |
15249 | 0 | let v1230 = constructor_output_xmm(ctx, v1229); |
15250 | 0 | // Rule at src/isa/x64/lower.isle line 2321. |
15251 | 0 | return Some(v1230); |
15252 | | } |
15253 | | F64X2 => { |
15254 | 0 | let v543 = C::unpack_value_array_3(ctx, v542); |
15255 | 0 | let v547 = constructor_put_in_xmm(ctx, v543.0); |
15256 | 0 | let v548 = constructor_put_in_xmm(ctx, v543.1); |
15257 | 0 | let v559 = constructor_put_in_xmm(ctx, v543.2); |
15258 | 0 | let v1177 = C::xmm_to_reg(ctx, v547); |
15259 | 0 | let v1178 = C::xmm_to_reg(ctx, v548); |
15260 | 0 | let v1179 = C::xmm_to_reg(ctx, v559); |
15261 | 0 | let v1231 = C::libcall_3(ctx, &LibCall::FmaF64, v1177, v1178, v1179); |
15262 | 0 | let v1232 = C::xmm_new(ctx, v1231); |
15263 | 0 | let v1182 = &C::xmm_to_xmm_mem(ctx, v547); |
15264 | 0 | let v1234 = constructor_x64_pshufd(ctx, v1182, 0xEE); |
15265 | 0 | let v1235 = C::xmm_to_reg(ctx, v1234); |
15266 | 0 | let v1185 = &C::xmm_to_xmm_mem(ctx, v548); |
15267 | 0 | let v1236 = constructor_x64_pshufd(ctx, v1185, 0xEE); |
15268 | 0 | let v1237 = C::xmm_to_reg(ctx, v1236); |
15269 | 0 | let v1188 = &C::xmm_to_xmm_mem(ctx, v559); |
15270 | 0 | let v1238 = constructor_x64_pshufd(ctx, v1188, 0xEE); |
15271 | 0 | let v1239 = C::xmm_to_reg(ctx, v1238); |
15272 | 0 | let v1240 = C::libcall_3(ctx, &LibCall::FmaF64, v1235, v1237, v1239); |
15273 | 0 | let v1241 = C::xmm_new(ctx, v1240); |
15274 | 0 | let v1243 = C::xmm_to_reg(ctx, v1241); |
15275 | 0 | let v1244 = &constructor_xmm_to_reg_mem(ctx, v1243); |
15276 | 0 | let v1245 = &C::xmm_mem_to_reg_mem(ctx, v1244); |
15277 | 0 | let v1246 = constructor_vec_insert_lane(ctx, F64X2, v1232, v1245, 0x1); |
15278 | 0 | let v1247 = constructor_output_xmm(ctx, v1246); |
15279 | 0 | // Rule at src/isa/x64/lower.isle line 2345. |
15280 | 0 | return Some(v1247); |
15281 | | } |
15282 | 0 | _ => {} |
15283 | | } |
15284 | 0 | } |
15285 | | } |
15286 | 0 | _ => {} |
15287 | | } |
15288 | | } |
15289 | | &InstructionData::TernaryImm8 { |
15290 | 0 | opcode: ref v570, |
15291 | 0 | args: ref v571, |
15292 | 0 | imm: v572, |
15293 | 0 | } => { |
15294 | 0 | if let &Opcode::Insertlane = v570 { |
15295 | 0 | let v573 = C::unpack_value_array_2(ctx, v571); |
15296 | 0 | let v578 = constructor_put_in_xmm(ctx, v573.0); |
15297 | 0 | let v579 = &C::put_in_reg_mem(ctx, v573.1); |
15298 | 0 | let v576 = C::value_type(ctx, v573.0); |
15299 | 0 | let v577 = C::u8_from_uimm8(ctx, v572); |
15300 | 0 | let v580 = constructor_vec_insert_lane(ctx, v576, v578, v579, v577); |
15301 | 0 | let v581 = constructor_output_xmm(ctx, v580); |
15302 | 0 | // Rule at src/isa/x64/lower.isle line 1239. |
15303 | 0 | return Some(v581); |
15304 | 0 | } |
15305 | | } |
15306 | | &InstructionData::Trap { |
15307 | 87.0k | opcode: ref v618, |
15308 | 87.0k | code: ref v619, |
15309 | 87.0k | } => { |
15310 | 87.0k | match v618 { |
15311 | | &Opcode::Trap => { |
15312 | 87.0k | let v620 = &constructor_x64_ud2(ctx, v619); |
15313 | 87.0k | let v621 = constructor_side_effect(ctx, v620); |
15314 | 87.0k | // Rule at src/isa/x64/lower.isle line 1365. |
15315 | 87.0k | return Some(v621); |
15316 | | } |
15317 | | &Opcode::ResumableTrap => { |
15318 | 0 | let v620 = &constructor_x64_ud2(ctx, v619); |
15319 | 0 | let v621 = constructor_side_effect(ctx, v620); |
15320 | 0 | // Rule at src/isa/x64/lower.isle line 1392. |
15321 | 0 | return Some(v621); |
15322 | | } |
15323 | 0 | _ => {} |
15324 | | } |
15325 | | } |
15326 | | &InstructionData::Unary { |
15327 | 387k | opcode: ref v300, |
15328 | 387k | arg: v301, |
15329 | 387k | } => { |
15330 | 387k | match v300 { |
15331 | | &Opcode::Splat => { |
15332 | 18.4E | let v1 = C::first_result(ctx, arg0); |
15333 | 18.4E | if let Some(v2) = v1 { |
15334 | 18.4E | let v3 = C::value_type(ctx, v2); |
15335 | 18.4E | let v64 = C::multi_lane(ctx, v3); |
15336 | 18.4E | if let Some(v65) = v64 { |
15337 | 18.4E | match v65.0 { |
15338 | | 0x20 => { |
15339 | 18.4E | if v65.1 == 0x4 { |
15340 | 18.4E | let v2109 = &C::sinkable_load(ctx, v301); |
15341 | 18.4E | if let Some(v2110) = v2109 { |
15342 | 18.4E | let v2167 = C::use_avx_simd(ctx); |
15343 | 18.4E | if v2167 == true { |
15344 | 0 | let v2168 = &constructor_sink_load_to_xmm_mem(ctx, v2110); |
15345 | 0 | let v2169 = constructor_x64_vbroadcastss(ctx, v2168); |
15346 | 0 | let v2170 = constructor_output_xmm(ctx, v2169); |
15347 | 0 | // Rule at src/isa/x64/lower.isle line 3843. |
15348 | 0 | return Some(v2170); |
15349 | 0 | } |
15350 | 0 | let v2113 = &C::sink_load(ctx, v2110); |
15351 | 0 | let v2114 = constructor_x64_movss_load(ctx, v2113); |
15352 | 0 | let v2164 = &C::xmm_to_xmm_mem(ctx, v2114); |
15353 | 0 | let v2165 = constructor_x64_shufps(ctx, v2114, v2164, 0x0); |
15354 | 0 | let v2166 = constructor_output_xmm(ctx, v2165); |
15355 | 0 | // Rule at src/isa/x64/lower.isle line 3840. |
15356 | 0 | return Some(v2166); |
15357 | 0 | } |
15358 | 0 | } |
15359 | | } |
15360 | | 0x40 => { |
15361 | 0 | if v65.1 == 0x2 { |
15362 | 0 | let v2109 = &C::sinkable_load(ctx, v301); |
15363 | 0 | if let Some(v2110) = v2109 { |
15364 | 0 | let v2168 = &constructor_sink_load_to_xmm_mem(ctx, v2110); |
15365 | 0 | let v2177 = constructor_x64_movddup(ctx, v2168); |
15366 | 0 | let v2178 = constructor_output_xmm(ctx, v2177); |
15367 | 0 | // Rule at src/isa/x64/lower.isle line 3854. |
15368 | 0 | return Some(v2178); |
15369 | 0 | } |
15370 | 0 | } |
15371 | | } |
15372 | 0 | _ => {} |
15373 | | } |
15374 | 0 | } |
15375 | 0 | match v3 { |
15376 | | I8X16 => { |
15377 | 0 | let v2129 = &C::sinkable_load_exact(ctx, v301); |
15378 | 0 | if let Some(v2130) = v2129 { |
15379 | 0 | let v2125 = C::use_avx2_simd(ctx); |
15380 | 0 | if v2125 == true { |
15381 | 0 | let v2138 = &constructor_sink_load_to_xmm_mem(ctx, v2130); |
15382 | 0 | let v2139 = constructor_x64_vpbroadcastb(ctx, v2138); |
15383 | 0 | let v2140 = constructor_output_xmm(ctx, v2139); |
15384 | 0 | // Rule at src/isa/x64/lower.isle line 3791. |
15385 | 0 | return Some(v2140); |
15386 | 0 | } |
15387 | 0 | let v2131 = constructor_xmm_uninit_value(ctx); |
15388 | 0 | let v2132 = &constructor_sink_load_to_gpr_mem(ctx, v2130); |
15389 | 0 | let v2133 = constructor_x64_pinsrb(ctx, v2131, v2132, 0x0); |
15390 | 0 | let v2134 = constructor_xmm_zero(ctx, I8X16); |
15391 | 0 | let v2135 = &C::xmm_to_xmm_mem(ctx, v2134); |
15392 | 0 | let v2136 = constructor_x64_pshufb(ctx, v2133, v2135); |
15393 | 0 | let v2137 = constructor_output_xmm(ctx, v2136); |
15394 | 0 | // Rule at src/isa/x64/lower.isle line 3789. |
15395 | 0 | return Some(v2137); |
15396 | 0 | } |
15397 | 0 | let v2125 = C::use_avx2_simd(ctx); |
15398 | 0 | if v2125 == true { |
15399 | 0 | let v302 = constructor_put_in_gpr(ctx, v301); |
15400 | 0 | let v2120 = constructor_bitcast_gpr_to_xmm(ctx, I32, v302); |
15401 | 0 | let v2126 = &C::xmm_to_xmm_mem(ctx, v2120); |
15402 | 0 | let v2127 = constructor_x64_vpbroadcastb(ctx, v2126); |
15403 | 0 | let v2128 = constructor_output_xmm(ctx, v2127); |
15404 | 0 | // Rule at src/isa/x64/lower.isle line 3786. |
15405 | 0 | return Some(v2128); |
15406 | 0 | } |
15407 | 0 | let v302 = constructor_put_in_gpr(ctx, v301); |
15408 | 0 | let v2120 = constructor_bitcast_gpr_to_xmm(ctx, I32, v302); |
15409 | 0 | let v2121 = constructor_xmm_zero(ctx, I8X16); |
15410 | 0 | let v2122 = &C::xmm_to_xmm_mem(ctx, v2121); |
15411 | 0 | let v2123 = constructor_x64_pshufb(ctx, v2120, v2122); |
15412 | 0 | let v2124 = constructor_output_xmm(ctx, v2123); |
15413 | 0 | // Rule at src/isa/x64/lower.isle line 3784. |
15414 | 0 | return Some(v2124); |
15415 | | } |
15416 | | I16X8 => { |
15417 | 0 | let v2129 = &C::sinkable_load_exact(ctx, v301); |
15418 | 0 | if let Some(v2130) = v2129 { |
15419 | 0 | let v2125 = C::use_avx2_simd(ctx); |
15420 | 0 | if v2125 == true { |
15421 | 0 | let v2138 = &constructor_sink_load_to_xmm_mem(ctx, v2130); |
15422 | 0 | let v2153 = constructor_x64_vpbroadcastw(ctx, v2138); |
15423 | 0 | let v2154 = constructor_output_xmm(ctx, v2153); |
15424 | 0 | // Rule at src/isa/x64/lower.isle line 3807. |
15425 | 0 | return Some(v2154); |
15426 | 0 | } |
15427 | 0 | let v2131 = constructor_xmm_uninit_value(ctx); |
15428 | 0 | let v2132 = &constructor_sink_load_to_gpr_mem(ctx, v2130); |
15429 | 0 | let v2147 = constructor_x64_pinsrw(ctx, v2131, v2132, 0x0); |
15430 | 0 | let v2148 = &C::xmm_to_xmm_mem(ctx, v2147); |
15431 | 0 | let v2149 = constructor_x64_pshuflw(ctx, v2148, 0x0); |
15432 | 0 | let v2150 = &C::xmm_to_xmm_mem(ctx, v2149); |
15433 | 0 | let v2151 = constructor_x64_pshufd(ctx, v2150, 0x0); |
15434 | 0 | let v2152 = constructor_output_xmm(ctx, v2151); |
15435 | 0 | // Rule at src/isa/x64/lower.isle line 3805. |
15436 | 0 | return Some(v2152); |
15437 | 0 | } |
15438 | 0 | let v2125 = C::use_avx2_simd(ctx); |
15439 | 0 | if v2125 == true { |
15440 | 0 | let v302 = constructor_put_in_gpr(ctx, v301); |
15441 | 0 | let v2120 = constructor_bitcast_gpr_to_xmm(ctx, I32, v302); |
15442 | 0 | let v2126 = &C::xmm_to_xmm_mem(ctx, v2120); |
15443 | 0 | let v2145 = constructor_x64_vpbroadcastw(ctx, v2126); |
15444 | 0 | let v2146 = constructor_output_xmm(ctx, v2145); |
15445 | 0 | // Rule at src/isa/x64/lower.isle line 3802. |
15446 | 0 | return Some(v2146); |
15447 | 0 | } |
15448 | 0 | let v302 = constructor_put_in_gpr(ctx, v301); |
15449 | 0 | let v2120 = constructor_bitcast_gpr_to_xmm(ctx, I32, v302); |
15450 | 0 | let v2126 = &C::xmm_to_xmm_mem(ctx, v2120); |
15451 | 0 | let v2141 = constructor_x64_pshuflw(ctx, v2126, 0x0); |
15452 | 0 | let v2142 = &C::xmm_to_xmm_mem(ctx, v2141); |
15453 | 0 | let v2143 = constructor_x64_pshufd(ctx, v2142, 0x0); |
15454 | 0 | let v2144 = constructor_output_xmm(ctx, v2143); |
15455 | 0 | // Rule at src/isa/x64/lower.isle line 3800. |
15456 | 0 | return Some(v2144); |
15457 | | } |
15458 | | I32X4 => { |
15459 | 0 | let v2125 = C::use_avx2_simd(ctx); |
15460 | 0 | if v2125 == true { |
15461 | 0 | let v302 = constructor_put_in_gpr(ctx, v301); |
15462 | 0 | let v2120 = constructor_bitcast_gpr_to_xmm(ctx, I32, v302); |
15463 | 0 | let v2126 = &C::xmm_to_xmm_mem(ctx, v2120); |
15464 | 0 | let v2157 = constructor_x64_vpbroadcastd(ctx, v2126); |
15465 | 0 | let v2158 = constructor_output_xmm(ctx, v2157); |
15466 | 0 | // Rule at src/isa/x64/lower.isle line 3817. |
15467 | 0 | return Some(v2158); |
15468 | 0 | } |
15469 | 0 | let v302 = constructor_put_in_gpr(ctx, v301); |
15470 | 0 | let v2120 = constructor_bitcast_gpr_to_xmm(ctx, I32, v302); |
15471 | 0 | let v2126 = &C::xmm_to_xmm_mem(ctx, v2120); |
15472 | 0 | let v2155 = constructor_x64_pshufd(ctx, v2126, 0x0); |
15473 | 0 | let v2156 = constructor_output_xmm(ctx, v2155); |
15474 | 0 | // Rule at src/isa/x64/lower.isle line 3815. |
15475 | 0 | return Some(v2156); |
15476 | | } |
15477 | | I64X2 => { |
15478 | 0 | let v302 = constructor_put_in_gpr(ctx, v301); |
15479 | 0 | let v2171 = constructor_bitcast_gpr_to_xmm(ctx, I64, v302); |
15480 | 0 | let v2172 = &C::xmm_to_xmm_mem(ctx, v2171); |
15481 | 0 | let v2173 = constructor_x64_movddup(ctx, v2172); |
15482 | 0 | let v2174 = constructor_output_xmm(ctx, v2173); |
15483 | 0 | // Rule at src/isa/x64/lower.isle line 3850. |
15484 | 0 | return Some(v2174); |
15485 | | } |
15486 | | F32X4 => { |
15487 | 0 | let v2125 = C::use_avx2_simd(ctx); |
15488 | 0 | if v2125 == true { |
15489 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
15490 | 0 | let v2162 = constructor_x64_vbroadcastss(ctx, v459); |
15491 | 0 | let v2163 = constructor_output_xmm(ctx, v2162); |
15492 | 0 | // Rule at src/isa/x64/lower.isle line 3827. |
15493 | 0 | return Some(v2163); |
15494 | 0 | } |
15495 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
15496 | 0 | let v2159 = constructor_put_in_xmm(ctx, v301); |
15497 | 0 | let v317 = &C::put_in_xmm_mem(ctx, v301); |
15498 | 0 | let v2160 = constructor_x64_shufps(ctx, v2159, v317, 0x0); |
15499 | 0 | let v2161 = constructor_output_xmm(ctx, v2160); |
15500 | 0 | // Rule at src/isa/x64/lower.isle line 3824. |
15501 | 0 | return Some(v2161); |
15502 | | } |
15503 | | F64X2 => { |
15504 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
15505 | 0 | let v2175 = constructor_x64_movddup(ctx, v459); |
15506 | 0 | let v2176 = constructor_output_xmm(ctx, v2175); |
15507 | 0 | // Rule at src/isa/x64/lower.isle line 3852. |
15508 | 0 | return Some(v2176); |
15509 | | } |
15510 | 0 | _ => {} |
15511 | | } |
15512 | 0 | } |
15513 | | } |
15514 | | &Opcode::SetPinnedReg => { |
15515 | 0 | let v302 = constructor_put_in_gpr(ctx, v301); |
15516 | 0 | let v1960 = &constructor_write_pinned_gpr(ctx, v302); |
15517 | 0 | let v1961 = constructor_side_effect(ctx, v1960); |
15518 | 0 | // Rule at src/isa/x64/lower.isle line 3543. |
15519 | 0 | return Some(v1961); |
15520 | | } |
15521 | | &Opcode::VanyTrue => { |
15522 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
15523 | 0 | let v1075 = &C::xmm_to_xmm_mem(ctx, v469); |
15524 | 0 | let v2179 = &constructor_x64_ptest(ctx, v1075, v469); |
15525 | 0 | let v2180 = &constructor_x64_setcc(ctx, &CC::NZ); |
15526 | 0 | let v2181 = constructor_with_flags(ctx, v2179, v2180); |
15527 | 0 | let v2182 = C::output(ctx, v2181); |
15528 | 0 | // Rule at src/isa/x64/lower.isle line 3859. |
15529 | 0 | return Some(v2182); |
15530 | | } |
15531 | | &Opcode::VallTrue => { |
15532 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
15533 | 0 | let v529 = C::value_type(ctx, v301); |
15534 | 0 | let v2183 = constructor_xmm_zero(ctx, v529); |
15535 | 0 | let v2184 = constructor_vec_int_type(ctx, v529); |
15536 | 0 | let v2185 = &C::xmm_to_xmm_mem(ctx, v2183); |
15537 | 0 | let v2186 = constructor_x64_pcmpeq(ctx, v2184, v469, v2185); |
15538 | 0 | let v2187 = &C::xmm_to_xmm_mem(ctx, v2186); |
15539 | 0 | let v2188 = &constructor_x64_ptest(ctx, v2187, v2186); |
15540 | 0 | let v2189 = &constructor_x64_setcc(ctx, &CC::Z); |
15541 | 0 | let v2190 = constructor_with_flags(ctx, v2188, v2189); |
15542 | 0 | let v2191 = C::output(ctx, v2190); |
15543 | 0 | // Rule at src/isa/x64/lower.isle line 3865. |
15544 | 0 | return Some(v2191); |
15545 | | } |
15546 | | &Opcode::VhighBits => { |
15547 | 0 | let v529 = C::value_type(ctx, v301); |
15548 | 0 | let v2192 = C::multi_lane(ctx, v529); |
15549 | 0 | if let Some(v2193) = v2192 { |
15550 | 0 | match v2193.0 { |
15551 | | 0x8 => { |
15552 | 0 | if v2193.1 == 0x10 { |
15553 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
15554 | 0 | let v2197 = constructor_x64_pmovmskb(ctx, &OperandSize::Size32, v469); |
15555 | 0 | let v2198 = constructor_output_gpr(ctx, v2197); |
15556 | 0 | // Rule at src/isa/x64/lower.isle line 3882. |
15557 | 0 | return Some(v2198); |
15558 | 0 | } |
15559 | | } |
15560 | | 0x10 => { |
15561 | 0 | if v2193.1 == 0x8 { |
15562 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
15563 | 0 | let v1075 = &C::xmm_to_xmm_mem(ctx, v469); |
15564 | 0 | let v2203 = constructor_x64_packsswb(ctx, v469, v1075); |
15565 | 0 | let v2204 = constructor_x64_pmovmskb(ctx, &OperandSize::Size32, v2203); |
15566 | 0 | let v968 = Imm8Reg::Imm8 { |
15567 | 0 | imm: 0x8, |
15568 | 0 | }; |
15569 | 0 | let v1909 = &C::imm8_reg_to_imm8_gpr(ctx, &v968); |
15570 | 0 | let v2205 = constructor_x64_shr(ctx, I64, v2204, v1909); |
15571 | 0 | let v2206 = constructor_output_gpr(ctx, v2205); |
15572 | 0 | // Rule at src/isa/x64/lower.isle line 3897. |
15573 | 0 | return Some(v2206); |
15574 | 0 | } |
15575 | | } |
15576 | | 0x20 => { |
15577 | 0 | if v2193.1 == 0x4 { |
15578 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
15579 | 0 | let v2199 = constructor_x64_movmskps(ctx, &OperandSize::Size32, v469); |
15580 | 0 | let v2200 = constructor_output_gpr(ctx, v2199); |
15581 | 0 | // Rule at src/isa/x64/lower.isle line 3885. |
15582 | 0 | return Some(v2200); |
15583 | 0 | } |
15584 | | } |
15585 | | 0x40 => { |
15586 | 0 | if v2193.1 == 0x2 { |
15587 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
15588 | 0 | let v2201 = constructor_x64_movmskpd(ctx, &OperandSize::Size32, v469); |
15589 | 0 | let v2202 = constructor_output_gpr(ctx, v2201); |
15590 | 0 | // Rule at src/isa/x64/lower.isle line 3888. |
15591 | 0 | return Some(v2202); |
15592 | 0 | } |
15593 | | } |
15594 | 0 | _ => {} |
15595 | | } |
15596 | 0 | } |
15597 | | } |
15598 | | &Opcode::Ineg => { |
15599 | 817 | let v1 = C::first_result(ctx, arg0); |
15600 | 817 | if let Some(v2) = v1 { |
15601 | 817 | let v3 = C::value_type(ctx, v2); |
15602 | 817 | match v3 { |
15603 | | I8X16 => { |
15604 | 0 | let v315 = constructor_imm(ctx, I8X16, 0x0); |
15605 | 0 | let v316 = C::xmm_new(ctx, v315); |
15606 | 0 | let v317 = &C::put_in_xmm_mem(ctx, v301); |
15607 | 0 | let v318 = constructor_x64_psubb(ctx, v316, v317); |
15608 | 0 | let v319 = constructor_output_xmm(ctx, v318); |
15609 | 0 | // Rule at src/isa/x64/lower.isle line 765. |
15610 | 0 | return Some(v319); |
15611 | | } |
15612 | | I16X8 => { |
15613 | 0 | let v321 = constructor_imm(ctx, I16X8, 0x0); |
15614 | 0 | let v322 = C::xmm_new(ctx, v321); |
15615 | 0 | let v317 = &C::put_in_xmm_mem(ctx, v301); |
15616 | 0 | let v323 = constructor_x64_psubw(ctx, v322, v317); |
15617 | 0 | let v324 = constructor_output_xmm(ctx, v323); |
15618 | 0 | // Rule at src/isa/x64/lower.isle line 768. |
15619 | 0 | return Some(v324); |
15620 | | } |
15621 | | I32X4 => { |
15622 | 0 | let v326 = constructor_imm(ctx, I32X4, 0x0); |
15623 | 0 | let v327 = C::xmm_new(ctx, v326); |
15624 | 0 | let v317 = &C::put_in_xmm_mem(ctx, v301); |
15625 | 0 | let v328 = constructor_x64_psubd(ctx, v327, v317); |
15626 | 0 | let v329 = constructor_output_xmm(ctx, v328); |
15627 | 0 | // Rule at src/isa/x64/lower.isle line 771. |
15628 | 0 | return Some(v329); |
15629 | | } |
15630 | | I64X2 => { |
15631 | 0 | let v331 = constructor_imm(ctx, I64X2, 0x0); |
15632 | 0 | let v332 = C::xmm_new(ctx, v331); |
15633 | 0 | let v317 = &C::put_in_xmm_mem(ctx, v301); |
15634 | 0 | let v333 = constructor_x64_psubq(ctx, v332, v317); |
15635 | 0 | let v334 = constructor_output_xmm(ctx, v333); |
15636 | 0 | // Rule at src/isa/x64/lower.isle line 774. |
15637 | 0 | return Some(v334); |
15638 | | } |
15639 | 817 | _ => {} |
15640 | 817 | } |
15641 | 817 | let v4 = C::fits_in_64(ctx, v3); |
15642 | 817 | if let Some(v5) = v4 { |
15643 | 817 | let v302 = constructor_put_in_gpr(ctx, v301); |
15644 | 817 | let v303 = constructor_x64_neg(ctx, v5, v302); |
15645 | 817 | let v304 = constructor_output_gpr(ctx, v303); |
15646 | 817 | // Rule at src/isa/x64/lower.isle line 751. |
15647 | 817 | return Some(v304); |
15648 | 0 | } |
15649 | 0 | if v3 == I128 { |
15650 | 0 | let v305 = C::put_in_regs(ctx, v301); |
15651 | 0 | let v306 = constructor_value_regs_get_gpr(ctx, v305, 0x0); |
15652 | 0 | let v307 = constructor_value_regs_get_gpr(ctx, v305, 0x1); |
15653 | 0 | let v308 = &constructor_x64_neg_paired(ctx, I64, v306); |
15654 | 0 | let v309 = constructor_imm(ctx, I64, 0x0); |
15655 | 0 | let v310 = C::gpr_new(ctx, v309); |
15656 | 0 | let v311 = &C::gpr_to_gpr_mem_imm(ctx, v307); |
15657 | 0 | let v312 = &constructor_x64_sbb_paired(ctx, I64, v310, v311); |
15658 | 0 | let v313 = constructor_with_flags(ctx, v308, v312); |
15659 | 0 | let v314 = C::output(ctx, v313); |
15660 | 0 | // Rule at src/isa/x64/lower.isle line 754. |
15661 | 0 | return Some(v314); |
15662 | 0 | } |
15663 | 0 | } |
15664 | | } |
15665 | | &Opcode::Iabs => { |
15666 | 0 | let v1 = C::first_result(ctx, arg0); |
15667 | 0 | if let Some(v2) = v1 { |
15668 | 0 | let v3 = C::value_type(ctx, v2); |
15669 | 0 | match v3 { |
15670 | | I8X16 => { |
15671 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
15672 | 0 | let v460 = constructor_x64_pabsb(ctx, v459); |
15673 | 0 | let v461 = constructor_output_xmm(ctx, v460); |
15674 | 0 | // Rule at src/isa/x64/lower.isle line 1040. |
15675 | 0 | return Some(v461); |
15676 | | } |
15677 | | I16X8 => { |
15678 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
15679 | 0 | let v462 = constructor_x64_pabsw(ctx, v459); |
15680 | 0 | let v463 = constructor_output_xmm(ctx, v462); |
15681 | 0 | // Rule at src/isa/x64/lower.isle line 1043. |
15682 | 0 | return Some(v463); |
15683 | | } |
15684 | | I32X4 => { |
15685 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
15686 | 0 | let v464 = constructor_x64_pabsd(ctx, v459); |
15687 | 0 | let v465 = constructor_output_xmm(ctx, v464); |
15688 | 0 | // Rule at src/isa/x64/lower.isle line 1046. |
15689 | 0 | return Some(v465); |
15690 | | } |
15691 | | I64X2 => { |
15692 | 0 | let v363 = C::avx512vl_enabled(ctx, v3); |
15693 | 0 | if v363 == true { |
15694 | 0 | let v466 = C::avx512f_enabled(ctx, v3); |
15695 | 0 | if v466 == true { |
15696 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
15697 | 0 | let v467 = constructor_x64_vpabsq(ctx, v459); |
15698 | 0 | let v468 = constructor_output_xmm(ctx, v467); |
15699 | 0 | // Rule at src/isa/x64/lower.isle line 1050. |
15700 | 0 | return Some(v468); |
15701 | 0 | } |
15702 | 0 | } |
15703 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
15704 | 0 | let v470 = constructor_imm(ctx, I64X2, 0x0); |
15705 | 0 | let v471 = C::xmm_new(ctx, v470); |
15706 | 0 | let v472 = &C::xmm_to_xmm_mem(ctx, v469); |
15707 | 0 | let v473 = constructor_x64_psubq(ctx, v471, v472); |
15708 | 0 | let v474 = &C::xmm_to_xmm_mem(ctx, v469); |
15709 | 0 | let v475 = constructor_x64_blendvpd(ctx, v473, v474, v473); |
15710 | 0 | let v476 = constructor_output_xmm(ctx, v475); |
15711 | 0 | // Rule at src/isa/x64/lower.isle line 1060. |
15712 | 0 | return Some(v476); |
15713 | | } |
15714 | 0 | _ => {} |
15715 | 0 | } |
15716 | 0 | let v4 = C::fits_in_64(ctx, v3); |
15717 | 0 | if let Some(v5) = v4 { |
15718 | 0 | let v302 = constructor_put_in_gpr(ctx, v301); |
15719 | 0 | let v477 = &constructor_x64_neg_paired(ctx, v5, v302); |
15720 | 0 | let v478 = constructor_produces_flags_get_reg(ctx, v477); |
15721 | 0 | let v479 = C::gpr_new(ctx, v478); |
15722 | 0 | let v481 = &C::gpr_to_gpr_mem(ctx, v302); |
15723 | 0 | let v482 = &constructor_cmove(ctx, v5, &CC::S, v481, v479); |
15724 | 0 | let v483 = &constructor_produces_flags_ignore(ctx, v477); |
15725 | 0 | let v484 = constructor_with_flags_reg(ctx, v483, v482); |
15726 | 0 | let v485 = constructor_output_reg(ctx, v484); |
15727 | 0 | // Rule at src/isa/x64/lower.isle line 1067. |
15728 | 0 | return Some(v485); |
15729 | 0 | } |
15730 | 0 | } |
15731 | | } |
15732 | | &Opcode::Bnot => { |
15733 | 487 | let v1 = C::first_result(ctx, arg0); |
15734 | 487 | if let Some(v2) = v1 { |
15735 | 487 | let v3 = C::value_type(ctx, v2); |
15736 | 487 | if v3 == I128 { |
15737 | 0 | let v534 = constructor_i128_not(ctx, v301); |
15738 | 0 | let v535 = C::output(ctx, v534); |
15739 | 0 | // Rule at src/isa/x64/lower.isle line 1176. |
15740 | 0 | return Some(v535); |
15741 | 487 | } |
15742 | 487 | let v64 = C::multi_lane(ctx, v3); |
15743 | 487 | if let Some(v650 ) = v64 { |
15744 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
15745 | 0 | let v496 = constructor_vector_all_ones(ctx); |
15746 | 0 | let v536 = &C::xmm_to_xmm_mem(ctx, v496); |
15747 | 0 | let v539 = constructor_x64_xor_vector(ctx, v3, v469, v536); |
15748 | 0 | let v540 = constructor_output_xmm(ctx, v539); |
15749 | 0 | // Rule at src/isa/x64/lower.isle line 1186. |
15750 | 0 | return Some(v540); |
15751 | 487 | } |
15752 | 487 | let v134 = C::ty_int_ref_scalar_64(ctx, v3); |
15753 | 487 | if let Some(v135) = v134 { |
15754 | 487 | let v302 = constructor_put_in_gpr(ctx, v301); |
15755 | 487 | let v532 = constructor_x64_not(ctx, v3, v302); |
15756 | 487 | let v533 = constructor_output_gpr(ctx, v532); |
15757 | 487 | // Rule at src/isa/x64/lower.isle line 1161. |
15758 | 487 | return Some(v533); |
15759 | 0 | } |
15760 | 0 | let v144 = C::ty_scalar_float(ctx, v3); |
15761 | 0 | if let Some(v145) = v144 { |
15762 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
15763 | 0 | let v496 = constructor_vector_all_ones(ctx); |
15764 | 0 | let v536 = &C::xmm_to_xmm_mem(ctx, v496); |
15765 | 0 | let v537 = constructor_x64_xor_vector(ctx, v145, v469, v536); |
15766 | 0 | let v538 = constructor_output_xmm(ctx, v537); |
15767 | 0 | // Rule at src/isa/x64/lower.isle line 1181. |
15768 | 0 | return Some(v538); |
15769 | 0 | } |
15770 | 0 | } |
15771 | | } |
15772 | | &Opcode::Bitrev => { |
15773 | 0 | let v1 = C::first_result(ctx, arg0); |
15774 | 0 | if let Some(v2) = v1 { |
15775 | 0 | let v3 = C::value_type(ctx, v2); |
15776 | 0 | match v3 { |
15777 | | I8 => { |
15778 | 0 | let v302 = constructor_put_in_gpr(ctx, v301); |
15779 | 0 | let v951 = constructor_do_bitrev8(ctx, I32, v302); |
15780 | 0 | let v952 = constructor_output_gpr(ctx, v951); |
15781 | 0 | // Rule at src/isa/x64/lower.isle line 1861. |
15782 | 0 | return Some(v952); |
15783 | | } |
15784 | | I16 => { |
15785 | 0 | let v302 = constructor_put_in_gpr(ctx, v301); |
15786 | 0 | let v953 = constructor_do_bitrev16(ctx, I32, v302); |
15787 | 0 | let v954 = constructor_output_gpr(ctx, v953); |
15788 | 0 | // Rule at src/isa/x64/lower.isle line 1864. |
15789 | 0 | return Some(v954); |
15790 | | } |
15791 | | I32 => { |
15792 | 0 | let v302 = constructor_put_in_gpr(ctx, v301); |
15793 | 0 | let v955 = constructor_do_bitrev32(ctx, I32, v302); |
15794 | 0 | let v956 = constructor_output_gpr(ctx, v955); |
15795 | 0 | // Rule at src/isa/x64/lower.isle line 1867. |
15796 | 0 | return Some(v956); |
15797 | | } |
15798 | | I64 => { |
15799 | 0 | let v302 = constructor_put_in_gpr(ctx, v301); |
15800 | 0 | let v957 = constructor_do_bitrev64(ctx, I64, v302); |
15801 | 0 | let v958 = constructor_output_gpr(ctx, v957); |
15802 | 0 | // Rule at src/isa/x64/lower.isle line 1870. |
15803 | 0 | return Some(v958); |
15804 | | } |
15805 | | I128 => { |
15806 | 0 | let v305 = C::put_in_regs(ctx, v301); |
15807 | 0 | let v868 = constructor_value_regs_get_gpr(ctx, v305, 0x1); |
15808 | 0 | let v959 = constructor_do_bitrev64(ctx, I64, v868); |
15809 | 0 | let v960 = C::gpr_to_reg(ctx, v959); |
15810 | 0 | let v961 = C::put_in_regs(ctx, v301); |
15811 | 0 | let v962 = constructor_value_regs_get_gpr(ctx, v961, 0x0); |
15812 | 0 | let v963 = constructor_do_bitrev64(ctx, I64, v962); |
15813 | 0 | let v964 = C::gpr_to_reg(ctx, v963); |
15814 | 0 | let v965 = C::value_regs(ctx, v960, v964); |
15815 | 0 | let v966 = C::output(ctx, v965); |
15816 | 0 | // Rule at src/isa/x64/lower.isle line 1873. |
15817 | 0 | return Some(v966); |
15818 | | } |
15819 | 0 | _ => {} |
15820 | | } |
15821 | 0 | } |
15822 | | } |
15823 | | &Opcode::Clz => { |
15824 | 80 | let v1 = C::first_result(ctx, arg0); |
15825 | 80 | if let Some(v2) = v1 { |
15826 | 80 | let v3 = C::value_type(ctx, v2); |
15827 | 80 | let v45 = C::ty_32_or_64(ctx, v3); |
15828 | 80 | if let Some(v46) = v45 { |
15829 | 80 | let v858 = C::use_lzcnt(ctx, v3); |
15830 | 80 | match v858 { |
15831 | | true => { |
15832 | 80 | let v302 = constructor_put_in_gpr(ctx, v301); |
15833 | 80 | let v859 = constructor_x64_lzcnt(ctx, v46, v302); |
15834 | 80 | let v860 = constructor_output_gpr(ctx, v859); |
15835 | 80 | // Rule at src/isa/x64/lower.isle line 1622. |
15836 | 80 | return Some(v860); |
15837 | | } |
15838 | | false => { |
15839 | 0 | let v302 = constructor_put_in_gpr(ctx, v301); |
15840 | 0 | let v861 = constructor_do_clz(ctx, v46, v46, v302); |
15841 | 0 | let v862 = constructor_output_gpr(ctx, v861); |
15842 | 0 | // Rule at src/isa/x64/lower.isle line 1629. |
15843 | 0 | return Some(v862); |
15844 | | } |
15845 | | _ => {} |
15846 | | } |
15847 | 0 | } |
15848 | 0 | let v863 = C::ty_8_or_16(ctx, v3); |
15849 | 0 | if let Some(v864) = v863 { |
15850 | 0 | let v865 = constructor_extend_to_gpr(ctx, v301, I32, &ExtendKind::Zero); |
15851 | 0 | let v866 = constructor_do_clz(ctx, I32, v864, v865); |
15852 | 0 | let v867 = constructor_output_gpr(ctx, v866); |
15853 | 0 | // Rule at src/isa/x64/lower.isle line 1636. |
15854 | 0 | return Some(v867); |
15855 | 0 | } |
15856 | 0 | if v3 == I128 { |
15857 | 0 | let v305 = C::put_in_regs(ctx, v301); |
15858 | 0 | let v868 = constructor_value_regs_get_gpr(ctx, v305, 0x1); |
15859 | 0 | let v869 = constructor_do_clz(ctx, I64, I64, v868); |
15860 | 0 | let v870 = C::put_in_regs(ctx, v301); |
15861 | 0 | let v871 = constructor_value_regs_get_gpr(ctx, v870, 0x0); |
15862 | 0 | let v872 = constructor_do_clz(ctx, I64, I64, v871); |
15863 | 0 | let v874 = RegMemImm::Imm { |
15864 | 0 | simm32: 0x40, |
15865 | 0 | }; |
15866 | 0 | let v875 = &C::gpr_mem_imm_new(ctx, &v874); |
15867 | 0 | let v876 = constructor_x64_add(ctx, I64, v872, v875); |
15868 | 0 | let v878 = &constructor_x64_cmp_imm(ctx, &OperandSize::Size64, 0x40, v869); |
15869 | 0 | let v879 = &C::gpr_to_gpr_mem(ctx, v869); |
15870 | 0 | let v880 = &constructor_cmove(ctx, I64, &CC::NZ, v879, v876); |
15871 | 0 | let v881 = constructor_with_flags_reg(ctx, v878, v880); |
15872 | 0 | let v882 = C::gpr_new(ctx, v881); |
15873 | 0 | let v883 = C::gpr_to_reg(ctx, v882); |
15874 | 0 | let v884 = constructor_imm(ctx, I64, 0x0); |
15875 | 0 | let v885 = C::value_regs(ctx, v883, v884); |
15876 | 0 | let v886 = C::output(ctx, v885); |
15877 | 0 | // Rule at src/isa/x64/lower.isle line 1641. |
15878 | 0 | return Some(v886); |
15879 | 0 | } |
15880 | 0 | } |
15881 | | } |
15882 | | &Opcode::Ctz => { |
15883 | 88 | let v1 = C::first_result(ctx, arg0); |
15884 | 88 | if let Some(v2) = v1 { |
15885 | 88 | let v3 = C::value_type(ctx, v2); |
15886 | 88 | let v45 = C::ty_32_or_64(ctx, v3); |
15887 | 88 | if let Some(v46) = v45 { |
15888 | 88 | let v171 = C::use_bmi1(ctx, v3); |
15889 | 88 | match v171 { |
15890 | | true => { |
15891 | 88 | let v302 = constructor_put_in_gpr(ctx, v301); |
15892 | 88 | let v887 = constructor_x64_tzcnt(ctx, v46, v302); |
15893 | 88 | let v888 = constructor_output_gpr(ctx, v887); |
15894 | 88 | // Rule at src/isa/x64/lower.isle line 1666. |
15895 | 88 | return Some(v888); |
15896 | | } |
15897 | | false => { |
15898 | 0 | let v302 = constructor_put_in_gpr(ctx, v301); |
15899 | 0 | let v889 = constructor_do_ctz(ctx, v46, v46, v302); |
15900 | 0 | let v890 = constructor_output_gpr(ctx, v889); |
15901 | 0 | // Rule at src/isa/x64/lower.isle line 1673. |
15902 | 0 | return Some(v890); |
15903 | | } |
15904 | | _ => {} |
15905 | | } |
15906 | 0 | } |
15907 | 0 | let v863 = C::ty_8_or_16(ctx, v3); |
15908 | 0 | if let Some(v864) = v863 { |
15909 | 0 | let v865 = constructor_extend_to_gpr(ctx, v301, I32, &ExtendKind::Zero); |
15910 | 0 | let v891 = constructor_do_ctz(ctx, I32, v864, v865); |
15911 | 0 | let v892 = constructor_output_gpr(ctx, v891); |
15912 | 0 | // Rule at src/isa/x64/lower.isle line 1680. |
15913 | 0 | return Some(v892); |
15914 | 0 | } |
15915 | 0 | if v3 == I128 { |
15916 | 0 | let v305 = C::put_in_regs(ctx, v301); |
15917 | 0 | let v306 = constructor_value_regs_get_gpr(ctx, v305, 0x0); |
15918 | 0 | let v893 = constructor_do_ctz(ctx, I64, I64, v306); |
15919 | 0 | let v870 = C::put_in_regs(ctx, v301); |
15920 | 0 | let v894 = constructor_value_regs_get_gpr(ctx, v870, 0x1); |
15921 | 0 | let v895 = constructor_do_ctz(ctx, I64, I64, v894); |
15922 | 0 | let v874 = RegMemImm::Imm { |
15923 | 0 | simm32: 0x40, |
15924 | 0 | }; |
15925 | 0 | let v875 = &C::gpr_mem_imm_new(ctx, &v874); |
15926 | 0 | let v896 = constructor_x64_add(ctx, I64, v895, v875); |
15927 | 0 | let v897 = &constructor_x64_cmp_imm(ctx, &OperandSize::Size64, 0x40, v893); |
15928 | 0 | let v898 = &C::gpr_to_gpr_mem(ctx, v896); |
15929 | 0 | let v899 = &constructor_cmove(ctx, I64, &CC::Z, v898, v893); |
15930 | 0 | let v900 = constructor_with_flags_reg(ctx, v897, v899); |
15931 | 0 | let v901 = C::gpr_new(ctx, v900); |
15932 | 0 | let v902 = C::gpr_to_reg(ctx, v901); |
15933 | 0 | let v884 = constructor_imm(ctx, I64, 0x0); |
15934 | 0 | let v903 = C::value_regs(ctx, v902, v884); |
15935 | 0 | let v904 = C::output(ctx, v903); |
15936 | 0 | // Rule at src/isa/x64/lower.isle line 1685. |
15937 | 0 | return Some(v904); |
15938 | 0 | } |
15939 | 0 | } |
15940 | | } |
15941 | | &Opcode::Bswap => { |
15942 | 0 | let v1 = C::first_result(ctx, arg0); |
15943 | 0 | if let Some(v2) = v1 { |
15944 | 0 | let v3 = C::value_type(ctx, v2); |
15945 | 0 | match v3 { |
15946 | | I16 => { |
15947 | 0 | let v302 = constructor_put_in_gpr(ctx, v301); |
15948 | 0 | let v968 = Imm8Reg::Imm8 { |
15949 | 0 | imm: 0x8, |
15950 | 0 | }; |
15951 | 0 | let v969 = &C::imm8_reg_to_imm8_gpr(ctx, &v968); |
15952 | 0 | let v970 = constructor_x64_rotl(ctx, I16, v302, v969); |
15953 | 0 | let v971 = constructor_output_gpr(ctx, v970); |
15954 | 0 | // Rule at src/isa/x64/lower.isle line 1940. |
15955 | 0 | return Some(v971); |
15956 | | } |
15957 | | I32 => { |
15958 | 0 | let v302 = constructor_put_in_gpr(ctx, v301); |
15959 | 0 | let v972 = constructor_x64_bswap(ctx, I32, v302); |
15960 | 0 | let v973 = constructor_output_gpr(ctx, v972); |
15961 | 0 | // Rule at src/isa/x64/lower.isle line 1943. |
15962 | 0 | return Some(v973); |
15963 | | } |
15964 | | I64 => { |
15965 | 0 | let v302 = constructor_put_in_gpr(ctx, v301); |
15966 | 0 | let v974 = constructor_x64_bswap(ctx, I64, v302); |
15967 | 0 | let v975 = constructor_output_gpr(ctx, v974); |
15968 | 0 | // Rule at src/isa/x64/lower.isle line 1946. |
15969 | 0 | return Some(v975); |
15970 | | } |
15971 | | I128 => { |
15972 | 0 | let v305 = C::put_in_regs(ctx, v301); |
15973 | 0 | let v868 = constructor_value_regs_get_gpr(ctx, v305, 0x1); |
15974 | 0 | let v976 = constructor_x64_bswap(ctx, I64, v868); |
15975 | 0 | let v977 = C::gpr_to_reg(ctx, v976); |
15976 | 0 | let v961 = C::put_in_regs(ctx, v301); |
15977 | 0 | let v962 = constructor_value_regs_get_gpr(ctx, v961, 0x0); |
15978 | 0 | let v978 = constructor_x64_bswap(ctx, I64, v962); |
15979 | 0 | let v979 = C::gpr_to_reg(ctx, v978); |
15980 | 0 | let v980 = C::value_regs(ctx, v977, v979); |
15981 | 0 | let v981 = C::output(ctx, v980); |
15982 | 0 | // Rule at src/isa/x64/lower.isle line 1949. |
15983 | 0 | return Some(v981); |
15984 | | } |
15985 | 0 | _ => {} |
15986 | | } |
15987 | 0 | } |
15988 | | } |
15989 | | &Opcode::Popcnt => { |
15990 | 64 | let v1 = C::first_result(ctx, arg0); |
15991 | 64 | if let Some(v2) = v1 { |
15992 | 64 | let v3 = C::value_type(ctx, v2); |
15993 | 64 | let v905 = C::use_popcnt(ctx, v3); |
15994 | 64 | if v905 == true { |
15995 | 64 | let v45 = C::ty_32_or_64(ctx, v3); |
15996 | 64 | if let Some(v46) = v45 { |
15997 | 64 | let v302 = constructor_put_in_gpr(ctx, v301); |
15998 | 64 | let v906 = constructor_x64_popcnt(ctx, v46, v302); |
15999 | 64 | let v907 = constructor_output_gpr(ctx, v906); |
16000 | 64 | // Rule at src/isa/x64/lower.isle line 1704. |
16001 | 64 | return Some(v907); |
16002 | 0 | } |
16003 | 0 | let v863 = C::ty_8_or_16(ctx, v3); |
16004 | 0 | if let Some(v864) = v863 { |
16005 | 0 | let v865 = constructor_extend_to_gpr(ctx, v301, I32, &ExtendKind::Zero); |
16006 | 0 | let v908 = constructor_x64_popcnt(ctx, I32, v865); |
16007 | 0 | let v909 = constructor_output_gpr(ctx, v908); |
16008 | 0 | // Rule at src/isa/x64/lower.isle line 1711. |
16009 | 0 | return Some(v909); |
16010 | 0 | } |
16011 | 0 | if v3 == I128 { |
16012 | 0 | let v305 = C::put_in_regs(ctx, v301); |
16013 | 0 | let v306 = constructor_value_regs_get_gpr(ctx, v305, 0x0); |
16014 | 0 | let v910 = constructor_x64_popcnt(ctx, I64, v306); |
16015 | 0 | let v870 = C::put_in_regs(ctx, v301); |
16016 | 0 | let v894 = constructor_value_regs_get_gpr(ctx, v870, 0x1); |
16017 | 0 | let v911 = constructor_x64_popcnt(ctx, I64, v894); |
16018 | 0 | let v912 = &C::gpr_to_gpr_mem_imm(ctx, v911); |
16019 | 0 | let v913 = constructor_x64_add(ctx, I64, v910, v912); |
16020 | 0 | let v914 = C::gpr_to_reg(ctx, v913); |
16021 | 0 | let v915 = constructor_imm(ctx, I64, 0x0); |
16022 | 0 | let v916 = C::value_regs(ctx, v914, v915); |
16023 | 0 | let v917 = C::output(ctx, v916); |
16024 | 0 | // Rule at src/isa/x64/lower.isle line 1718. |
16025 | 0 | return Some(v917); |
16026 | 0 | } |
16027 | 0 | } |
16028 | 0 | match v3 { |
16029 | | I128 => { |
16030 | 0 | let v305 = C::put_in_regs(ctx, v301); |
16031 | 0 | let v306 = constructor_value_regs_get_gpr(ctx, v305, 0x0); |
16032 | 0 | let v922 = constructor_do_popcnt(ctx, I64, v306); |
16033 | 0 | let v870 = C::put_in_regs(ctx, v301); |
16034 | 0 | let v894 = constructor_value_regs_get_gpr(ctx, v870, 0x1); |
16035 | 0 | let v923 = constructor_do_popcnt(ctx, I64, v894); |
16036 | 0 | let v924 = &C::gpr_to_gpr_mem_imm(ctx, v923); |
16037 | 0 | let v925 = constructor_x64_add(ctx, I64, v922, v924); |
16038 | 0 | let v926 = C::gpr_to_reg(ctx, v925); |
16039 | 0 | let v915 = constructor_imm(ctx, I64, 0x0); |
16040 | 0 | let v927 = C::value_regs(ctx, v926, v915); |
16041 | 0 | let v928 = C::output(ctx, v927); |
16042 | 0 | // Rule at src/isa/x64/lower.isle line 1737. |
16043 | 0 | return Some(v928); |
16044 | | } |
16045 | | I8X16 => { |
16046 | 0 | let v363 = C::avx512vl_enabled(ctx, v3); |
16047 | 0 | if v363 == true { |
16048 | 0 | let v929 = C::avx512bitalg_enabled(ctx, v3); |
16049 | 0 | if v929 == true { |
16050 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16051 | 0 | let v930 = constructor_x64_vpopcntb(ctx, v459); |
16052 | 0 | let v931 = constructor_output_xmm(ctx, v930); |
16053 | 0 | // Rule at src/isa/x64/lower.isle line 1810. |
16054 | 0 | return Some(v931); |
16055 | 0 | } |
16056 | 0 | } |
16057 | 0 | let v932 = C::popcount_4bit_table(ctx); |
16058 | 0 | let v933 = C::popcount_low_mask(ctx); |
16059 | 0 | let v934 = &constructor_const_to_xmm_mem(ctx, v933); |
16060 | 0 | let v935 = constructor_put_in_xmm(ctx, v301); |
16061 | 0 | let v936 = constructor_sse_and(ctx, I8X16, v935, v934); |
16062 | 0 | let v937 = constructor_put_in_xmm(ctx, v301); |
16063 | 0 | let v939 = &C::xmi_imm(ctx, 0x4); |
16064 | 0 | let v940 = constructor_x64_psrlw(ctx, v937, v939); |
16065 | 0 | let v941 = constructor_sse_and(ctx, I8X16, v940, v934); |
16066 | 0 | let v942 = C::popcount_4bit_table(ctx); |
16067 | 0 | let v943 = constructor_x64_xmm_load_const(ctx, I8X16, v942); |
16068 | 0 | let v944 = &C::xmm_to_xmm_mem(ctx, v936); |
16069 | 0 | let v945 = constructor_x64_pshufb(ctx, v943, v944); |
16070 | 0 | let v946 = &C::xmm_to_xmm_mem(ctx, v941); |
16071 | 0 | let v947 = constructor_x64_pshufb(ctx, v943, v946); |
16072 | 0 | let v948 = &C::xmm_to_xmm_mem(ctx, v947); |
16073 | 0 | let v949 = constructor_x64_paddb(ctx, v945, v948); |
16074 | 0 | let v950 = constructor_output_xmm(ctx, v949); |
16075 | 0 | // Rule at src/isa/x64/lower.isle line 1844. |
16076 | 0 | return Some(v950); |
16077 | | } |
16078 | 0 | _ => {} |
16079 | 0 | } |
16080 | 0 | let v45 = C::ty_32_or_64(ctx, v3); |
16081 | 0 | if let Some(v46) = v45 { |
16082 | 0 | let v302 = constructor_put_in_gpr(ctx, v301); |
16083 | 0 | let v918 = constructor_do_popcnt(ctx, v46, v302); |
16084 | 0 | let v919 = constructor_output_gpr(ctx, v918); |
16085 | 0 | // Rule at src/isa/x64/lower.isle line 1727. |
16086 | 0 | return Some(v919); |
16087 | 0 | } |
16088 | 0 | let v863 = C::ty_8_or_16(ctx, v3); |
16089 | 0 | if let Some(v864) = v863 { |
16090 | 0 | let v865 = constructor_extend_to_gpr(ctx, v301, I32, &ExtendKind::Zero); |
16091 | 0 | let v920 = constructor_do_popcnt(ctx, I32, v865); |
16092 | 0 | let v921 = constructor_output_gpr(ctx, v920); |
16093 | 0 | // Rule at src/isa/x64/lower.isle line 1732. |
16094 | 0 | return Some(v921); |
16095 | 0 | } |
16096 | 0 | } |
16097 | | } |
16098 | | &Opcode::Sqrt => { |
16099 | 0 | let v1 = C::first_result(ctx, arg0); |
16100 | 0 | if let Some(v2) = v1 { |
16101 | 0 | let v3 = C::value_type(ctx, v2); |
16102 | 0 | match v3 { |
16103 | | F32 => { |
16104 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16105 | 0 | let v1065 = constructor_x64_sqrtss(ctx, v459); |
16106 | 0 | let v1066 = constructor_output_xmm(ctx, v1065); |
16107 | 0 | // Rule at src/isa/x64/lower.isle line 2095. |
16108 | 0 | return Some(v1066); |
16109 | | } |
16110 | | F64 => { |
16111 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16112 | 0 | let v1067 = constructor_x64_sqrtsd(ctx, v459); |
16113 | 0 | let v1068 = constructor_output_xmm(ctx, v1067); |
16114 | 0 | // Rule at src/isa/x64/lower.isle line 2097. |
16115 | 0 | return Some(v1068); |
16116 | | } |
16117 | | F32X4 => { |
16118 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16119 | 0 | let v1069 = constructor_x64_sqrtps(ctx, v459); |
16120 | 0 | let v1070 = constructor_output_xmm(ctx, v1069); |
16121 | 0 | // Rule at src/isa/x64/lower.isle line 2099. |
16122 | 0 | return Some(v1070); |
16123 | | } |
16124 | | F64X2 => { |
16125 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16126 | 0 | let v1071 = constructor_x64_sqrtpd(ctx, v459); |
16127 | 0 | let v1072 = constructor_output_xmm(ctx, v1071); |
16128 | 0 | // Rule at src/isa/x64/lower.isle line 2101. |
16129 | 0 | return Some(v1072); |
16130 | | } |
16131 | 0 | _ => {} |
16132 | | } |
16133 | 0 | } |
16134 | | } |
16135 | | &Opcode::Fneg => { |
16136 | 0 | let v1 = C::first_result(ctx, arg0); |
16137 | 0 | if let Some(v2) = v1 { |
16138 | 0 | let v3 = C::value_type(ctx, v2); |
16139 | 0 | match v3 { |
16140 | | F32 => { |
16141 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
16142 | 0 | let v508 = constructor_imm(ctx, F32, 0x80000000); |
16143 | 0 | let v509 = &constructor_reg_to_xmm_mem(ctx, v508); |
16144 | 0 | let v510 = constructor_x64_xorps(ctx, v469, v509); |
16145 | 0 | let v511 = constructor_output_xmm(ctx, v510); |
16146 | 0 | // Rule at src/isa/x64/lower.isle line 1099. |
16147 | 0 | return Some(v511); |
16148 | | } |
16149 | | F64 => { |
16150 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
16151 | 0 | let v513 = constructor_imm(ctx, F64, 0x8000000000000000); |
16152 | 0 | let v514 = &constructor_reg_to_xmm_mem(ctx, v513); |
16153 | 0 | let v515 = constructor_x64_xorpd(ctx, v469, v514); |
16154 | 0 | let v516 = constructor_output_xmm(ctx, v515); |
16155 | 0 | // Rule at src/isa/x64/lower.isle line 1102. |
16156 | 0 | return Some(v516); |
16157 | | } |
16158 | | F32X4 => { |
16159 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
16160 | 0 | let v496 = constructor_vector_all_ones(ctx); |
16161 | 0 | let v518 = &C::xmi_imm(ctx, 0x1F); |
16162 | 0 | let v519 = constructor_x64_pslld(ctx, v496, v518); |
16163 | 0 | let v520 = &C::xmm_to_xmm_mem(ctx, v519); |
16164 | 0 | let v521 = constructor_x64_xorps(ctx, v469, v520); |
16165 | 0 | let v522 = constructor_output_xmm(ctx, v521); |
16166 | 0 | // Rule at src/isa/x64/lower.isle line 1105. |
16167 | 0 | return Some(v522); |
16168 | | } |
16169 | | F64X2 => { |
16170 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
16171 | 0 | let v496 = constructor_vector_all_ones(ctx); |
16172 | 0 | let v524 = &C::xmi_imm(ctx, 0x3F); |
16173 | 0 | let v525 = constructor_x64_psllq(ctx, v496, v524); |
16174 | 0 | let v526 = &C::xmm_to_xmm_mem(ctx, v525); |
16175 | 0 | let v527 = constructor_x64_xorpd(ctx, v469, v526); |
16176 | 0 | let v528 = constructor_output_xmm(ctx, v527); |
16177 | 0 | // Rule at src/isa/x64/lower.isle line 1109. |
16178 | 0 | return Some(v528); |
16179 | | } |
16180 | 0 | _ => {} |
16181 | | } |
16182 | 0 | } |
16183 | | } |
16184 | | &Opcode::Fabs => { |
16185 | 0 | let v1 = C::first_result(ctx, arg0); |
16186 | 0 | if let Some(v2) = v1 { |
16187 | 0 | let v3 = C::value_type(ctx, v2); |
16188 | 0 | match v3 { |
16189 | | F32 => { |
16190 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
16191 | 0 | let v487 = constructor_imm(ctx, F32, 0x7FFFFFFF); |
16192 | 0 | let v488 = &constructor_reg_to_xmm_mem(ctx, v487); |
16193 | 0 | let v489 = constructor_x64_andps(ctx, v469, v488); |
16194 | 0 | let v490 = constructor_output_xmm(ctx, v489); |
16195 | 0 | // Rule at src/isa/x64/lower.isle line 1081. |
16196 | 0 | return Some(v490); |
16197 | | } |
16198 | | F64 => { |
16199 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
16200 | 0 | let v492 = constructor_imm(ctx, F64, 0x7FFFFFFFFFFFFFFF); |
16201 | 0 | let v493 = &constructor_reg_to_xmm_mem(ctx, v492); |
16202 | 0 | let v494 = constructor_x64_andpd(ctx, v469, v493); |
16203 | 0 | let v495 = constructor_output_xmm(ctx, v494); |
16204 | 0 | // Rule at src/isa/x64/lower.isle line 1084. |
16205 | 0 | return Some(v495); |
16206 | | } |
16207 | | F32X4 => { |
16208 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
16209 | 0 | let v496 = constructor_vector_all_ones(ctx); |
16210 | 0 | let v498 = &C::xmi_imm(ctx, 0x1); |
16211 | 0 | let v499 = constructor_x64_psrld(ctx, v496, v498); |
16212 | 0 | let v500 = &C::xmm_to_xmm_mem(ctx, v499); |
16213 | 0 | let v501 = constructor_x64_andps(ctx, v469, v500); |
16214 | 0 | let v502 = constructor_output_xmm(ctx, v501); |
16215 | 0 | // Rule at src/isa/x64/lower.isle line 1088. |
16216 | 0 | return Some(v502); |
16217 | | } |
16218 | | F64X2 => { |
16219 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
16220 | 0 | let v496 = constructor_vector_all_ones(ctx); |
16221 | 0 | let v498 = &C::xmi_imm(ctx, 0x1); |
16222 | 0 | let v503 = constructor_x64_psrlq(ctx, v496, v498); |
16223 | 0 | let v504 = &C::xmm_to_xmm_mem(ctx, v503); |
16224 | 0 | let v505 = constructor_x64_andpd(ctx, v469, v504); |
16225 | 0 | let v506 = constructor_output_xmm(ctx, v505); |
16226 | 0 | // Rule at src/isa/x64/lower.isle line 1093. |
16227 | 0 | return Some(v506); |
16228 | | } |
16229 | 0 | _ => {} |
16230 | | } |
16231 | 0 | } |
16232 | | } |
16233 | | &Opcode::Ceil => { |
16234 | 0 | let v1 = C::first_result(ctx, arg0); |
16235 | 0 | if let Some(v2) = v1 { |
16236 | 0 | let v529 = C::value_type(ctx, v301); |
16237 | 0 | match v529 { |
16238 | | F32 => { |
16239 | 0 | let v3 = C::value_type(ctx, v2); |
16240 | 0 | let v1814 = C::use_sse41(ctx, v3); |
16241 | 0 | match v1814 { |
16242 | | true => { |
16243 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16244 | 0 | let v1816 = constructor_x64_roundss(ctx, v459, &RoundImm::RoundUp); |
16245 | 0 | let v1817 = constructor_output_xmm(ctx, v1816); |
16246 | 0 | // Rule at src/isa/x64/lower.isle line 3289. |
16247 | 0 | return Some(v1817); |
16248 | | } |
16249 | | false => { |
16250 | 0 | let v1819 = C::put_in_reg(ctx, v301); |
16251 | 0 | let v1820 = C::libcall_1(ctx, &LibCall::CeilF32, v1819); |
16252 | 0 | let v1821 = constructor_output_reg(ctx, v1820); |
16253 | 0 | // Rule at src/isa/x64/lower.isle line 3292. |
16254 | 0 | return Some(v1821); |
16255 | | } |
16256 | | _ => {} |
16257 | | } |
16258 | | } |
16259 | | F64 => { |
16260 | 0 | let v3 = C::value_type(ctx, v2); |
16261 | 0 | let v1814 = C::use_sse41(ctx, v3); |
16262 | 0 | match v1814 { |
16263 | | true => { |
16264 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16265 | 0 | let v1822 = constructor_x64_roundsd(ctx, v459, &RoundImm::RoundUp); |
16266 | 0 | let v1823 = constructor_output_xmm(ctx, v1822); |
16267 | 0 | // Rule at src/isa/x64/lower.isle line 3295. |
16268 | 0 | return Some(v1823); |
16269 | | } |
16270 | | false => { |
16271 | 0 | let v1819 = C::put_in_reg(ctx, v301); |
16272 | 0 | let v1825 = C::libcall_1(ctx, &LibCall::CeilF64, v1819); |
16273 | 0 | let v1826 = constructor_output_reg(ctx, v1825); |
16274 | 0 | // Rule at src/isa/x64/lower.isle line 3298. |
16275 | 0 | return Some(v1826); |
16276 | | } |
16277 | | _ => {} |
16278 | | } |
16279 | | } |
16280 | | F32X4 => { |
16281 | 0 | let v3 = C::value_type(ctx, v2); |
16282 | 0 | let v1814 = C::use_sse41(ctx, v3); |
16283 | 0 | if v1814 == true { |
16284 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16285 | 0 | let v1827 = constructor_x64_roundps(ctx, v459, &RoundImm::RoundUp); |
16286 | 0 | let v1828 = constructor_output_xmm(ctx, v1827); |
16287 | 0 | // Rule at src/isa/x64/lower.isle line 3301. |
16288 | 0 | return Some(v1828); |
16289 | 0 | } |
16290 | | } |
16291 | | F64X2 => { |
16292 | 0 | let v3 = C::value_type(ctx, v2); |
16293 | 0 | let v1814 = C::use_sse41(ctx, v3); |
16294 | 0 | if v1814 == true { |
16295 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16296 | 0 | let v1829 = constructor_x64_roundpd(ctx, v459, &RoundImm::RoundUp); |
16297 | 0 | let v1830 = constructor_output_xmm(ctx, v1829); |
16298 | 0 | // Rule at src/isa/x64/lower.isle line 3304. |
16299 | 0 | return Some(v1830); |
16300 | 0 | } |
16301 | | } |
16302 | 0 | _ => {} |
16303 | | } |
16304 | 0 | } |
16305 | | } |
16306 | | &Opcode::Floor => { |
16307 | 0 | let v1 = C::first_result(ctx, arg0); |
16308 | 0 | if let Some(v2) = v1 { |
16309 | 0 | let v529 = C::value_type(ctx, v301); |
16310 | 0 | match v529 { |
16311 | | F32 => { |
16312 | 0 | let v3 = C::value_type(ctx, v2); |
16313 | 0 | let v1814 = C::use_sse41(ctx, v3); |
16314 | 0 | match v1814 { |
16315 | | true => { |
16316 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16317 | 0 | let v1832 = constructor_x64_roundss(ctx, v459, &RoundImm::RoundDown); |
16318 | 0 | let v1833 = constructor_output_xmm(ctx, v1832); |
16319 | 0 | // Rule at src/isa/x64/lower.isle line 3309. |
16320 | 0 | return Some(v1833); |
16321 | | } |
16322 | | false => { |
16323 | 0 | let v1819 = C::put_in_reg(ctx, v301); |
16324 | 0 | let v1835 = C::libcall_1(ctx, &LibCall::FloorF32, v1819); |
16325 | 0 | let v1836 = constructor_output_reg(ctx, v1835); |
16326 | 0 | // Rule at src/isa/x64/lower.isle line 3312. |
16327 | 0 | return Some(v1836); |
16328 | | } |
16329 | | _ => {} |
16330 | | } |
16331 | | } |
16332 | | F64 => { |
16333 | 0 | let v3 = C::value_type(ctx, v2); |
16334 | 0 | let v1814 = C::use_sse41(ctx, v3); |
16335 | 0 | match v1814 { |
16336 | | true => { |
16337 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16338 | 0 | let v1837 = constructor_x64_roundsd(ctx, v459, &RoundImm::RoundDown); |
16339 | 0 | let v1838 = constructor_output_xmm(ctx, v1837); |
16340 | 0 | // Rule at src/isa/x64/lower.isle line 3315. |
16341 | 0 | return Some(v1838); |
16342 | | } |
16343 | | false => { |
16344 | 0 | let v1819 = C::put_in_reg(ctx, v301); |
16345 | 0 | let v1840 = C::libcall_1(ctx, &LibCall::FloorF64, v1819); |
16346 | 0 | let v1841 = constructor_output_reg(ctx, v1840); |
16347 | 0 | // Rule at src/isa/x64/lower.isle line 3318. |
16348 | 0 | return Some(v1841); |
16349 | | } |
16350 | | _ => {} |
16351 | | } |
16352 | | } |
16353 | | F32X4 => { |
16354 | 0 | let v3 = C::value_type(ctx, v2); |
16355 | 0 | let v1814 = C::use_sse41(ctx, v3); |
16356 | 0 | if v1814 == true { |
16357 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16358 | 0 | let v1842 = constructor_x64_roundps(ctx, v459, &RoundImm::RoundDown); |
16359 | 0 | let v1843 = constructor_output_xmm(ctx, v1842); |
16360 | 0 | // Rule at src/isa/x64/lower.isle line 3321. |
16361 | 0 | return Some(v1843); |
16362 | 0 | } |
16363 | | } |
16364 | | F64X2 => { |
16365 | 0 | let v3 = C::value_type(ctx, v2); |
16366 | 0 | let v1814 = C::use_sse41(ctx, v3); |
16367 | 0 | if v1814 == true { |
16368 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16369 | 0 | let v1844 = constructor_x64_roundpd(ctx, v459, &RoundImm::RoundDown); |
16370 | 0 | let v1845 = constructor_output_xmm(ctx, v1844); |
16371 | 0 | // Rule at src/isa/x64/lower.isle line 3324. |
16372 | 0 | return Some(v1845); |
16373 | 0 | } |
16374 | | } |
16375 | 0 | _ => {} |
16376 | | } |
16377 | 0 | } |
16378 | | } |
16379 | | &Opcode::Trunc => { |
16380 | 0 | let v1 = C::first_result(ctx, arg0); |
16381 | 0 | if let Some(v2) = v1 { |
16382 | 0 | let v529 = C::value_type(ctx, v301); |
16383 | 0 | match v529 { |
16384 | | F32 => { |
16385 | 0 | let v3 = C::value_type(ctx, v2); |
16386 | 0 | let v1814 = C::use_sse41(ctx, v3); |
16387 | 0 | match v1814 { |
16388 | | true => { |
16389 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16390 | 0 | let v1862 = constructor_x64_roundss(ctx, v459, &RoundImm::RoundZero); |
16391 | 0 | let v1863 = constructor_output_xmm(ctx, v1862); |
16392 | 0 | // Rule at src/isa/x64/lower.isle line 3349. |
16393 | 0 | return Some(v1863); |
16394 | | } |
16395 | | false => { |
16396 | 0 | let v1819 = C::put_in_reg(ctx, v301); |
16397 | 0 | let v1865 = C::libcall_1(ctx, &LibCall::TruncF32, v1819); |
16398 | 0 | let v1866 = constructor_output_reg(ctx, v1865); |
16399 | 0 | // Rule at src/isa/x64/lower.isle line 3352. |
16400 | 0 | return Some(v1866); |
16401 | | } |
16402 | | _ => {} |
16403 | | } |
16404 | | } |
16405 | | F64 => { |
16406 | 0 | let v3 = C::value_type(ctx, v2); |
16407 | 0 | let v1814 = C::use_sse41(ctx, v3); |
16408 | 0 | match v1814 { |
16409 | | true => { |
16410 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16411 | 0 | let v1867 = constructor_x64_roundsd(ctx, v459, &RoundImm::RoundZero); |
16412 | 0 | let v1868 = constructor_output_xmm(ctx, v1867); |
16413 | 0 | // Rule at src/isa/x64/lower.isle line 3355. |
16414 | 0 | return Some(v1868); |
16415 | | } |
16416 | | false => { |
16417 | 0 | let v1819 = C::put_in_reg(ctx, v301); |
16418 | 0 | let v1870 = C::libcall_1(ctx, &LibCall::TruncF64, v1819); |
16419 | 0 | let v1871 = constructor_output_reg(ctx, v1870); |
16420 | 0 | // Rule at src/isa/x64/lower.isle line 3358. |
16421 | 0 | return Some(v1871); |
16422 | | } |
16423 | | _ => {} |
16424 | | } |
16425 | | } |
16426 | | F32X4 => { |
16427 | 0 | let v3 = C::value_type(ctx, v2); |
16428 | 0 | let v1814 = C::use_sse41(ctx, v3); |
16429 | 0 | if v1814 == true { |
16430 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16431 | 0 | let v1872 = constructor_x64_roundps(ctx, v459, &RoundImm::RoundZero); |
16432 | 0 | let v1873 = constructor_output_xmm(ctx, v1872); |
16433 | 0 | // Rule at src/isa/x64/lower.isle line 3361. |
16434 | 0 | return Some(v1873); |
16435 | 0 | } |
16436 | | } |
16437 | | F64X2 => { |
16438 | 0 | let v3 = C::value_type(ctx, v2); |
16439 | 0 | let v1814 = C::use_sse41(ctx, v3); |
16440 | 0 | if v1814 == true { |
16441 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16442 | 0 | let v1874 = constructor_x64_roundpd(ctx, v459, &RoundImm::RoundZero); |
16443 | 0 | let v1875 = constructor_output_xmm(ctx, v1874); |
16444 | 0 | // Rule at src/isa/x64/lower.isle line 3364. |
16445 | 0 | return Some(v1875); |
16446 | 0 | } |
16447 | | } |
16448 | 0 | _ => {} |
16449 | | } |
16450 | 0 | } |
16451 | | } |
16452 | | &Opcode::Nearest => { |
16453 | 0 | let v1 = C::first_result(ctx, arg0); |
16454 | 0 | if let Some(v2) = v1 { |
16455 | 0 | let v529 = C::value_type(ctx, v301); |
16456 | 0 | match v529 { |
16457 | | F32 => { |
16458 | 0 | let v3 = C::value_type(ctx, v2); |
16459 | 0 | let v1814 = C::use_sse41(ctx, v3); |
16460 | 0 | match v1814 { |
16461 | | true => { |
16462 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16463 | 0 | let v1847 = constructor_x64_roundss(ctx, v459, &RoundImm::RoundNearest); |
16464 | 0 | let v1848 = constructor_output_xmm(ctx, v1847); |
16465 | 0 | // Rule at src/isa/x64/lower.isle line 3329. |
16466 | 0 | return Some(v1848); |
16467 | | } |
16468 | | false => { |
16469 | 0 | let v1819 = C::put_in_reg(ctx, v301); |
16470 | 0 | let v1850 = C::libcall_1(ctx, &LibCall::NearestF32, v1819); |
16471 | 0 | let v1851 = constructor_output_reg(ctx, v1850); |
16472 | 0 | // Rule at src/isa/x64/lower.isle line 3332. |
16473 | 0 | return Some(v1851); |
16474 | | } |
16475 | | _ => {} |
16476 | | } |
16477 | | } |
16478 | | F64 => { |
16479 | 0 | let v3 = C::value_type(ctx, v2); |
16480 | 0 | let v1814 = C::use_sse41(ctx, v3); |
16481 | 0 | match v1814 { |
16482 | | true => { |
16483 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16484 | 0 | let v1852 = constructor_x64_roundsd(ctx, v459, &RoundImm::RoundNearest); |
16485 | 0 | let v1853 = constructor_output_xmm(ctx, v1852); |
16486 | 0 | // Rule at src/isa/x64/lower.isle line 3335. |
16487 | 0 | return Some(v1853); |
16488 | | } |
16489 | | false => { |
16490 | 0 | let v1819 = C::put_in_reg(ctx, v301); |
16491 | 0 | let v1855 = C::libcall_1(ctx, &LibCall::NearestF64, v1819); |
16492 | 0 | let v1856 = constructor_output_reg(ctx, v1855); |
16493 | 0 | // Rule at src/isa/x64/lower.isle line 3338. |
16494 | 0 | return Some(v1856); |
16495 | | } |
16496 | | _ => {} |
16497 | | } |
16498 | | } |
16499 | | F32X4 => { |
16500 | 0 | let v3 = C::value_type(ctx, v2); |
16501 | 0 | let v1814 = C::use_sse41(ctx, v3); |
16502 | 0 | if v1814 == true { |
16503 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16504 | 0 | let v1857 = constructor_x64_roundps(ctx, v459, &RoundImm::RoundNearest); |
16505 | 0 | let v1858 = constructor_output_xmm(ctx, v1857); |
16506 | 0 | // Rule at src/isa/x64/lower.isle line 3341. |
16507 | 0 | return Some(v1858); |
16508 | 0 | } |
16509 | | } |
16510 | | F64X2 => { |
16511 | 0 | let v3 = C::value_type(ctx, v2); |
16512 | 0 | let v1814 = C::use_sse41(ctx, v3); |
16513 | 0 | if v1814 == true { |
16514 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16515 | 0 | let v1859 = constructor_x64_roundpd(ctx, v459, &RoundImm::RoundNearest); |
16516 | 0 | let v1860 = constructor_output_xmm(ctx, v1859); |
16517 | 0 | // Rule at src/isa/x64/lower.isle line 3344. |
16518 | 0 | return Some(v1860); |
16519 | 0 | } |
16520 | | } |
16521 | 0 | _ => {} |
16522 | | } |
16523 | 0 | } |
16524 | | } |
16525 | | &Opcode::IsNull => { |
16526 | 0 | let v529 = C::value_type(ctx, v301); |
16527 | 0 | if v529 == R64 { |
16528 | 0 | let v302 = constructor_put_in_gpr(ctx, v301); |
16529 | 0 | let v983 = &constructor_x64_cmp_imm(ctx, &OperandSize::Size64, 0x0, v302); |
16530 | 0 | let v984 = &constructor_x64_setcc(ctx, &CC::Z); |
16531 | 0 | let v985 = constructor_with_flags(ctx, v983, v984); |
16532 | 0 | let v986 = C::output(ctx, v985); |
16533 | 0 | // Rule at src/isa/x64/lower.isle line 1957. |
16534 | 0 | return Some(v986); |
16535 | 0 | } |
16536 | | } |
16537 | | &Opcode::IsInvalid => { |
16538 | 0 | let v529 = C::value_type(ctx, v301); |
16539 | 0 | if v529 == R64 { |
16540 | 0 | let v302 = constructor_put_in_gpr(ctx, v301); |
16541 | 0 | let v988 = &constructor_x64_cmp_imm(ctx, &OperandSize::Size64, 0xFFFFFFFF, v302); |
16542 | 0 | let v984 = &constructor_x64_setcc(ctx, &CC::Z); |
16543 | 0 | let v989 = constructor_with_flags(ctx, v988, v984); |
16544 | 0 | let v990 = C::output(ctx, v989); |
16545 | 0 | // Rule at src/isa/x64/lower.isle line 1965. |
16546 | 0 | return Some(v990); |
16547 | 0 | } |
16548 | | } |
16549 | | &Opcode::ScalarToVector => { |
16550 | 0 | let v2109 = &C::sinkable_load(ctx, v301); |
16551 | 0 | if let Some(v2110) = v2109 { |
16552 | 0 | let v529 = C::value_type(ctx, v301); |
16553 | 0 | let v2116 = C::ty_64(ctx, v529); |
16554 | 0 | if let Some(v2117) = v2116 { |
16555 | 0 | let v2113 = &C::sink_load(ctx, v2110); |
16556 | 0 | let v2118 = constructor_x64_movsd_load(ctx, v2113); |
16557 | 0 | let v2119 = constructor_output_xmm(ctx, v2118); |
16558 | 0 | // Rule at src/isa/x64/lower.isle line 3768. |
16559 | 0 | return Some(v2119); |
16560 | 0 | } |
16561 | 0 | let v2111 = C::ty_32(ctx, v529); |
16562 | 0 | if let Some(v2112) = v2111 { |
16563 | 0 | let v2113 = &C::sink_load(ctx, v2110); |
16564 | 0 | let v2114 = constructor_x64_movss_load(ctx, v2113); |
16565 | 0 | let v2115 = constructor_output_xmm(ctx, v2114); |
16566 | 0 | // Rule at src/isa/x64/lower.isle line 3766. |
16567 | 0 | return Some(v2115); |
16568 | 0 | } |
16569 | 0 | } |
16570 | 0 | let v529 = C::value_type(ctx, v301); |
16571 | 0 | let v1616 = C::ty_scalar_float(ctx, v529); |
16572 | 0 | if let Some(v1617) = v1616 { |
16573 | 0 | let v1009 = constructor_output_value(ctx, v301); |
16574 | 0 | // Rule at src/isa/x64/lower.isle line 3756. |
16575 | 0 | return Some(v1009); |
16576 | 0 | } |
16577 | 0 | let v302 = constructor_put_in_gpr(ctx, v301); |
16578 | 0 | let v2107 = constructor_bitcast_gpr_to_xmm(ctx, v529, v302); |
16579 | 0 | let v2108 = constructor_output_xmm(ctx, v2107); |
16580 | 0 | // Rule at src/isa/x64/lower.isle line 3761. |
16581 | 0 | return Some(v2108); |
16582 | | } |
16583 | | &Opcode::Bmask => { |
16584 | 0 | let v1 = C::first_result(ctx, arg0); |
16585 | 0 | if let Some(v2) = v1 { |
16586 | 0 | let v305 = C::put_in_regs(ctx, v301); |
16587 | 0 | let v3 = C::value_type(ctx, v2); |
16588 | 0 | let v529 = C::value_type(ctx, v301); |
16589 | 0 | let v530 = constructor_lower_bmask(ctx, v3, v529, v305); |
16590 | 0 | let v531 = C::output(ctx, v530); |
16591 | 0 | // Rule at src/isa/x64/lower.isle line 1154. |
16592 | 0 | return Some(v531); |
16593 | 0 | } |
16594 | | } |
16595 | | &Opcode::Ireduce => { |
16596 | 6.29k | let v1 = C::first_result(ctx, arg0); |
16597 | 6.29k | if let Some(v2) = v1 { |
16598 | 6.29k | let v3 = C::value_type(ctx, v2); |
16599 | 6.29k | let v4 = C::fits_in_64(ctx, v3); |
16600 | 6.29k | if let Some(v5) = v4 { |
16601 | 6.29k | let v305 = C::put_in_regs(ctx, v301); |
16602 | 6.29k | let v306 = constructor_value_regs_get_gpr(ctx, v305, 0x0); |
16603 | 6.29k | let v1010 = constructor_output_gpr(ctx, v306); |
16604 | 6.29k | // Rule at src/isa/x64/lower.isle line 2015. |
16605 | 6.29k | return Some(v1010); |
16606 | 0 | } |
16607 | 0 | let v529 = C::value_type(ctx, v301); |
16608 | 0 | if v3 == v529 { |
16609 | 0 | let v1009 = constructor_output_value(ctx, v301); |
16610 | 0 | // Rule at src/isa/x64/lower.isle line 2009. |
16611 | 0 | return Some(v1009); |
16612 | 0 | } |
16613 | 0 | } |
16614 | | } |
16615 | | &Opcode::SwidenLow => { |
16616 | 0 | let v1 = C::first_result(ctx, arg0); |
16617 | 0 | if let Some(v2) = v1 { |
16618 | 0 | let v3 = C::value_type(ctx, v2); |
16619 | 0 | match v3 { |
16620 | | I16X8 => { |
16621 | 0 | let v529 = C::value_type(ctx, v301); |
16622 | 0 | if v529 == I8X16 { |
16623 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16624 | 0 | let v1728 = constructor_x64_pmovsxbw(ctx, v459); |
16625 | 0 | let v1729 = constructor_output_xmm(ctx, v1728); |
16626 | 0 | // Rule at src/isa/x64/lower.isle line 3154. |
16627 | 0 | return Some(v1729); |
16628 | 0 | } |
16629 | | } |
16630 | | I32X4 => { |
16631 | 0 | let v529 = C::value_type(ctx, v301); |
16632 | 0 | if v529 == I16X8 { |
16633 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16634 | 0 | let v1730 = constructor_x64_pmovsxwd(ctx, v459); |
16635 | 0 | let v1731 = constructor_output_xmm(ctx, v1730); |
16636 | 0 | // Rule at src/isa/x64/lower.isle line 3157. |
16637 | 0 | return Some(v1731); |
16638 | 0 | } |
16639 | | } |
16640 | | I64X2 => { |
16641 | 0 | let v529 = C::value_type(ctx, v301); |
16642 | 0 | if v529 == I32X4 { |
16643 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16644 | 0 | let v1732 = constructor_x64_pmovsxdq(ctx, v459); |
16645 | 0 | let v1733 = constructor_output_xmm(ctx, v1732); |
16646 | 0 | // Rule at src/isa/x64/lower.isle line 3160. |
16647 | 0 | return Some(v1733); |
16648 | 0 | } |
16649 | | } |
16650 | 0 | _ => {} |
16651 | | } |
16652 | 0 | } |
16653 | | } |
16654 | | &Opcode::SwidenHigh => { |
16655 | 0 | let v1 = C::first_result(ctx, arg0); |
16656 | 0 | if let Some(v2) = v1 { |
16657 | 0 | let v3 = C::value_type(ctx, v2); |
16658 | 0 | match v3 { |
16659 | | I16X8 => { |
16660 | 0 | let v529 = C::value_type(ctx, v301); |
16661 | 0 | if v529 == I8X16 { |
16662 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
16663 | 0 | let v1075 = &C::xmm_to_xmm_mem(ctx, v469); |
16664 | 0 | let v1734 = constructor_x64_palignr(ctx, v469, v1075, 0x8); |
16665 | 0 | let v1735 = &C::xmm_to_xmm_mem(ctx, v1734); |
16666 | 0 | let v1736 = constructor_x64_pmovsxbw(ctx, v1735); |
16667 | 0 | let v1737 = constructor_output_xmm(ctx, v1736); |
16668 | 0 | // Rule at src/isa/x64/lower.isle line 3165. |
16669 | 0 | return Some(v1737); |
16670 | 0 | } |
16671 | | } |
16672 | | I32X4 => { |
16673 | 0 | let v529 = C::value_type(ctx, v301); |
16674 | 0 | if v529 == I16X8 { |
16675 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
16676 | 0 | let v1075 = &C::xmm_to_xmm_mem(ctx, v469); |
16677 | 0 | let v1734 = constructor_x64_palignr(ctx, v469, v1075, 0x8); |
16678 | 0 | let v1735 = &C::xmm_to_xmm_mem(ctx, v1734); |
16679 | 0 | let v1738 = constructor_x64_pmovsxwd(ctx, v1735); |
16680 | 0 | let v1739 = constructor_output_xmm(ctx, v1738); |
16681 | 0 | // Rule at src/isa/x64/lower.isle line 3169. |
16682 | 0 | return Some(v1739); |
16683 | 0 | } |
16684 | | } |
16685 | | I64X2 => { |
16686 | 0 | let v529 = C::value_type(ctx, v301); |
16687 | 0 | if v529 == I32X4 { |
16688 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16689 | 0 | let v1740 = constructor_x64_pshufd(ctx, v459, 0xEE); |
16690 | 0 | let v1741 = &C::xmm_to_xmm_mem(ctx, v1740); |
16691 | 0 | let v1742 = constructor_x64_pmovsxdq(ctx, v1741); |
16692 | 0 | let v1743 = constructor_output_xmm(ctx, v1742); |
16693 | 0 | // Rule at src/isa/x64/lower.isle line 3173. |
16694 | 0 | return Some(v1743); |
16695 | 0 | } |
16696 | | } |
16697 | 0 | _ => {} |
16698 | | } |
16699 | 0 | } |
16700 | | } |
16701 | | &Opcode::UwidenLow => { |
16702 | 0 | let v1 = C::first_result(ctx, arg0); |
16703 | 0 | if let Some(v2) = v1 { |
16704 | 0 | let v3 = C::value_type(ctx, v2); |
16705 | 0 | match v3 { |
16706 | | I16X8 => { |
16707 | 0 | let v529 = C::value_type(ctx, v301); |
16708 | 0 | if v529 == I8X16 { |
16709 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16710 | 0 | let v1744 = constructor_x64_pmovzxbw(ctx, v459); |
16711 | 0 | let v1745 = constructor_output_xmm(ctx, v1744); |
16712 | 0 | // Rule at src/isa/x64/lower.isle line 3178. |
16713 | 0 | return Some(v1745); |
16714 | 0 | } |
16715 | | } |
16716 | | I32X4 => { |
16717 | 0 | let v529 = C::value_type(ctx, v301); |
16718 | 0 | if v529 == I16X8 { |
16719 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16720 | 0 | let v1746 = constructor_x64_pmovzxwd(ctx, v459); |
16721 | 0 | let v1747 = constructor_output_xmm(ctx, v1746); |
16722 | 0 | // Rule at src/isa/x64/lower.isle line 3181. |
16723 | 0 | return Some(v1747); |
16724 | 0 | } |
16725 | | } |
16726 | | I64X2 => { |
16727 | 0 | let v529 = C::value_type(ctx, v301); |
16728 | 0 | if v529 == I32X4 { |
16729 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16730 | 0 | let v1748 = constructor_x64_pmovzxdq(ctx, v459); |
16731 | 0 | let v1749 = constructor_output_xmm(ctx, v1748); |
16732 | 0 | // Rule at src/isa/x64/lower.isle line 3184. |
16733 | 0 | return Some(v1749); |
16734 | 0 | } |
16735 | | } |
16736 | 0 | _ => {} |
16737 | | } |
16738 | 0 | } |
16739 | | } |
16740 | | &Opcode::UwidenHigh => { |
16741 | 0 | let v1 = C::first_result(ctx, arg0); |
16742 | 0 | if let Some(v2) = v1 { |
16743 | 0 | let v3 = C::value_type(ctx, v2); |
16744 | 0 | match v3 { |
16745 | | I16X8 => { |
16746 | 0 | let v529 = C::value_type(ctx, v301); |
16747 | 0 | if v529 == I8X16 { |
16748 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
16749 | 0 | let v1075 = &C::xmm_to_xmm_mem(ctx, v469); |
16750 | 0 | let v1734 = constructor_x64_palignr(ctx, v469, v1075, 0x8); |
16751 | 0 | let v1735 = &C::xmm_to_xmm_mem(ctx, v1734); |
16752 | 0 | let v1750 = constructor_x64_pmovzxbw(ctx, v1735); |
16753 | 0 | let v1751 = constructor_output_xmm(ctx, v1750); |
16754 | 0 | // Rule at src/isa/x64/lower.isle line 3189. |
16755 | 0 | return Some(v1751); |
16756 | 0 | } |
16757 | | } |
16758 | | I32X4 => { |
16759 | 0 | let v529 = C::value_type(ctx, v301); |
16760 | 0 | if v529 == I16X8 { |
16761 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
16762 | 0 | let v1075 = &C::xmm_to_xmm_mem(ctx, v469); |
16763 | 0 | let v1734 = constructor_x64_palignr(ctx, v469, v1075, 0x8); |
16764 | 0 | let v1735 = &C::xmm_to_xmm_mem(ctx, v1734); |
16765 | 0 | let v1752 = constructor_x64_pmovzxwd(ctx, v1735); |
16766 | 0 | let v1753 = constructor_output_xmm(ctx, v1752); |
16767 | 0 | // Rule at src/isa/x64/lower.isle line 3193. |
16768 | 0 | return Some(v1753); |
16769 | 0 | } |
16770 | | } |
16771 | | I64X2 => { |
16772 | 0 | let v529 = C::value_type(ctx, v301); |
16773 | 0 | if v529 == I32X4 { |
16774 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16775 | 0 | let v1740 = constructor_x64_pshufd(ctx, v459, 0xEE); |
16776 | 0 | let v1741 = &C::xmm_to_xmm_mem(ctx, v1740); |
16777 | 0 | let v1754 = constructor_x64_pmovzxdq(ctx, v1741); |
16778 | 0 | let v1755 = constructor_output_xmm(ctx, v1754); |
16779 | 0 | // Rule at src/isa/x64/lower.isle line 3197. |
16780 | 0 | return Some(v1755); |
16781 | 0 | } |
16782 | | } |
16783 | 0 | _ => {} |
16784 | | } |
16785 | 0 | } |
16786 | | } |
16787 | | &Opcode::Uextend => { |
16788 | 379k | let v1 = C::first_result(ctx, arg0); |
16789 | 379k | if let Some(v2) = v1 { |
16790 | 379k | let v3 = C::value_type(ctx, v2); |
16791 | 379k | match v3 { |
16792 | | I64 => { |
16793 | 373k | let v991 = constructor_extend_to_gpr(ctx, v301, I64, &ExtendKind::Zero); |
16794 | 373k | let v996 = constructor_output_gpr(ctx, v991); |
16795 | 373k | // Rule at src/isa/x64/lower.isle line 1978. |
16796 | 373k | return Some(v996); |
16797 | | } |
16798 | | I128 => { |
16799 | 0 | let v991 = constructor_extend_to_gpr(ctx, v301, I64, &ExtendKind::Zero); |
16800 | 0 | let v992 = C::gpr_to_reg(ctx, v991); |
16801 | 0 | let v993 = constructor_imm(ctx, I64, 0x0); |
16802 | 0 | let v994 = C::value_regs(ctx, v992, v993); |
16803 | 0 | let v995 = C::output(ctx, v994); |
16804 | 0 | // Rule at src/isa/x64/lower.isle line 1974. |
16805 | 0 | return Some(v995); |
16806 | | } |
16807 | 6.19k | _ => {} |
16808 | 6.19k | } |
16809 | 6.19k | let v997 = C::fits_in_32(ctx, v3); |
16810 | 6.19k | if let Some(v9986.18k ) = v997 { |
16811 | 6.18k | let v865 = constructor_extend_to_gpr(ctx, v301, I32, &ExtendKind::Zero); |
16812 | 6.18k | let v999 = constructor_output_gpr(ctx, v865); |
16813 | 6.18k | // Rule at src/isa/x64/lower.isle line 1983. |
16814 | 6.18k | return Some(v999); |
16815 | 0 | } |
16816 | 0 | } |
16817 | | } |
16818 | | &Opcode::Sextend => { |
16819 | 4 | let v1 = C::first_result(ctx, arg0); |
16820 | 4 | if let Some(v2) = v1 { |
16821 | 4 | let v3 = C::value_type(ctx, v2); |
16822 | 4 | match v3 { |
16823 | | I64 => { |
16824 | 4 | let v1000 = constructor_extend_to_gpr(ctx, v301, I64, &ExtendKind::Sign); |
16825 | 4 | let v1006 = constructor_output_gpr(ctx, v1000); |
16826 | 4 | // Rule at src/isa/x64/lower.isle line 1998. |
16827 | 4 | return Some(v1006); |
16828 | | } |
16829 | | I128 => { |
16830 | 0 | let v1000 = constructor_extend_to_gpr(ctx, v301, I64, &ExtendKind::Sign); |
16831 | 0 | let v673 = Imm8Reg::Imm8 { |
16832 | 0 | imm: 0x3F, |
16833 | 0 | }; |
16834 | 0 | let v674 = &C::imm8_reg_to_imm8_gpr(ctx, &v673); |
16835 | 0 | let v1001 = constructor_x64_sar(ctx, I64, v1000, v674); |
16836 | 0 | let v1002 = C::gpr_to_reg(ctx, v1000); |
16837 | 0 | let v1003 = C::gpr_to_reg(ctx, v1001); |
16838 | 0 | let v1004 = C::value_regs(ctx, v1002, v1003); |
16839 | 0 | let v1005 = C::output(ctx, v1004); |
16840 | 0 | // Rule at src/isa/x64/lower.isle line 1992. |
16841 | 0 | return Some(v1005); |
16842 | | } |
16843 | 0 | _ => {} |
16844 | 0 | } |
16845 | 0 | let v997 = C::fits_in_32(ctx, v3); |
16846 | 0 | if let Some(v998) = v997 { |
16847 | 0 | let v1007 = constructor_extend_to_gpr(ctx, v301, I32, &ExtendKind::Sign); |
16848 | 0 | let v1008 = constructor_output_gpr(ctx, v1007); |
16849 | 0 | // Rule at src/isa/x64/lower.isle line 2003. |
16850 | 0 | return Some(v1008); |
16851 | 0 | } |
16852 | 0 | } |
16853 | | } |
16854 | | &Opcode::Fpromote => { |
16855 | 0 | let v1 = C::first_result(ctx, arg0); |
16856 | 0 | if let Some(v2) = v1 { |
16857 | 0 | let v3 = C::value_type(ctx, v2); |
16858 | 0 | if v3 == F64 { |
16859 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16860 | 0 | let v1073 = constructor_x64_cvtss2sd(ctx, v459); |
16861 | 0 | let v1074 = constructor_output_xmm(ctx, v1073); |
16862 | 0 | // Rule at src/isa/x64/lower.isle line 2105. |
16863 | 0 | return Some(v1074); |
16864 | 0 | } |
16865 | 0 | } |
16866 | | } |
16867 | | &Opcode::Fdemote => { |
16868 | 0 | let v1 = C::first_result(ctx, arg0); |
16869 | 0 | if let Some(v2) = v1 { |
16870 | 0 | let v3 = C::value_type(ctx, v2); |
16871 | 0 | if v3 == F32 { |
16872 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16873 | 0 | let v1078 = constructor_x64_cvtsd2ss(ctx, v459); |
16874 | 0 | let v1079 = constructor_output_xmm(ctx, v1078); |
16875 | 0 | // Rule at src/isa/x64/lower.isle line 2113. |
16876 | 0 | return Some(v1079); |
16877 | 0 | } |
16878 | 0 | } |
16879 | | } |
16880 | | &Opcode::Fvdemote => { |
16881 | 0 | let v1 = C::first_result(ctx, arg0); |
16882 | 0 | if let Some(v2) = v1 { |
16883 | 0 | let v3 = C::value_type(ctx, v2); |
16884 | 0 | if v3 == F32X4 { |
16885 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
16886 | 0 | let v1080 = constructor_x64_cvtpd2ps(ctx, v459); |
16887 | 0 | let v1081 = constructor_output_xmm(ctx, v1080); |
16888 | 0 | // Rule at src/isa/x64/lower.isle line 2117. |
16889 | 0 | return Some(v1081); |
16890 | 0 | } |
16891 | 0 | } |
16892 | | } |
16893 | | &Opcode::FvpromoteLow => { |
16894 | 0 | let v1 = C::first_result(ctx, arg0); |
16895 | 0 | if let Some(v2) = v1 { |
16896 | 0 | let v3 = C::value_type(ctx, v2); |
16897 | 0 | if v3 == F64X2 { |
16898 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
16899 | 0 | let v1075 = &C::xmm_to_xmm_mem(ctx, v469); |
16900 | 0 | let v1076 = constructor_x64_cvtps2pd(ctx, v1075); |
16901 | 0 | let v1077 = constructor_output_xmm(ctx, v1076); |
16902 | 0 | // Rule at src/isa/x64/lower.isle line 2109. |
16903 | 0 | return Some(v1077); |
16904 | 0 | } |
16905 | 0 | } |
16906 | | } |
16907 | | &Opcode::FcvtToUint => { |
16908 | 0 | let v1 = C::first_result(ctx, arg0); |
16909 | 0 | if let Some(v2) = v1 { |
16910 | 0 | let v529 = C::value_type(ctx, v301); |
16911 | 0 | let v1616 = C::ty_scalar_float(ctx, v529); |
16912 | 0 | if let Some(v1617) = v1616 { |
16913 | 0 | let v3 = C::value_type(ctx, v2); |
16914 | 0 | let v1618 = constructor_cvt_float_to_uint_seq(ctx, v3, v301, false); |
16915 | 0 | let v1619 = constructor_output_gpr(ctx, v1618); |
16916 | 0 | // Rule at src/isa/x64/lower.isle line 2965. |
16917 | 0 | return Some(v1619); |
16918 | 0 | } |
16919 | 0 | } |
16920 | | } |
16921 | | &Opcode::FcvtToSint => { |
16922 | 0 | let v1 = C::first_result(ctx, arg0); |
16923 | 0 | if let Some(v2) = v1 { |
16924 | 0 | let v529 = C::value_type(ctx, v301); |
16925 | 0 | let v1616 = C::ty_scalar_float(ctx, v529); |
16926 | 0 | if let Some(v1617) = v1616 { |
16927 | 0 | let v3 = C::value_type(ctx, v2); |
16928 | 0 | let v1622 = constructor_cvt_float_to_sint_seq(ctx, v3, v301, false); |
16929 | 0 | let v1623 = constructor_output_gpr(ctx, v1622); |
16930 | 0 | // Rule at src/isa/x64/lower.isle line 2971. |
16931 | 0 | return Some(v1623); |
16932 | 0 | } |
16933 | 0 | } |
16934 | | } |
16935 | | &Opcode::FcvtToUintSat => { |
16936 | 0 | let v1 = C::first_result(ctx, arg0); |
16937 | 0 | if let Some(v2) = v1 { |
16938 | 0 | let v3 = C::value_type(ctx, v2); |
16939 | 0 | if v3 == I32X4 { |
16940 | 0 | let v529 = C::value_type(ctx, v301); |
16941 | 0 | if v529 == F32X4 { |
16942 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
16943 | 0 | let v1640 = constructor_xmm_zero(ctx, F32X4); |
16944 | 0 | let v1641 = &C::xmm_to_xmm_mem(ctx, v1640); |
16945 | 0 | let v1642 = constructor_x64_maxps(ctx, v469, v1641); |
16946 | 0 | let v1643 = &C::xmm_to_xmm_mem(ctx, v1640); |
16947 | 0 | let v1644 = constructor_x64_pcmpeqd(ctx, v1640, v1643); |
16948 | 0 | let v1645 = &C::xmi_imm(ctx, 0x1); |
16949 | 0 | let v1646 = constructor_x64_psrld(ctx, v1644, v1645); |
16950 | 0 | let v1647 = &C::xmm_to_xmm_mem(ctx, v1646); |
16951 | 0 | let v1648 = constructor_x64_cvtdq2ps(ctx, v1647); |
16952 | 0 | let v1649 = &C::xmm_to_xmm_mem(ctx, v1642); |
16953 | 0 | let v1650 = constructor_x64_cvttps2dq(ctx, v1649); |
16954 | 0 | let v1651 = &C::xmm_to_xmm_mem(ctx, v1648); |
16955 | 0 | let v1652 = constructor_x64_subps(ctx, v1642, v1651); |
16956 | 0 | let v1653 = &C::xmm_to_xmm_mem(ctx, v1652); |
16957 | 0 | let v1654 = constructor_x64_cmpps(ctx, v1648, v1653, &FcmpImm::LessThanOrEqual); |
16958 | 0 | let v1655 = &C::xmm_to_xmm_mem(ctx, v1652); |
16959 | 0 | let v1656 = constructor_x64_cvttps2dq(ctx, v1655); |
16960 | 0 | let v1657 = &C::xmm_to_xmm_mem(ctx, v1654); |
16961 | 0 | let v1658 = constructor_x64_pxor(ctx, v1656, v1657); |
16962 | 0 | let v1659 = constructor_xmm_zero(ctx, I32X4); |
16963 | 0 | let v1660 = &C::xmm_to_xmm_mem(ctx, v1659); |
16964 | 0 | let v1661 = constructor_x64_pmaxsd(ctx, v1658, v1660); |
16965 | 0 | let v1662 = &C::xmm_to_xmm_mem(ctx, v1650); |
16966 | 0 | let v1663 = constructor_x64_paddd(ctx, v1661, v1662); |
16967 | 0 | let v1664 = constructor_output_xmm(ctx, v1663); |
16968 | 0 | // Rule at src/isa/x64/lower.isle line 3049. |
16969 | 0 | return Some(v1664); |
16970 | 0 | } |
16971 | 0 | } |
16972 | 0 | let v529 = C::value_type(ctx, v301); |
16973 | 0 | let v1616 = C::ty_scalar_float(ctx, v529); |
16974 | 0 | if let Some(v1617) = v1616 { |
16975 | 0 | let v1620 = constructor_cvt_float_to_uint_seq(ctx, v3, v301, true); |
16976 | 0 | let v1621 = constructor_output_gpr(ctx, v1620); |
16977 | 0 | // Rule at src/isa/x64/lower.isle line 2968. |
16978 | 0 | return Some(v1621); |
16979 | 0 | } |
16980 | 0 | } |
16981 | | } |
16982 | | &Opcode::FcvtToSintSat => { |
16983 | 0 | let v1 = C::first_result(ctx, arg0); |
16984 | 0 | if let Some(v2) = v1 { |
16985 | 0 | let v3 = C::value_type(ctx, v2); |
16986 | 0 | if v3 == I32X4 { |
16987 | 0 | let v529 = C::value_type(ctx, v301); |
16988 | 0 | if v529 == F32X4 { |
16989 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
16990 | 0 | let v1075 = &C::xmm_to_xmm_mem(ctx, v469); |
16991 | 0 | let v1626 = constructor_x64_cmpps(ctx, v469, v1075, &FcmpImm::Equal); |
16992 | 0 | let v1627 = &C::xmm_to_xmm_mem(ctx, v1626); |
16993 | 0 | let v1628 = constructor_x64_andps(ctx, v469, v1627); |
16994 | 0 | let v1629 = &C::xmm_to_xmm_mem(ctx, v1628); |
16995 | 0 | let v1630 = constructor_x64_pxor(ctx, v1626, v1629); |
16996 | 0 | let v1631 = &C::xmm_to_xmm_mem(ctx, v1628); |
16997 | 0 | let v1632 = constructor_x64_cvttps2dq(ctx, v1631); |
16998 | 0 | let v1633 = &C::xmm_to_xmm_mem(ctx, v1630); |
16999 | 0 | let v1634 = constructor_x64_pand(ctx, v1632, v1633); |
17000 | 0 | let v1635 = &C::xmi_imm(ctx, 0x1F); |
17001 | 0 | let v1636 = constructor_x64_psrad(ctx, v1634, v1635); |
17002 | 0 | let v1637 = &C::xmm_to_xmm_mem(ctx, v1632); |
17003 | 0 | let v1638 = constructor_x64_pxor(ctx, v1636, v1637); |
17004 | 0 | let v1639 = constructor_output_xmm(ctx, v1638); |
17005 | 0 | // Rule at src/isa/x64/lower.isle line 2978. |
17006 | 0 | return Some(v1639); |
17007 | 0 | } |
17008 | 0 | } |
17009 | 0 | let v529 = C::value_type(ctx, v301); |
17010 | 0 | let v1616 = C::ty_scalar_float(ctx, v529); |
17011 | 0 | if let Some(v1617) = v1616 { |
17012 | 0 | let v1624 = constructor_cvt_float_to_sint_seq(ctx, v3, v301, true); |
17013 | 0 | let v1625 = constructor_output_gpr(ctx, v1624); |
17014 | 0 | // Rule at src/isa/x64/lower.isle line 2974. |
17015 | 0 | return Some(v1625); |
17016 | 0 | } |
17017 | 0 | } |
17018 | | } |
17019 | | &Opcode::X86Cvtt2dq => { |
17020 | 0 | let v1 = C::first_result(ctx, arg0); |
17021 | 0 | if let Some(v2) = v1 { |
17022 | 0 | let v3 = C::value_type(ctx, v2); |
17023 | 0 | if v3 == I32X4 { |
17024 | 0 | let v529 = C::value_type(ctx, v301); |
17025 | 0 | if v529 == F32X4 { |
17026 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
17027 | 0 | let v1665 = constructor_x64_cvttps2dq(ctx, v459); |
17028 | 0 | let v1666 = constructor_output_xmm(ctx, v1665); |
17029 | 0 | // Rule at src/isa/x64/lower.isle line 3096. |
17030 | 0 | return Some(v1666); |
17031 | 0 | } |
17032 | 0 | } |
17033 | 0 | } |
17034 | | } |
17035 | | &Opcode::FcvtFromUint => { |
17036 | 0 | let v1 = C::first_result(ctx, arg0); |
17037 | 0 | if let Some(v2) = v1 { |
17038 | 0 | let v3 = C::value_type(ctx, v2); |
17039 | 0 | match v3 { |
17040 | | F32 => { |
17041 | 0 | let v529 = C::value_type(ctx, v301); |
17042 | 0 | let v1571 = C::fits_in_32(ctx, v529); |
17043 | 0 | if let Some(v1572) = v1571 { |
17044 | 0 | let v1573 = C::ty_int(ctx, v1572); |
17045 | 0 | if let Some(v1574) = v1573 { |
17046 | 0 | let v991 = constructor_extend_to_gpr(ctx, v301, I64, &ExtendKind::Zero); |
17047 | 0 | let v1575 = &C::gpr_to_gpr_mem(ctx, v991); |
17048 | 0 | let v1576 = constructor_x64_cvtsi2ss(ctx, I64, v1575); |
17049 | 0 | let v1577 = constructor_output_xmm(ctx, v1576); |
17050 | 0 | // Rule at src/isa/x64/lower.isle line 2893. |
17051 | 0 | return Some(v1577); |
17052 | 0 | } |
17053 | 0 | } |
17054 | | } |
17055 | | F64 => { |
17056 | 0 | let v529 = C::value_type(ctx, v301); |
17057 | 0 | let v1571 = C::fits_in_32(ctx, v529); |
17058 | 0 | if let Some(v1572) = v1571 { |
17059 | 0 | let v1573 = C::ty_int(ctx, v1572); |
17060 | 0 | if let Some(v1574) = v1573 { |
17061 | 0 | let v991 = constructor_extend_to_gpr(ctx, v301, I64, &ExtendKind::Zero); |
17062 | 0 | let v1575 = &C::gpr_to_gpr_mem(ctx, v991); |
17063 | 0 | let v1578 = constructor_x64_cvtsi2sd(ctx, I64, v1575); |
17064 | 0 | let v1579 = constructor_output_xmm(ctx, v1578); |
17065 | 0 | // Rule at src/isa/x64/lower.isle line 2896. |
17066 | 0 | return Some(v1579); |
17067 | 0 | } |
17068 | 0 | } |
17069 | | } |
17070 | | F32X4 => { |
17071 | 0 | let v363 = C::avx512vl_enabled(ctx, v3); |
17072 | 0 | if v363 == true { |
17073 | 0 | let v466 = C::avx512f_enabled(ctx, v3); |
17074 | 0 | if v466 == true { |
17075 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
17076 | 0 | let v1596 = constructor_x64_vcvtudq2ps(ctx, v459); |
17077 | 0 | let v1597 = constructor_output_xmm(ctx, v1596); |
17078 | 0 | // Rule at src/isa/x64/lower.isle line 2914. |
17079 | 0 | return Some(v1597); |
17080 | 0 | } |
17081 | 0 | } |
17082 | 0 | let v469 = constructor_put_in_xmm(ctx, v301); |
17083 | 0 | let v1599 = &C::xmi_imm(ctx, 0x10); |
17084 | 0 | let v1600 = constructor_x64_pslld(ctx, v469, v1599); |
17085 | 0 | let v1601 = &C::xmi_imm(ctx, 0x10); |
17086 | 0 | let v1602 = constructor_x64_psrld(ctx, v1600, v1601); |
17087 | 0 | let v1603 = &C::xmm_to_xmm_mem(ctx, v1602); |
17088 | 0 | let v1604 = constructor_x64_psubd(ctx, v469, v1603); |
17089 | 0 | let v1605 = &C::xmm_to_xmm_mem(ctx, v1602); |
17090 | 0 | let v1606 = constructor_x64_cvtdq2ps(ctx, v1605); |
17091 | 0 | let v1607 = &C::xmi_imm(ctx, 0x1); |
17092 | 0 | let v1608 = constructor_x64_psrld(ctx, v1604, v1607); |
17093 | 0 | let v1609 = &C::xmm_to_xmm_mem(ctx, v1608); |
17094 | 0 | let v1610 = constructor_x64_cvtdq2ps(ctx, v1609); |
17095 | 0 | let v1611 = &C::xmm_to_xmm_mem(ctx, v1610); |
17096 | 0 | let v1612 = constructor_x64_addps(ctx, v1610, v1611); |
17097 | 0 | let v1613 = &C::xmm_to_xmm_mem(ctx, v1606); |
17098 | 0 | let v1614 = constructor_x64_addps(ctx, v1612, v1613); |
17099 | 0 | let v1615 = constructor_output_xmm(ctx, v1614); |
17100 | 0 | // Rule at src/isa/x64/lower.isle line 2941. |
17101 | 0 | return Some(v1615); |
17102 | | } |
17103 | | F64X2 => { |
17104 | 0 | let v1582 = C::def_inst(ctx, v301); |
17105 | 0 | if let Some(v1583) = v1582 { |
17106 | 0 | let v1584 = &C::inst_data(ctx, v1583); |
17107 | | if let &InstructionData::Unary { |
17108 | 0 | opcode: ref v1585, |
17109 | 0 | arg: v1586, |
17110 | 0 | } = v1584 { |
17111 | 0 | if let &Opcode::UwidenLow = v1585 { |
17112 | 0 | let v1587 = C::value_type(ctx, v1586); |
17113 | 0 | if v1587 == I32X4 { |
17114 | 0 | let v1588 = C::fcvt_uint_mask_const(ctx); |
17115 | 0 | let v1589 = &constructor_const_to_xmm_mem(ctx, v1588); |
17116 | 0 | let v1590 = constructor_put_in_xmm(ctx, v1586); |
17117 | 0 | let v1591 = constructor_x64_unpcklps(ctx, v1590, v1589); |
17118 | 0 | let v1592 = C::fcvt_uint_mask_high_const(ctx); |
17119 | 0 | let v1593 = &constructor_const_to_xmm_mem(ctx, v1592); |
17120 | 0 | let v1594 = constructor_x64_subpd(ctx, v1591, v1593); |
17121 | 0 | let v1595 = constructor_output_xmm(ctx, v1594); |
17122 | 0 | // Rule at src/isa/x64/lower.isle line 2906. |
17123 | 0 | return Some(v1595); |
17124 | 0 | } |
17125 | 0 | } |
17126 | 0 | } |
17127 | 0 | } |
17128 | | } |
17129 | 0 | _ => {} |
17130 | | } |
17131 | 0 | let v529 = C::value_type(ctx, v301); |
17132 | 0 | if v529 == I64 { |
17133 | 0 | let v302 = constructor_put_in_gpr(ctx, v301); |
17134 | 0 | let v1580 = constructor_cvt_u64_to_float_seq(ctx, v3, v302); |
17135 | 0 | let v1581 = constructor_output_xmm(ctx, v1580); |
17136 | 0 | // Rule at src/isa/x64/lower.isle line 2899. |
17137 | 0 | return Some(v1581); |
17138 | 0 | } |
17139 | 0 | } |
17140 | | } |
17141 | | &Opcode::FcvtFromSint => { |
17142 | 0 | let v1 = C::first_result(ctx, arg0); |
17143 | 0 | if let Some(v2) = v1 { |
17144 | 0 | let v3 = C::value_type(ctx, v2); |
17145 | 0 | match v3 { |
17146 | | F32 => { |
17147 | 0 | let v529 = C::value_type(ctx, v301); |
17148 | 0 | match v529 { |
17149 | | I8 => { |
17150 | 0 | let v1007 = constructor_extend_to_gpr(ctx, v301, I32, &ExtendKind::Sign); |
17151 | 0 | let v1553 = &C::gpr_to_gpr_mem(ctx, v1007); |
17152 | 0 | let v1554 = constructor_x64_cvtsi2ss(ctx, I32, v1553); |
17153 | 0 | let v1555 = constructor_output_xmm(ctx, v1554); |
17154 | 0 | // Rule at src/isa/x64/lower.isle line 2865. |
17155 | 0 | return Some(v1555); |
17156 | | } |
17157 | | I16 => { |
17158 | 0 | let v1007 = constructor_extend_to_gpr(ctx, v301, I32, &ExtendKind::Sign); |
17159 | 0 | let v1553 = &C::gpr_to_gpr_mem(ctx, v1007); |
17160 | 0 | let v1554 = constructor_x64_cvtsi2ss(ctx, I32, v1553); |
17161 | 0 | let v1555 = constructor_output_xmm(ctx, v1554); |
17162 | 0 | // Rule at src/isa/x64/lower.isle line 2868. |
17163 | 0 | return Some(v1555); |
17164 | | } |
17165 | 0 | _ => {} |
17166 | 0 | } |
17167 | 0 | let v1556 = C::ty_int(ctx, v529); |
17168 | 0 | if let Some(v1557) = v1556 { |
17169 | 0 | let v1558 = C::fits_in_64(ctx, v1557); |
17170 | 0 | if let Some(v1559) = v1558 { |
17171 | 0 | let v1560 = &constructor_put_in_gpr_mem(ctx, v301); |
17172 | 0 | let v1561 = constructor_x64_cvtsi2ss(ctx, v1559, v1560); |
17173 | 0 | let v1562 = constructor_output_xmm(ctx, v1561); |
17174 | 0 | // Rule at src/isa/x64/lower.isle line 2871. |
17175 | 0 | return Some(v1562); |
17176 | 0 | } |
17177 | 0 | } |
17178 | | } |
17179 | | F64 => { |
17180 | 0 | let v529 = C::value_type(ctx, v301); |
17181 | 0 | match v529 { |
17182 | | I8 => { |
17183 | 0 | let v1007 = constructor_extend_to_gpr(ctx, v301, I32, &ExtendKind::Sign); |
17184 | 0 | let v1553 = &C::gpr_to_gpr_mem(ctx, v1007); |
17185 | 0 | let v1563 = constructor_x64_cvtsi2sd(ctx, I32, v1553); |
17186 | 0 | let v1564 = constructor_output_xmm(ctx, v1563); |
17187 | 0 | // Rule at src/isa/x64/lower.isle line 2874. |
17188 | 0 | return Some(v1564); |
17189 | | } |
17190 | | I16 => { |
17191 | 0 | let v1007 = constructor_extend_to_gpr(ctx, v301, I32, &ExtendKind::Sign); |
17192 | 0 | let v1553 = &C::gpr_to_gpr_mem(ctx, v1007); |
17193 | 0 | let v1563 = constructor_x64_cvtsi2sd(ctx, I32, v1553); |
17194 | 0 | let v1564 = constructor_output_xmm(ctx, v1563); |
17195 | 0 | // Rule at src/isa/x64/lower.isle line 2877. |
17196 | 0 | return Some(v1564); |
17197 | | } |
17198 | 0 | _ => {} |
17199 | 0 | } |
17200 | 0 | let v1556 = C::ty_int(ctx, v529); |
17201 | 0 | if let Some(v1557) = v1556 { |
17202 | 0 | let v1558 = C::fits_in_64(ctx, v1557); |
17203 | 0 | if let Some(v1559) = v1558 { |
17204 | 0 | let v1560 = &constructor_put_in_gpr_mem(ctx, v301); |
17205 | 0 | let v1565 = constructor_x64_cvtsi2sd(ctx, v1559, v1560); |
17206 | 0 | let v1566 = constructor_output_xmm(ctx, v1565); |
17207 | 0 | // Rule at src/isa/x64/lower.isle line 2880. |
17208 | 0 | return Some(v1566); |
17209 | 0 | } |
17210 | 0 | } |
17211 | | } |
17212 | 0 | _ => {} |
17213 | | } |
17214 | 0 | } |
17215 | 0 | let v529 = C::value_type(ctx, v301); |
17216 | 0 | if v529 == I32X4 { |
17217 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
17218 | 0 | let v1567 = constructor_x64_cvtdq2ps(ctx, v459); |
17219 | 0 | let v1568 = constructor_output_xmm(ctx, v1567); |
17220 | 0 | // Rule at src/isa/x64/lower.isle line 2883. |
17221 | 0 | return Some(v1568); |
17222 | 0 | } |
17223 | | } |
17224 | | &Opcode::FcvtLowFromSint => { |
17225 | 0 | let v459 = &C::put_in_xmm_mem(ctx, v301); |
17226 | 0 | let v1569 = constructor_x64_cvtdq2pd(ctx, v459); |
17227 | 0 | let v1570 = constructor_output_xmm(ctx, v1569); |
17228 | 0 | // Rule at src/isa/x64/lower.isle line 2888. |
17229 | 0 | return Some(v1570); |
17230 | | } |
17231 | | &Opcode::Isplit => { |
17232 | 0 | let v529 = C::value_type(ctx, v301); |
17233 | 0 | if v529 == I128 { |
17234 | 0 | let v305 = C::put_in_regs(ctx, v301); |
17235 | 0 | let v2211 = C::value_regs_get(ctx, v305, 0x0); |
17236 | 0 | let v2212 = C::value_regs_get(ctx, v305, 0x1); |
17237 | 0 | let v2213 = C::value_reg(ctx, v2211); |
17238 | 0 | let v2214 = C::value_reg(ctx, v2212); |
17239 | 0 | let v2215 = C::output_pair(ctx, v2213, v2214); |
17240 | 0 | // Rule at src/isa/x64/lower.isle line 3910. |
17241 | 0 | return Some(v2215); |
17242 | 0 | } |
17243 | | } |
17244 | 0 | _ => {} |
17245 | | } |
17246 | | } |
17247 | | &InstructionData::UnaryConst { |
17248 | 0 | opcode: ref v1962, |
17249 | 0 | constant_handle: v1963, |
17250 | 0 | } => { |
17251 | 0 | if let &Opcode::Vconst = v1962 { |
17252 | 0 | let v1 = C::first_result(ctx, arg0); |
17253 | 0 | if let Some(v2) = v1 { |
17254 | 0 | let v1964 = C::const_to_vconst(ctx, v1963); |
17255 | 0 | let v3 = C::value_type(ctx, v2); |
17256 | 0 | let v1965 = constructor_x64_xmm_load_const(ctx, v3, v1964); |
17257 | 0 | let v1966 = constructor_output_xmm(ctx, v1965); |
17258 | 0 | // Rule at src/isa/x64/lower.isle line 3548. |
17259 | 0 | return Some(v1966); |
17260 | 0 | } |
17261 | 0 | } |
17262 | | } |
17263 | | &InstructionData::UnaryGlobalValue { |
17264 | 0 | opcode: ref v1448, |
17265 | 0 | global_value: v1449, |
17266 | 0 | } => { |
17267 | 0 | match v1448 { |
17268 | | &Opcode::SymbolValue => { |
17269 | 0 | let v1450 = C::symbol_value_data(ctx, v1449); |
17270 | 0 | if let Some(v1451) = v1450 { |
17271 | 0 | let v1455 = constructor_load_ext_name(ctx, v1451.0, v1451.2); |
17272 | 0 | let v1456 = constructor_output_reg(ctx, v1455); |
17273 | 0 | // Rule at src/isa/x64/lower.isle line 2718. |
17274 | 0 | return Some(v1456); |
17275 | 0 | } |
17276 | | } |
17277 | | &Opcode::TlsValue => { |
17278 | 0 | let v1 = C::first_result(ctx, arg0); |
17279 | 0 | if let Some(v2) = v1 { |
17280 | 0 | let v1450 = C::symbol_value_data(ctx, v1449); |
17281 | 0 | if let Some(v1451) = v1450 { |
17282 | 0 | let v3 = C::value_type(ctx, v2); |
17283 | 0 | let v2216 = &C::tls_model(ctx, v3); |
17284 | 0 | match v2216 { |
17285 | | &TlsModel::ElfGd => { |
17286 | 0 | let v2217 = constructor_elf_tls_get_addr(ctx, v1451.0); |
17287 | 0 | let v2218 = constructor_output_gpr(ctx, v2217); |
17288 | 0 | // Rule at src/isa/x64/lower.isle line 3918. |
17289 | 0 | return Some(v2218); |
17290 | | } |
17291 | | &TlsModel::Macho => { |
17292 | 0 | let v2219 = constructor_macho_tls_get_addr(ctx, v1451.0); |
17293 | 0 | let v2220 = constructor_output_gpr(ctx, v2219); |
17294 | 0 | // Rule at src/isa/x64/lower.isle line 3921. |
17295 | 0 | return Some(v2220); |
17296 | | } |
17297 | | &TlsModel::Coff => { |
17298 | 0 | let v2221 = constructor_coff_tls_get_addr(ctx, v1451.0); |
17299 | 0 | let v2222 = constructor_output_gpr(ctx, v2221); |
17300 | 0 | // Rule at src/isa/x64/lower.isle line 3924. |
17301 | 0 | return Some(v2222); |
17302 | | } |
17303 | 0 | _ => {} |
17304 | | } |
17305 | 0 | } |
17306 | 0 | } |
17307 | | } |
17308 | 0 | _ => {} |
17309 | | } |
17310 | | } |
17311 | | &InstructionData::UnaryIeee32 { |
17312 | 0 | opcode: ref v18, |
17313 | 0 | imm: v19, |
17314 | 0 | } => { |
17315 | 0 | if let &Opcode::F32const = v18 { |
17316 | 0 | let v20 = C::u32_from_ieee32(ctx, v19); |
17317 | 0 | let v22 = C::u32_as_u64(ctx, v20); |
17318 | 0 | let v23 = constructor_imm(ctx, F32, v22); |
17319 | 0 | let v24 = constructor_output_reg(ctx, v23); |
17320 | 0 | // Rule at src/isa/x64/lower.isle line 27. |
17321 | 0 | return Some(v24); |
17322 | 0 | } |
17323 | | } |
17324 | | &InstructionData::UnaryIeee64 { |
17325 | 0 | opcode: ref v25, |
17326 | 0 | imm: v26, |
17327 | 0 | } => { |
17328 | 0 | if let &Opcode::F64const = v25 { |
17329 | 0 | let v27 = C::u64_from_ieee64(ctx, v26); |
17330 | 0 | let v29 = constructor_imm(ctx, F64, v27); |
17331 | 0 | let v30 = constructor_output_reg(ctx, v29); |
17332 | 0 | // Rule at src/isa/x64/lower.isle line 32. |
17333 | 0 | return Some(v30); |
17334 | 0 | } |
17335 | | } |
17336 | | &InstructionData::UnaryImm { |
17337 | 387k | opcode: ref v7, |
17338 | 387k | imm: v8, |
17339 | 387k | } => { |
17340 | 387k | if let &Opcode::Iconst = v7 { |
17341 | 387k | let v1 = C::first_result(ctx, arg0); |
17342 | 387k | if let Some(v2) = v1 { |
17343 | 387k | let v3 = C::value_type(ctx, v2); |
17344 | 387k | if v3 == I128 { |
17345 | 0 | let v9 = C::u64_from_imm64(ctx, v8); |
17346 | 0 | let v13 = constructor_imm(ctx, I64, v9); |
17347 | 0 | let v15 = constructor_imm(ctx, I64, 0x0); |
17348 | 0 | let v16 = C::value_regs(ctx, v13, v15); |
17349 | 0 | let v17 = C::output(ctx, v16); |
17350 | 0 | // Rule at src/isa/x64/lower.isle line 20. |
17351 | 0 | return Some(v17); |
17352 | 387k | } |
17353 | 387k | let v4 = C::fits_in_64(ctx, v3); |
17354 | 387k | if let Some(v5387k ) = v4 { |
17355 | 387k | let v9 = C::u64_from_imm64(ctx, v8); |
17356 | 387k | let v10 = constructor_imm(ctx, v5, v9); |
17357 | 387k | let v11 = constructor_output_reg(ctx, v10); |
17358 | 387k | // Rule at src/isa/x64/lower.isle line 15. |
17359 | 387k | return Some(v11); |
17360 | 0 | } |
17361 | 0 | } |
17362 | 0 | } |
17363 | | } |
17364 | 0 | _ => {} |
17365 | | } |
17366 | 0 | None |
17367 | 2.67M | } |
17368 | | |
17369 | | // Generated as internal constructor for term lower_branch. |
17370 | 396k | pub fn constructor_lower_branch<C: Context>( |
17371 | 396k | ctx: &mut C, |
17372 | 396k | arg0: Inst, |
17373 | 396k | arg1: &MachLabelSlice, |
17374 | 396k | ) -> Option<Unit> { |
17375 | 396k | let v1 = &C::inst_data(ctx, arg0); |
17376 | 396k | match v1 { |
17377 | | &InstructionData::BranchTable { |
17378 | 7.48k | opcode: ref v55, |
17379 | 7.48k | arg: v56, |
17380 | 7.48k | table: v57, |
17381 | 7.48k | } => { |
17382 | 7.48k | if let &Opcode::BrTable = v55 { |
17383 | 7.48k | let v59 = C::jump_table_targets(ctx, arg1); |
17384 | 7.52k | if let Some(v60) = v597.48k { |
17385 | 7.52k | let v58 = C::value_type(ctx, v56); |
17386 | 7.52k | let v63 = &C::raw_operand_size_of_type(ctx, v58); |
17387 | 7.52k | let v64 = C::jump_table_size(ctx, &v60.1); |
17388 | 7.52k | let v65 = C::u32_as_u64(ctx, v64); |
17389 | 7.52k | let v66 = constructor_imm(ctx, v58, v65); |
17390 | 7.52k | let v69 = constructor_extend_to_gpr(ctx, v56, I64, &ExtendKind::Zero); |
17391 | 7.52k | let v70 = &constructor_reg_to_gpr_mem_imm(ctx, v66); |
17392 | 7.52k | let v71 = &constructor_x64_cmp(ctx, v63, v70, v69); |
17393 | 7.52k | let v73 = &C::gpr_to_gpr_mem(ctx, v69); |
17394 | 7.52k | let v74 = C::gpr_new(ctx, v66); |
17395 | 7.52k | let v75 = &constructor_cmove(ctx, v58, &CC::B, v73, v74); |
17396 | 7.52k | let v76 = constructor_with_flags_reg(ctx, v71, v75); |
17397 | 7.52k | let v77 = C::gpr_new(ctx, v76); |
17398 | 7.52k | let v78 = &constructor_jmp_table_seq(ctx, v58, v77, v60.0, &v60.1); |
17399 | 7.52k | let v79 = constructor_emit_side_effect(ctx, v78); |
17400 | 7.52k | // Rule at src/isa/x64/lower.isle line 2839. |
17401 | 7.52k | return Some(v79); |
17402 | 0 | } |
17403 | 0 | } |
17404 | | } |
17405 | | &InstructionData::Brif { |
17406 | 233k | opcode: ref v9, |
17407 | 233k | arg: v10, |
17408 | 233k | blocks: ref v11, |
17409 | 233k | } => { |
17410 | 233k | if let &Opcode::Brif = v9 { |
17411 | 233k | let v26 = C::two_targets(ctx, arg1); |
17412 | 233k | if let Some(v27) = v26 { |
17413 | 233k | let v12 = C::maybe_uextend(ctx, v10); |
17414 | 233k | if let Some(v13) = v12 { |
17415 | 233k | let v14 = C::def_inst(ctx, v13); |
17416 | 233k | if let Some(v15207k ) = v14 { |
17417 | 207k | let v16 = &C::inst_data(ctx, v15); |
17418 | 207k | match v16 { |
17419 | | &InstructionData::FloatCompare { |
17420 | 18.4E | opcode: ref v33, |
17421 | 18.4E | args: ref v34, |
17422 | 18.4E | cond: ref v35, |
17423 | 18.4E | } => { |
17424 | 18.4E | if let &Opcode::Fcmp = v33 { |
17425 | 0 | let v36 = C::unpack_value_array_2(ctx, v34); |
17426 | 0 | let v39 = &constructor_emit_fcmp(ctx, v35, v36.0, v36.1); |
17427 | 0 | let v40 = &constructor_jmp_cond_fcmp(ctx, v39, v27.0, v27.1); |
17428 | 0 | let v41 = constructor_emit_side_effect(ctx, v40); |
17429 | 0 | // Rule at src/isa/x64/lower.isle line 2800. |
17430 | 0 | return Some(v41); |
17431 | 0 | } |
17432 | | } |
17433 | | &InstructionData::IntCompare { |
17434 | 163k | opcode: ref v17, |
17435 | 163k | args: ref v18, |
17436 | 163k | cond: ref v19, |
17437 | 163k | } => { |
17438 | 163k | if let &Opcode::Icmp = v17 { |
17439 | 163k | let v20 = C::unpack_value_array_2(ctx, v18); |
17440 | 163k | let v30 = &constructor_emit_cmp(ctx, v19, v20.0, v20.1); |
17441 | 163k | let v31 = &constructor_jmp_cond_icmp(ctx, v30, v27.0, v27.1); |
17442 | 163k | let v32 = constructor_emit_side_effect(ctx, v31); |
17443 | 163k | // Rule at src/isa/x64/lower.isle line 2797. |
17444 | 163k | return Some(v32); |
17445 | 0 | } |
17446 | | } |
17447 | 44.3k | _ => {} |
17448 | | } |
17449 | 25.7k | } |
17450 | 0 | } |
17451 | 70.1k | let v42 = C::value_type(ctx, v10); |
17452 | 70.1k | if v42 == I128 { |
17453 | 0 | let v44 = C::put_in_regs(ctx, v10); |
17454 | 0 | let v45 = &constructor_cmp_zero_i128(ctx, &CC::Z, v44); |
17455 | 0 | let v46 = &constructor_jmp_cond_icmp(ctx, v45, v27.0, v27.1); |
17456 | 0 | let v47 = constructor_emit_side_effect(ctx, v46); |
17457 | 0 | // Rule at src/isa/x64/lower.isle line 2803. |
17458 | 0 | return Some(v47); |
17459 | 70.1k | } |
17460 | 70.1k | let v48 = C::ty_int_bool_or_ref(ctx, v42); |
17461 | 70.1k | if let Some(v4970.1k ) = v48 { |
17462 | 70.1k | let v50 = &constructor_cmp_zero_int_bool_ref(ctx, v10); |
17463 | 70.1k | let v52 = &constructor_jmp_cond(ctx, &CC::NZ, v27.0, v27.1); |
17464 | 70.1k | let v53 = &constructor_with_flags_side_effect(ctx, v50, v52); |
17465 | 70.1k | let v54 = constructor_emit_side_effect(ctx, v53); |
17466 | 70.1k | // Rule at src/isa/x64/lower.isle line 2807. |
17467 | 70.1k | return Some(v54); |
17468 | 0 | } |
17469 | 0 | } |
17470 | 0 | } |
17471 | | } |
17472 | | &InstructionData::Jump { |
17473 | 155k | opcode: ref v2, |
17474 | 155k | destination: v3, |
17475 | 155k | } => { |
17476 | 155k | if let &Opcode::Jump = v2 { |
17477 | 155k | let v5 = C::single_target(ctx, arg1); |
17478 | 155k | if let Some(v6) = v5 { |
17479 | 155k | let v7 = &constructor_jmp_known(ctx, v6); |
17480 | 155k | let v8 = constructor_emit_side_effect(ctx, v7); |
17481 | 155k | // Rule at src/isa/x64/lower.isle line 2792. |
17482 | 155k | return Some(v8); |
17483 | 0 | } |
17484 | 0 | } |
17485 | | } |
17486 | 0 | _ => {} |
17487 | | } |
17488 | 0 | None |
17489 | 396k | } |
17490 | | |
17491 | | // Generated as internal constructor for term sse_and. |
17492 | 0 | pub fn constructor_sse_and<C: Context>( |
17493 | 0 | ctx: &mut C, |
17494 | 0 | arg0: Type, |
17495 | 0 | arg1: Xmm, |
17496 | 0 | arg2: &XmmMem, |
17497 | 0 | ) -> Xmm { |
17498 | 0 | match arg0 { |
17499 | | F32 => { |
17500 | 0 | let v3 = constructor_x64_andps(ctx, arg1, arg2); |
17501 | 0 | // Rule at src/isa/x64/lower.isle line 225. |
17502 | 0 | return v3; |
17503 | | } |
17504 | | F64 => { |
17505 | 0 | let v4 = constructor_x64_andpd(ctx, arg1, arg2); |
17506 | 0 | // Rule at src/isa/x64/lower.isle line 226. |
17507 | 0 | return v4; |
17508 | | } |
17509 | | F32X4 => { |
17510 | 0 | let v3 = constructor_x64_andps(ctx, arg1, arg2); |
17511 | 0 | // Rule at src/isa/x64/lower.isle line 223. |
17512 | 0 | return v3; |
17513 | | } |
17514 | | F64X2 => { |
17515 | 0 | let v4 = constructor_x64_andpd(ctx, arg1, arg2); |
17516 | 0 | // Rule at src/isa/x64/lower.isle line 224. |
17517 | 0 | return v4; |
17518 | | } |
17519 | 0 | _ => {} |
17520 | 0 | } |
17521 | 0 | let v5 = C::multi_lane(ctx, arg0); |
17522 | 0 | if let Some(v6) = v5 { |
17523 | 0 | let v9 = constructor_x64_pand(ctx, arg1, arg2); |
17524 | 0 | // Rule at src/isa/x64/lower.isle line 227. |
17525 | 0 | return v9; |
17526 | 0 | } |
17527 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "sse_and", "src/isa/x64/lower.isle line 222") |
17528 | 0 | } |
17529 | | |
17530 | | // Generated as internal constructor for term sse_and_not. |
17531 | 0 | pub fn constructor_sse_and_not<C: Context>( |
17532 | 0 | ctx: &mut C, |
17533 | 0 | arg0: Type, |
17534 | 0 | arg1: Xmm, |
17535 | 0 | arg2: &XmmMem, |
17536 | 0 | ) -> Xmm { |
17537 | 0 | match arg0 { |
17538 | | F32X4 => { |
17539 | 0 | let v3 = constructor_x64_andnps(ctx, arg1, arg2); |
17540 | 0 | // Rule at src/isa/x64/lower.isle line 250. |
17541 | 0 | return v3; |
17542 | | } |
17543 | | F64X2 => { |
17544 | 0 | let v4 = constructor_x64_andnpd(ctx, arg1, arg2); |
17545 | 0 | // Rule at src/isa/x64/lower.isle line 251. |
17546 | 0 | return v4; |
17547 | | } |
17548 | 0 | _ => {} |
17549 | 0 | } |
17550 | 0 | let v5 = C::multi_lane(ctx, arg0); |
17551 | 0 | if let Some(v6) = v5 { |
17552 | 0 | let v9 = constructor_x64_pandn(ctx, arg1, arg2); |
17553 | 0 | // Rule at src/isa/x64/lower.isle line 252. |
17554 | 0 | return v9; |
17555 | 0 | } |
17556 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "sse_and_not", "src/isa/x64/lower.isle line 249") |
17557 | 0 | } |
17558 | | |
17559 | | // Generated as internal constructor for term sse_or. |
17560 | 0 | pub fn constructor_sse_or<C: Context>( |
17561 | 0 | ctx: &mut C, |
17562 | 0 | arg0: Type, |
17563 | 0 | arg1: Xmm, |
17564 | 0 | arg2: &XmmMem, |
17565 | 0 | ) -> Xmm { |
17566 | 0 | match arg0 { |
17567 | | F32 => { |
17568 | 0 | let v3 = constructor_x64_orps(ctx, arg1, arg2); |
17569 | 0 | // Rule at src/isa/x64/lower.isle line 305. |
17570 | 0 | return v3; |
17571 | | } |
17572 | | F64 => { |
17573 | 0 | let v4 = constructor_x64_orpd(ctx, arg1, arg2); |
17574 | 0 | // Rule at src/isa/x64/lower.isle line 306. |
17575 | 0 | return v4; |
17576 | | } |
17577 | | F32X4 => { |
17578 | 0 | let v3 = constructor_x64_orps(ctx, arg1, arg2); |
17579 | 0 | // Rule at src/isa/x64/lower.isle line 303. |
17580 | 0 | return v3; |
17581 | | } |
17582 | | F64X2 => { |
17583 | 0 | let v4 = constructor_x64_orpd(ctx, arg1, arg2); |
17584 | 0 | // Rule at src/isa/x64/lower.isle line 304. |
17585 | 0 | return v4; |
17586 | | } |
17587 | 0 | _ => {} |
17588 | 0 | } |
17589 | 0 | let v5 = C::multi_lane(ctx, arg0); |
17590 | 0 | if let Some(v6) = v5 { |
17591 | 0 | let v9 = constructor_x64_por(ctx, arg1, arg2); |
17592 | 0 | // Rule at src/isa/x64/lower.isle line 307. |
17593 | 0 | return v9; |
17594 | 0 | } |
17595 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "sse_or", "src/isa/x64/lower.isle line 302") |
17596 | 0 | } |
17597 | | |
17598 | | // Generated as internal constructor for term or_i128. |
17599 | 0 | pub fn constructor_or_i128<C: Context>( |
17600 | 0 | ctx: &mut C, |
17601 | 0 | arg0: ValueRegs, |
17602 | 0 | arg1: ValueRegs, |
17603 | 0 | ) -> ValueRegs { |
17604 | 0 | let v3 = constructor_value_regs_get_gpr(ctx, arg0, 0x0); |
17605 | 0 | let v5 = constructor_value_regs_get_gpr(ctx, arg0, 0x1); |
17606 | 0 | let v6 = constructor_value_regs_get_gpr(ctx, arg1, 0x0); |
17607 | 0 | let v7 = constructor_value_regs_get_gpr(ctx, arg1, 0x1); |
17608 | 0 | let v9 = &C::gpr_to_gpr_mem_imm(ctx, v6); |
17609 | 0 | let v10 = constructor_x64_or(ctx, I64, v3, v9); |
17610 | 0 | let v11 = &C::gpr_to_gpr_mem_imm(ctx, v7); |
17611 | 0 | let v12 = constructor_x64_or(ctx, I64, v5, v11); |
17612 | 0 | let v13 = constructor_value_gprs(ctx, v10, v12); |
17613 | 0 | // Rule at src/isa/x64/lower.isle line 316. |
17614 | 0 | return v13; |
17615 | 0 | } |
17616 | | |
17617 | | // Generated as internal constructor for term shl_i128. |
17618 | 0 | pub fn constructor_shl_i128<C: Context>( |
17619 | 0 | ctx: &mut C, |
17620 | 0 | arg0: ValueRegs, |
17621 | 0 | arg1: Gpr, |
17622 | 0 | ) -> ValueRegs { |
17623 | 0 | let v3 = constructor_value_regs_get_gpr(ctx, arg0, 0x0); |
17624 | 0 | let v5 = constructor_value_regs_get_gpr(ctx, arg0, 0x1); |
17625 | 0 | let v7 = &C::gpr_to_imm8_gpr(ctx, arg1); |
17626 | 0 | let v8 = constructor_x64_shl(ctx, I64, v3, v7); |
17627 | 0 | let v9 = &C::gpr_to_imm8_gpr(ctx, arg1); |
17628 | 0 | let v10 = constructor_x64_shl(ctx, I64, v5, v9); |
17629 | 0 | let v12 = constructor_imm(ctx, I64, 0x40); |
17630 | 0 | let v13 = C::gpr_new(ctx, v12); |
17631 | 0 | let v14 = &C::gpr_to_gpr_mem_imm(ctx, arg1); |
17632 | 0 | let v15 = constructor_x64_sub(ctx, I64, v13, v14); |
17633 | 0 | let v16 = &C::gpr_to_imm8_gpr(ctx, v15); |
17634 | 0 | let v17 = constructor_x64_shr(ctx, I64, v3, v16); |
17635 | 0 | let v19 = constructor_imm(ctx, I64, 0x0); |
17636 | 0 | let v20 = C::gpr_new(ctx, v19); |
17637 | 0 | let v23 = RegMemImm::Imm { |
17638 | 0 | simm32: 0x7F, |
17639 | 0 | }; |
17640 | 0 | let v24 = &C::gpr_mem_imm_new(ctx, &v23); |
17641 | 0 | let v25 = &constructor_x64_test(ctx, &OperandSize::Size64, v24, arg1); |
17642 | 0 | let v27 = &C::gpr_to_gpr_mem(ctx, v20); |
17643 | 0 | let v28 = &constructor_cmove(ctx, I64, &CC::Z, v27, v17); |
17644 | 0 | let v29 = constructor_with_flags_reg(ctx, v25, v28); |
17645 | 0 | let v30 = C::gpr_new(ctx, v29); |
17646 | 0 | let v31 = &C::gpr_to_gpr_mem_imm(ctx, v10); |
17647 | 0 | let v32 = constructor_x64_or(ctx, I64, v30, v31); |
17648 | 0 | let v34 = RegMemImm::Imm { |
17649 | 0 | simm32: 0x40, |
17650 | 0 | }; |
17651 | 0 | let v35 = &C::gpr_mem_imm_new(ctx, &v34); |
17652 | 0 | let v36 = &constructor_x64_test(ctx, &OperandSize::Size64, v35, arg1); |
17653 | 0 | let v37 = &C::gpr_to_gpr_mem(ctx, v8); |
17654 | 0 | let v38 = &constructor_cmove(ctx, I64, &CC::Z, v37, v20); |
17655 | 0 | let v39 = &C::gpr_to_gpr_mem(ctx, v32); |
17656 | 0 | let v40 = &constructor_cmove(ctx, I64, &CC::Z, v39, v8); |
17657 | 0 | let v41 = &constructor_consumes_flags_concat(ctx, v38, v40); |
17658 | 0 | let v42 = constructor_with_flags(ctx, v36, v41); |
17659 | 0 | // Rule at src/isa/x64/lower.isle line 379. |
17660 | 0 | return v42; |
17661 | 0 | } |
17662 | | |
17663 | | // Generated as internal constructor for term ishl_i8x16_mask. |
17664 | 0 | pub fn constructor_ishl_i8x16_mask<C: Context>( |
17665 | 0 | ctx: &mut C, |
17666 | 0 | arg0: &RegMemImm, |
17667 | 0 | ) -> SyntheticAmode { |
17668 | 0 | match arg0 { |
17669 | | &RegMemImm::Reg { |
17670 | 0 | reg: v3, |
17671 | 0 | } => { |
17672 | 0 | let v4 = &C::ishl_i8x16_mask_table(ctx); |
17673 | 0 | let v6 = constructor_x64_lea(ctx, I64, v4); |
17674 | 0 | let v7 = C::gpr_new(ctx, v3); |
17675 | 0 | let v9 = &C::imm8_to_imm8_gpr(ctx, 0x4); |
17676 | 0 | let v10 = constructor_x64_shl(ctx, I64, v7, v9); |
17677 | 0 | let v13 = C::mem_flags_trusted(ctx); |
17678 | 0 | let v14 = Amode::ImmRegRegShift { |
17679 | 0 | simm32: 0x0, |
17680 | 0 | base: v6, |
17681 | 0 | index: v10, |
17682 | 0 | shift: 0x0, |
17683 | 0 | flags: v13, |
17684 | 0 | }; |
17685 | 0 | let v15 = &C::amode_to_synthetic_amode(ctx, &v14); |
17686 | 0 | // Rule at src/isa/x64/lower.isle line 453. |
17687 | 0 | return v15.clone(); |
17688 | | } |
17689 | | &RegMemImm::Mem { |
17690 | 0 | addr: ref v16, |
17691 | 0 | } => { |
17692 | 0 | let v18 = constructor_x64_load(ctx, I64, v16, &ExtKind::None); |
17693 | 0 | let v19 = RegMemImm::Reg { |
17694 | 0 | reg: v18, |
17695 | 0 | }; |
17696 | 0 | let v20 = &constructor_ishl_i8x16_mask(ctx, &v19); |
17697 | 0 | // Rule at src/isa/x64/lower.isle line 464. |
17698 | 0 | return v20.clone(); |
17699 | | } |
17700 | | &RegMemImm::Imm { |
17701 | 0 | simm32: v1, |
17702 | 0 | } => { |
17703 | 0 | let v2 = &C::ishl_i8x16_mask_for_const(ctx, v1); |
17704 | 0 | // Rule at src/isa/x64/lower.isle line 444. |
17705 | 0 | return v2.clone(); |
17706 | | } |
17707 | 0 | _ => {} |
17708 | 0 | } |
17709 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "ishl_i8x16_mask", "src/isa/x64/lower.isle line 438") |
17710 | 0 | } |
17711 | | |
17712 | | // Generated as internal constructor for term shr_i128. |
17713 | 0 | pub fn constructor_shr_i128<C: Context>( |
17714 | 0 | ctx: &mut C, |
17715 | 0 | arg0: ValueRegs, |
17716 | 0 | arg1: Gpr, |
17717 | 0 | ) -> ValueRegs { |
17718 | 0 | let v3 = constructor_value_regs_get_gpr(ctx, arg0, 0x0); |
17719 | 0 | let v5 = constructor_value_regs_get_gpr(ctx, arg0, 0x1); |
17720 | 0 | let v7 = &C::gpr_to_imm8_gpr(ctx, arg1); |
17721 | 0 | let v8 = constructor_x64_shr(ctx, I64, v3, v7); |
17722 | 0 | let v9 = &C::gpr_to_imm8_gpr(ctx, arg1); |
17723 | 0 | let v10 = constructor_x64_shr(ctx, I64, v5, v9); |
17724 | 0 | let v12 = constructor_imm(ctx, I64, 0x40); |
17725 | 0 | let v13 = C::gpr_new(ctx, v12); |
17726 | 0 | let v14 = &C::gpr_to_gpr_mem_imm(ctx, arg1); |
17727 | 0 | let v15 = constructor_x64_sub(ctx, I64, v13, v14); |
17728 | 0 | let v16 = &C::gpr_to_imm8_gpr(ctx, v15); |
17729 | 0 | let v17 = constructor_x64_shl(ctx, I64, v5, v16); |
17730 | 0 | let v19 = constructor_imm(ctx, I64, 0x0); |
17731 | 0 | let v20 = C::gpr_new(ctx, v19); |
17732 | 0 | let v23 = RegMemImm::Imm { |
17733 | 0 | simm32: 0x7F, |
17734 | 0 | }; |
17735 | 0 | let v24 = &C::gpr_mem_imm_new(ctx, &v23); |
17736 | 0 | let v25 = &constructor_x64_test(ctx, &OperandSize::Size64, v24, arg1); |
17737 | 0 | let v27 = &C::gpr_to_gpr_mem(ctx, v20); |
17738 | 0 | let v28 = &constructor_cmove(ctx, I64, &CC::Z, v27, v17); |
17739 | 0 | let v29 = constructor_with_flags_reg(ctx, v25, v28); |
17740 | 0 | let v30 = C::gpr_new(ctx, v29); |
17741 | 0 | let v31 = &C::gpr_to_gpr_mem_imm(ctx, v8); |
17742 | 0 | let v32 = constructor_x64_or(ctx, I64, v30, v31); |
17743 | 0 | let v34 = RegMemImm::Imm { |
17744 | 0 | simm32: 0x40, |
17745 | 0 | }; |
17746 | 0 | let v35 = &C::gpr_mem_imm_new(ctx, &v34); |
17747 | 0 | let v36 = &constructor_x64_test(ctx, &OperandSize::Size64, v35, arg1); |
17748 | 0 | let v37 = &C::gpr_to_gpr_mem(ctx, v32); |
17749 | 0 | let v38 = &constructor_cmove(ctx, I64, &CC::Z, v37, v10); |
17750 | 0 | let v39 = &C::gpr_to_gpr_mem(ctx, v10); |
17751 | 0 | let v40 = &constructor_cmove(ctx, I64, &CC::Z, v39, v20); |
17752 | 0 | let v41 = &constructor_consumes_flags_concat(ctx, v38, v40); |
17753 | 0 | let v42 = constructor_with_flags(ctx, v36, v41); |
17754 | 0 | // Rule at src/isa/x64/lower.isle line 489. |
17755 | 0 | return v42; |
17756 | 0 | } |
17757 | | |
17758 | | // Generated as internal constructor for term ushr_i8x16_mask. |
17759 | 0 | pub fn constructor_ushr_i8x16_mask<C: Context>( |
17760 | 0 | ctx: &mut C, |
17761 | 0 | arg0: &RegMemImm, |
17762 | 0 | ) -> SyntheticAmode { |
17763 | 0 | match arg0 { |
17764 | | &RegMemImm::Reg { |
17765 | 0 | reg: v3, |
17766 | 0 | } => { |
17767 | 0 | let v4 = &C::ushr_i8x16_mask_table(ctx); |
17768 | 0 | let v6 = constructor_x64_lea(ctx, I64, v4); |
17769 | 0 | let v7 = C::gpr_new(ctx, v3); |
17770 | 0 | let v9 = &C::imm8_to_imm8_gpr(ctx, 0x4); |
17771 | 0 | let v10 = constructor_x64_shl(ctx, I64, v7, v9); |
17772 | 0 | let v13 = C::mem_flags_trusted(ctx); |
17773 | 0 | let v14 = Amode::ImmRegRegShift { |
17774 | 0 | simm32: 0x0, |
17775 | 0 | base: v6, |
17776 | 0 | index: v10, |
17777 | 0 | shift: 0x0, |
17778 | 0 | flags: v13, |
17779 | 0 | }; |
17780 | 0 | let v15 = &C::amode_to_synthetic_amode(ctx, &v14); |
17781 | 0 | // Rule at src/isa/x64/lower.isle line 558. |
17782 | 0 | return v15.clone(); |
17783 | | } |
17784 | | &RegMemImm::Mem { |
17785 | 0 | addr: ref v16, |
17786 | 0 | } => { |
17787 | 0 | let v18 = constructor_x64_load(ctx, I64, v16, &ExtKind::None); |
17788 | 0 | let v19 = RegMemImm::Reg { |
17789 | 0 | reg: v18, |
17790 | 0 | }; |
17791 | 0 | let v20 = &constructor_ushr_i8x16_mask(ctx, &v19); |
17792 | 0 | // Rule at src/isa/x64/lower.isle line 570. |
17793 | 0 | return v20.clone(); |
17794 | | } |
17795 | | &RegMemImm::Imm { |
17796 | 0 | simm32: v1, |
17797 | 0 | } => { |
17798 | 0 | let v2 = &C::ushr_i8x16_mask_for_const(ctx, v1); |
17799 | 0 | // Rule at src/isa/x64/lower.isle line 549. |
17800 | 0 | return v2.clone(); |
17801 | | } |
17802 | 0 | _ => {} |
17803 | 0 | } |
17804 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "ushr_i8x16_mask", "src/isa/x64/lower.isle line 543") |
17805 | 0 | } |
17806 | | |
17807 | | // Generated as internal constructor for term mask_xmm_shift. |
17808 | 0 | pub fn constructor_mask_xmm_shift<C: Context>( |
17809 | 0 | ctx: &mut C, |
17810 | 0 | arg0: Type, |
17811 | 0 | arg1: Value, |
17812 | 0 | ) -> RegMemImm { |
17813 | 0 | let v10 = C::def_inst(ctx, arg1); |
17814 | 0 | if let Some(v11) = v10 { |
17815 | 0 | let v12 = &C::inst_data(ctx, v11); |
17816 | | if let &InstructionData::UnaryImm { |
17817 | 0 | opcode: ref v13, |
17818 | 0 | imm: v14, |
17819 | 0 | } = v12 { |
17820 | 0 | if let &Opcode::Iconst = v13 { |
17821 | 0 | let v15 = C::shift_amount_masked(ctx, arg0, v14); |
17822 | 0 | let v16 = RegMemImm::Imm { |
17823 | 0 | simm32: v15, |
17824 | 0 | }; |
17825 | 0 | // Rule at src/isa/x64/lower.isle line 587. |
17826 | 0 | return v16; |
17827 | 0 | } |
17828 | 0 | } |
17829 | 0 | } |
17830 | 0 | let v3 = constructor_put_in_gpr(ctx, arg1); |
17831 | 0 | let v4 = C::shift_mask(ctx, arg0); |
17832 | 0 | let v5 = RegMemImm::Imm { |
17833 | 0 | simm32: v4, |
17834 | 0 | }; |
17835 | 0 | let v6 = &C::gpr_mem_imm_new(ctx, &v5); |
17836 | 0 | let v7 = constructor_x64_and(ctx, I64, v3, v6); |
17837 | 0 | let v8 = C::gpr_to_reg(ctx, v7); |
17838 | 0 | let v9 = &C::reg_to_reg_mem_imm(ctx, v8); |
17839 | 0 | // Rule at src/isa/x64/lower.isle line 585. |
17840 | 0 | return v9.clone(); |
17841 | 0 | } |
17842 | | |
17843 | | // Generated as internal constructor for term sar_i128. |
17844 | 0 | pub fn constructor_sar_i128<C: Context>( |
17845 | 0 | ctx: &mut C, |
17846 | 0 | arg0: ValueRegs, |
17847 | 0 | arg1: Gpr, |
17848 | 0 | ) -> ValueRegs { |
17849 | 0 | let v3 = constructor_value_regs_get_gpr(ctx, arg0, 0x0); |
17850 | 0 | let v5 = constructor_value_regs_get_gpr(ctx, arg0, 0x1); |
17851 | 0 | let v7 = &C::gpr_to_imm8_gpr(ctx, arg1); |
17852 | 0 | let v8 = constructor_x64_shr(ctx, I64, v3, v7); |
17853 | 0 | let v9 = &C::gpr_to_imm8_gpr(ctx, arg1); |
17854 | 0 | let v10 = constructor_x64_sar(ctx, I64, v5, v9); |
17855 | 0 | let v12 = constructor_imm(ctx, I64, 0x40); |
17856 | 0 | let v13 = C::gpr_new(ctx, v12); |
17857 | 0 | let v14 = &C::gpr_to_gpr_mem_imm(ctx, arg1); |
17858 | 0 | let v15 = constructor_x64_sub(ctx, I64, v13, v14); |
17859 | 0 | let v16 = &C::gpr_to_imm8_gpr(ctx, v15); |
17860 | 0 | let v17 = constructor_x64_shl(ctx, I64, v5, v16); |
17861 | 0 | let v20 = RegMemImm::Imm { |
17862 | 0 | simm32: 0x7F, |
17863 | 0 | }; |
17864 | 0 | let v21 = &C::gpr_mem_imm_new(ctx, &v20); |
17865 | 0 | let v22 = &constructor_x64_test(ctx, &OperandSize::Size64, v21, arg1); |
17866 | 0 | let v25 = constructor_imm(ctx, I64, 0x0); |
17867 | 0 | let v26 = &C::reg_to_gpr_mem(ctx, v25); |
17868 | 0 | let v27 = &constructor_cmove(ctx, I64, &CC::Z, v26, v17); |
17869 | 0 | let v28 = constructor_with_flags_reg(ctx, v22, v27); |
17870 | 0 | let v29 = C::gpr_new(ctx, v28); |
17871 | 0 | let v30 = &C::gpr_to_gpr_mem_imm(ctx, v29); |
17872 | 0 | let v31 = constructor_x64_or(ctx, I64, v8, v30); |
17873 | 0 | let v33 = &C::imm8_to_imm8_gpr(ctx, 0x3F); |
17874 | 0 | let v34 = constructor_x64_sar(ctx, I64, v5, v33); |
17875 | 0 | let v36 = RegMemImm::Imm { |
17876 | 0 | simm32: 0x40, |
17877 | 0 | }; |
17878 | 0 | let v37 = &C::gpr_mem_imm_new(ctx, &v36); |
17879 | 0 | let v38 = &constructor_x64_test(ctx, &OperandSize::Size64, v37, arg1); |
17880 | 0 | let v39 = &C::gpr_to_gpr_mem(ctx, v31); |
17881 | 0 | let v40 = &constructor_cmove(ctx, I64, &CC::Z, v39, v10); |
17882 | 0 | let v41 = &C::gpr_to_gpr_mem(ctx, v10); |
17883 | 0 | let v42 = &constructor_cmove(ctx, I64, &CC::Z, v41, v34); |
17884 | 0 | let v43 = &constructor_consumes_flags_concat(ctx, v40, v42); |
17885 | 0 | let v44 = constructor_with_flags(ctx, v38, v43); |
17886 | 0 | // Rule at src/isa/x64/lower.isle line 601. |
17887 | 0 | return v44; |
17888 | 0 | } |
17889 | | |
17890 | | // Generated as internal constructor for term sshr_i8x16_bigger_shift. |
17891 | 0 | pub fn constructor_sshr_i8x16_bigger_shift<C: Context>( |
17892 | 0 | ctx: &mut C, |
17893 | 0 | arg0: Type, |
17894 | 0 | arg1: &RegMemImm, |
17895 | 0 | ) -> XmmMemImm { |
17896 | 0 | match arg1 { |
17897 | | &RegMemImm::Reg { |
17898 | 0 | reg: v7, |
17899 | 0 | } => { |
17900 | 0 | let v8 = C::gpr_new(ctx, v7); |
17901 | 0 | let v9 = RegMemImm::Imm { |
17902 | 0 | simm32: 0x8, |
17903 | 0 | }; |
17904 | 0 | let v10 = &C::gpr_mem_imm_new(ctx, &v9); |
17905 | 0 | let v11 = constructor_x64_add(ctx, arg0, v8, v10); |
17906 | 0 | let v12 = C::gpr_to_reg(ctx, v11); |
17907 | 0 | let v13 = RegMemImm::Reg { |
17908 | 0 | reg: v12, |
17909 | 0 | }; |
17910 | 0 | let v14 = &constructor_mov_rmi_to_xmm(ctx, &v13); |
17911 | 0 | // Rule at src/isa/x64/lower.isle line 669. |
17912 | 0 | return v14.clone(); |
17913 | | } |
17914 | | &RegMemImm::Mem { |
17915 | 0 | addr: ref v15, |
17916 | 0 | } => { |
17917 | 0 | let v17 = constructor_imm(ctx, arg0, 0x8); |
17918 | 0 | let v18 = C::gpr_new(ctx, v17); |
17919 | 0 | let v19 = &C::gpr_mem_imm_new(ctx, arg1); |
17920 | 0 | let v20 = constructor_x64_add(ctx, arg0, v18, v19); |
17921 | 0 | let v21 = C::gpr_to_reg(ctx, v20); |
17922 | 0 | let v22 = RegMemImm::Reg { |
17923 | 0 | reg: v21, |
17924 | 0 | }; |
17925 | 0 | let v23 = &constructor_mov_rmi_to_xmm(ctx, &v22); |
17926 | 0 | // Rule at src/isa/x64/lower.isle line 673. |
17927 | 0 | return v23.clone(); |
17928 | | } |
17929 | | &RegMemImm::Imm { |
17930 | 0 | simm32: v2, |
17931 | 0 | } => { |
17932 | 0 | let v4 = C::u32_add(ctx, v2, 0x8); |
17933 | 0 | let v5 = RegMemImm::Imm { |
17934 | 0 | simm32: v4, |
17935 | 0 | }; |
17936 | 0 | let v6 = &C::xmm_mem_imm_new(ctx, &v5); |
17937 | 0 | // Rule at src/isa/x64/lower.isle line 667. |
17938 | 0 | return v6.clone(); |
17939 | | } |
17940 | 0 | _ => {} |
17941 | 0 | } |
17942 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "sshr_i8x16_bigger_shift", "src/isa/x64/lower.isle line 666") |
17943 | 0 | } |
17944 | | |
17945 | | // Generated as internal constructor for term lower_bmask. |
17946 | 0 | pub fn constructor_lower_bmask<C: Context>( |
17947 | 0 | ctx: &mut C, |
17948 | 0 | arg0: Type, |
17949 | 0 | arg1: Type, |
17950 | 0 | arg2: ValueRegs, |
17951 | 0 | ) -> ValueRegs { |
17952 | 0 | if arg0 == I128 { |
17953 | 0 | let v23 = constructor_lower_bmask(ctx, I64, arg1, arg2); |
17954 | 0 | let v24 = constructor_value_regs_get_gpr(ctx, v23, 0x0); |
17955 | 0 | let v25 = C::gpr_to_reg(ctx, v24); |
17956 | 0 | let v26 = C::gpr_to_reg(ctx, v24); |
17957 | 0 | let v27 = C::value_regs(ctx, v25, v26); |
17958 | 0 | // Rule at src/isa/x64/lower.isle line 1146. |
17959 | 0 | return v27; |
17960 | 0 | } |
17961 | 0 | let v1 = C::fits_in_64(ctx, arg0); |
17962 | 0 | if let Some(v2) = v1 { |
17963 | 0 | if arg1 == I128 { |
17964 | 0 | let v8 = constructor_value_regs_get_gpr(ctx, arg2, 0x0); |
17965 | 0 | let v16 = constructor_value_regs_get_gpr(ctx, arg2, 0x1); |
17966 | 0 | let v18 = &C::gpr_to_gpr_mem_imm(ctx, v16); |
17967 | 0 | let v19 = constructor_x64_or(ctx, I64, v8, v18); |
17968 | 0 | let v20 = C::gpr_to_reg(ctx, v19); |
17969 | 0 | let v21 = C::value_reg(ctx, v20); |
17970 | 0 | let v22 = constructor_lower_bmask(ctx, v2, I64, v21); |
17971 | 0 | // Rule at src/isa/x64/lower.isle line 1138. |
17972 | 0 | return v22; |
17973 | 0 | } |
17974 | 0 | let v4 = C::fits_in_64(ctx, arg1); |
17975 | 0 | if let Some(v5) = v4 { |
17976 | 0 | let v8 = constructor_value_regs_get_gpr(ctx, arg2, 0x0); |
17977 | 0 | let v9 = &constructor_x64_neg_paired(ctx, v5, v8); |
17978 | 0 | let v10 = &C::gpr_to_gpr_mem_imm(ctx, v8); |
17979 | 0 | let v11 = &constructor_x64_sbb_paired(ctx, v2, v8, v10); |
17980 | 0 | let v12 = constructor_with_flags(ctx, v9, v11); |
17981 | 0 | let v14 = C::value_regs_get(ctx, v12, 0x1); |
17982 | 0 | let v15 = C::value_reg(ctx, v14); |
17983 | 0 | // Rule at src/isa/x64/lower.isle line 1127. |
17984 | 0 | return v15; |
17985 | 0 | } |
17986 | 0 | } |
17987 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "lower_bmask", "src/isa/x64/lower.isle line 1115") |
17988 | 0 | } |
17989 | | |
17990 | | // Generated as internal constructor for term i128_not. |
17991 | 0 | pub fn constructor_i128_not<C: Context>( |
17992 | 0 | ctx: &mut C, |
17993 | 0 | arg0: Value, |
17994 | 0 | ) -> ValueRegs { |
17995 | 0 | let v1 = C::put_in_regs(ctx, arg0); |
17996 | 0 | let v3 = constructor_value_regs_get_gpr(ctx, v1, 0x0); |
17997 | 0 | let v5 = constructor_value_regs_get_gpr(ctx, v1, 0x1); |
17998 | 0 | let v7 = constructor_x64_not(ctx, I64, v3); |
17999 | 0 | let v8 = constructor_x64_not(ctx, I64, v5); |
18000 | 0 | let v9 = constructor_value_gprs(ctx, v7, v8); |
18001 | 0 | // Rule at src/isa/x64/lower.isle line 1169. |
18002 | 0 | return v9; |
18003 | 0 | } |
18004 | | |
18005 | | // Generated as internal constructor for term all_ones_or_all_zeros. |
18006 | 0 | pub fn constructor_all_ones_or_all_zeros<C: Context>( |
18007 | 0 | ctx: &mut C, |
18008 | 0 | arg0: Value, |
18009 | 0 | ) -> Option<bool> { |
18010 | 0 | let v1 = C::def_inst(ctx, arg0); |
18011 | 0 | if let Some(v2) = v1 { |
18012 | 0 | let v3 = &C::inst_data(ctx, v2); |
18013 | 0 | match v3 { |
18014 | | &InstructionData::FloatCompare { |
18015 | 0 | opcode: ref v16, |
18016 | 0 | args: ref v17, |
18017 | 0 | cond: ref v18, |
18018 | 0 | } => { |
18019 | 0 | if let &Opcode::Fcmp = v16 { |
18020 | 0 | let v10 = C::value_type(ctx, arg0); |
18021 | 0 | let v11 = C::multi_lane(ctx, v10); |
18022 | 0 | if let Some(v12) = v11 { |
18023 | | // Rule at src/isa/x64/lower.isle line 1217. |
18024 | 0 | return Some(true); |
18025 | 0 | } |
18026 | 0 | } |
18027 | | } |
18028 | | &InstructionData::IntCompare { |
18029 | 0 | opcode: ref v4, |
18030 | 0 | args: ref v5, |
18031 | 0 | cond: ref v6, |
18032 | 0 | } => { |
18033 | 0 | if let &Opcode::Icmp = v4 { |
18034 | 0 | let v10 = C::value_type(ctx, arg0); |
18035 | 0 | let v11 = C::multi_lane(ctx, v10); |
18036 | 0 | if let Some(v12) = v11 { |
18037 | | // Rule at src/isa/x64/lower.isle line 1216. |
18038 | 0 | return Some(true); |
18039 | 0 | } |
18040 | 0 | } |
18041 | | } |
18042 | | &InstructionData::UnaryConst { |
18043 | 0 | opcode: ref v22, |
18044 | 0 | constant_handle: v23, |
18045 | 0 | } => { |
18046 | 0 | if let &Opcode::Vconst = v22 { |
18047 | 0 | let v24 = C::vconst_all_ones_or_all_zeros(ctx, v23); |
18048 | 0 | if let Some(v25) = v24 { |
18049 | | // Rule at src/isa/x64/lower.isle line 1218. |
18050 | 0 | return Some(true); |
18051 | 0 | } |
18052 | 0 | } |
18053 | | } |
18054 | 0 | _ => {} |
18055 | | } |
18056 | 0 | } |
18057 | 0 | None |
18058 | 0 | } |
18059 | | |
18060 | | // Generated as internal constructor for term vec_insert_lane. |
18061 | 0 | pub fn constructor_vec_insert_lane<C: Context>( |
18062 | 0 | ctx: &mut C, |
18063 | 0 | arg0: Type, |
18064 | 0 | arg1: Xmm, |
18065 | 0 | arg2: &RegMem, |
18066 | 0 | arg3: u8, |
18067 | 0 | ) -> Xmm { |
18068 | 0 | match arg0 { |
18069 | | I8X16 => { |
18070 | 0 | let v4 = &C::reg_mem_to_gpr_mem(ctx, arg2); |
18071 | 0 | let v5 = constructor_x64_pinsrb(ctx, arg1, v4, arg3); |
18072 | 0 | // Rule at src/isa/x64/lower.isle line 1250. |
18073 | 0 | return v5; |
18074 | | } |
18075 | | I16X8 => { |
18076 | 0 | let v4 = &C::reg_mem_to_gpr_mem(ctx, arg2); |
18077 | 0 | let v6 = constructor_x64_pinsrw(ctx, arg1, v4, arg3); |
18078 | 0 | // Rule at src/isa/x64/lower.isle line 1254. |
18079 | 0 | return v6; |
18080 | | } |
18081 | | I32X4 => { |
18082 | 0 | let v4 = &C::reg_mem_to_gpr_mem(ctx, arg2); |
18083 | 0 | let v7 = constructor_x64_pinsrd(ctx, arg1, v4, arg3); |
18084 | 0 | // Rule at src/isa/x64/lower.isle line 1258. |
18085 | 0 | return v7; |
18086 | | } |
18087 | | I64X2 => { |
18088 | 0 | let v4 = &C::reg_mem_to_gpr_mem(ctx, arg2); |
18089 | 0 | let v8 = constructor_x64_pinsrq(ctx, arg1, v4, arg3); |
18090 | 0 | // Rule at src/isa/x64/lower.isle line 1262. |
18091 | 0 | return v8; |
18092 | | } |
18093 | | F32X4 => { |
18094 | 0 | let v9 = &C::reg_mem_to_xmm_mem(ctx, arg2); |
18095 | 0 | let v10 = C::sse_insertps_lane_imm(ctx, arg3); |
18096 | 0 | let v11 = constructor_x64_insertps(ctx, arg1, v9, v10); |
18097 | 0 | // Rule at src/isa/x64/lower.isle line 1266. |
18098 | 0 | return v11; |
18099 | | } |
18100 | | F64X2 => { |
18101 | 0 | match arg3 { |
18102 | | 0x0 => { |
18103 | 0 | match arg2 { |
18104 | | &RegMem::Reg { |
18105 | 0 | reg: v12, |
18106 | 0 | } => { |
18107 | 0 | let v13 = C::xmm_new(ctx, v12); |
18108 | 0 | let v14 = constructor_x64_movsd_regmove(ctx, arg1, v13); |
18109 | 0 | // Rule at src/isa/x64/lower.isle line 1278. |
18110 | 0 | return v14; |
18111 | | } |
18112 | | &RegMem::Mem { |
18113 | 0 | addr: ref v15, |
18114 | 0 | } => { |
18115 | 0 | let v16 = constructor_x64_movsd_load(ctx, v15); |
18116 | 0 | let v17 = constructor_x64_movsd_regmove(ctx, arg1, v16); |
18117 | 0 | // Rule at src/isa/x64/lower.isle line 1280. |
18118 | 0 | return v17; |
18119 | | } |
18120 | 0 | _ => {} |
18121 | | } |
18122 | | } |
18123 | | 0x1 => { |
18124 | 0 | let v9 = &C::reg_mem_to_xmm_mem(ctx, arg2); |
18125 | 0 | let v18 = constructor_x64_movlhps(ctx, arg1, v9); |
18126 | 0 | // Rule at src/isa/x64/lower.isle line 1288. |
18127 | 0 | return v18; |
18128 | | } |
18129 | 0 | _ => {} |
18130 | | } |
18131 | | } |
18132 | 0 | _ => {} |
18133 | | } |
18134 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "vec_insert_lane", "src/isa/x64/lower.isle line 1247") |
18135 | 0 | } |
18136 | | |
18137 | | // Generated as internal constructor for term cmp_and_choose. |
18138 | 1.56k | pub fn constructor_cmp_and_choose<C: Context>( |
18139 | 1.56k | ctx: &mut C, |
18140 | 1.56k | arg0: Type, |
18141 | 1.56k | arg1: &CC, |
18142 | 1.56k | arg2: Value, |
18143 | 1.56k | arg3: Value, |
18144 | 1.56k | ) -> ValueRegs { |
18145 | 1.56k | let v1 = C::fits_in_64(ctx, arg0); |
18146 | 1.56k | if let Some(v2) = v1 { |
18147 | 1.56k | let v6 = &C::raw_operand_size_of_type(ctx, v2); |
18148 | 1.56k | let v7 = C::put_in_reg(ctx, arg2); |
18149 | 1.56k | let v8 = C::put_in_reg(ctx, arg3); |
18150 | 1.56k | let v9 = &constructor_reg_to_gpr_mem_imm(ctx, v7); |
18151 | 1.56k | let v10 = C::gpr_new(ctx, v8); |
18152 | 1.56k | let v11 = &constructor_x64_cmp(ctx, v6, v9, v10); |
18153 | 1.56k | let v12 = &C::reg_to_gpr_mem(ctx, v8); |
18154 | 1.56k | let v13 = C::gpr_new(ctx, v7); |
18155 | 1.56k | let v14 = &constructor_cmove(ctx, v2, arg1, v12, v13); |
18156 | 1.56k | let v15 = constructor_with_flags_reg(ctx, v11, v14); |
18157 | 1.56k | let v16 = C::value_reg(ctx, v15); |
18158 | 1.56k | // Rule at src/isa/x64/lower.isle line 1296. |
18159 | 1.56k | return v16; |
18160 | 0 | } |
18161 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "cmp_and_choose", "src/isa/x64/lower.isle line 1295") |
18162 | 1.56k | } |
18163 | | |
18164 | | // Generated as internal constructor for term lower_select_fcmp. |
18165 | 0 | pub fn constructor_lower_select_fcmp<C: Context>( |
18166 | 0 | ctx: &mut C, |
18167 | 0 | arg0: Type, |
18168 | 0 | arg1: &FcmpCondResult, |
18169 | 0 | arg2: Value, |
18170 | 0 | arg3: Value, |
18171 | 0 | ) -> InstOutput { |
18172 | 0 | match arg1 { |
18173 | | &FcmpCondResult::Condition { |
18174 | 0 | producer: ref v2, |
18175 | 0 | cc: ref v3, |
18176 | 0 | } => { |
18177 | 0 | let v6 = &constructor_cmove_from_values(ctx, arg0, v3, arg2, arg3); |
18178 | 0 | let v7 = constructor_with_flags(ctx, v2, v6); |
18179 | 0 | let v8 = C::output(ctx, v7); |
18180 | 0 | // Rule at src/isa/x64/lower.isle line 1588. |
18181 | 0 | return v8; |
18182 | | } |
18183 | | &FcmpCondResult::OrCondition { |
18184 | 0 | producer: ref v9, |
18185 | 0 | cc1: ref v10, |
18186 | 0 | cc2: ref v11, |
18187 | 0 | } => { |
18188 | 0 | let v12 = &constructor_cmove_or_from_values(ctx, arg0, v10, v11, arg2, arg3); |
18189 | 0 | let v13 = constructor_with_flags(ctx, v9, v12); |
18190 | 0 | let v14 = C::output(ctx, v13); |
18191 | 0 | // Rule at src/isa/x64/lower.isle line 1590. |
18192 | 0 | return v14; |
18193 | | } |
18194 | 0 | _ => {} |
18195 | 0 | } |
18196 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "lower_select_fcmp", "src/isa/x64/lower.isle line 1587") |
18197 | 0 | } |
18198 | | |
18199 | | // Generated as internal constructor for term do_clz. |
18200 | 0 | pub fn constructor_do_clz<C: Context>( |
18201 | 0 | ctx: &mut C, |
18202 | 0 | arg0: Type, |
18203 | 0 | arg1: Type, |
18204 | 0 | arg2: Gpr, |
18205 | 0 | ) -> Gpr { |
18206 | 0 | let v5 = constructor_imm_i64(ctx, I64, -0x1); |
18207 | 0 | let v6 = C::gpr_new(ctx, v5); |
18208 | 0 | let v7 = constructor_bsr_or_else(ctx, arg0, arg2, v6); |
18209 | 0 | let v8 = C::gpr_to_reg(ctx, v7); |
18210 | 0 | let v9 = C::ty_bits_u64(ctx, arg1); |
18211 | 0 | let v11 = C::u64_sub(ctx, v9, 0x1); |
18212 | 0 | let v12 = constructor_imm(ctx, arg0, v11); |
18213 | 0 | let v13 = C::gpr_new(ctx, v12); |
18214 | 0 | let v14 = &constructor_reg_to_gpr_mem_imm(ctx, v8); |
18215 | 0 | let v15 = constructor_x64_sub(ctx, arg0, v13, v14); |
18216 | 0 | // Rule at src/isa/x64/lower.isle line 1656. |
18217 | 0 | return v15; |
18218 | 0 | } |
18219 | | |
18220 | | // Generated as internal constructor for term do_ctz. |
18221 | 0 | pub fn constructor_do_ctz<C: Context>( |
18222 | 0 | ctx: &mut C, |
18223 | 0 | arg0: Type, |
18224 | 0 | arg1: Type, |
18225 | 0 | arg2: Gpr, |
18226 | 0 | ) -> Gpr { |
18227 | 0 | let v4 = C::ty_bits_u64(ctx, arg1); |
18228 | 0 | let v5 = constructor_imm(ctx, I64, v4); |
18229 | 0 | let v6 = C::gpr_new(ctx, v5); |
18230 | 0 | let v7 = constructor_bsf_or_else(ctx, arg0, arg2, v6); |
18231 | 0 | // Rule at src/isa/x64/lower.isle line 1699. |
18232 | 0 | return v7; |
18233 | 0 | } |
18234 | | |
18235 | | // Generated as internal constructor for term do_popcnt. |
18236 | 0 | pub fn constructor_do_popcnt<C: Context>( |
18237 | 0 | ctx: &mut C, |
18238 | 0 | arg0: Type, |
18239 | 0 | arg1: Gpr, |
18240 | 0 | ) -> Gpr { |
18241 | 0 | match arg0 { |
18242 | | I32 => { |
18243 | 0 | let v4 = Imm8Reg::Imm8 { |
18244 | 0 | imm: 0x1, |
18245 | 0 | }; |
18246 | 0 | let v5 = &C::imm8_reg_to_imm8_gpr(ctx, &v4); |
18247 | 0 | let v47 = constructor_x64_shr(ctx, I32, arg1, v5); |
18248 | 0 | let v49 = constructor_imm(ctx, I32, 0x77777777); |
18249 | 0 | let v50 = C::gpr_new(ctx, v49); |
18250 | 0 | let v51 = &C::gpr_to_gpr_mem_imm(ctx, v50); |
18251 | 0 | let v52 = constructor_x64_and(ctx, I32, v47, v51); |
18252 | 0 | let v53 = &C::gpr_to_gpr_mem_imm(ctx, v52); |
18253 | 0 | let v54 = constructor_x64_sub(ctx, I32, arg1, v53); |
18254 | 0 | let v14 = &C::imm8_reg_to_imm8_gpr(ctx, &v4); |
18255 | 0 | let v55 = constructor_x64_shr(ctx, I32, v52, v14); |
18256 | 0 | let v56 = &C::gpr_to_gpr_mem_imm(ctx, v50); |
18257 | 0 | let v57 = constructor_x64_and(ctx, I32, v55, v56); |
18258 | 0 | let v58 = &C::gpr_to_gpr_mem_imm(ctx, v57); |
18259 | 0 | let v59 = constructor_x64_sub(ctx, I32, v54, v58); |
18260 | 0 | let v20 = &C::imm8_reg_to_imm8_gpr(ctx, &v4); |
18261 | 0 | let v60 = constructor_x64_shr(ctx, I32, v57, v20); |
18262 | 0 | let v61 = &C::gpr_to_gpr_mem_imm(ctx, v50); |
18263 | 0 | let v62 = constructor_x64_and(ctx, I32, v60, v61); |
18264 | 0 | let v63 = &C::gpr_to_gpr_mem_imm(ctx, v62); |
18265 | 0 | let v64 = constructor_x64_sub(ctx, I32, v59, v63); |
18266 | 0 | let v27 = Imm8Reg::Imm8 { |
18267 | 0 | imm: 0x4, |
18268 | 0 | }; |
18269 | 0 | let v28 = &C::imm8_reg_to_imm8_gpr(ctx, &v27); |
18270 | 0 | let v65 = constructor_x64_shr(ctx, I32, v64, v28); |
18271 | 0 | let v66 = &C::gpr_to_gpr_mem_imm(ctx, v64); |
18272 | 0 | let v67 = constructor_x64_add(ctx, I32, v65, v66); |
18273 | 0 | let v69 = RegMemImm::Imm { |
18274 | 0 | simm32: 0xF0F0F0F, |
18275 | 0 | }; |
18276 | 0 | let v70 = &C::gpr_mem_imm_new(ctx, &v69); |
18277 | 0 | let v71 = constructor_x64_and(ctx, I32, v67, v70); |
18278 | 0 | let v73 = RegMemImm::Imm { |
18279 | 0 | simm32: 0x1010101, |
18280 | 0 | }; |
18281 | 0 | let v74 = &C::gpr_mem_imm_new(ctx, &v73); |
18282 | 0 | let v75 = constructor_x64_mul(ctx, I32, v71, v74); |
18283 | 0 | let v77 = Imm8Reg::Imm8 { |
18284 | 0 | imm: 0x18, |
18285 | 0 | }; |
18286 | 0 | let v78 = &C::imm8_reg_to_imm8_gpr(ctx, &v77); |
18287 | 0 | let v79 = constructor_x64_shr(ctx, I32, v75, v78); |
18288 | 0 | // Rule at src/isa/x64/lower.isle line 1790. |
18289 | 0 | return v79; |
18290 | | } |
18291 | | I64 => { |
18292 | 0 | let v4 = Imm8Reg::Imm8 { |
18293 | 0 | imm: 0x1, |
18294 | 0 | }; |
18295 | 0 | let v5 = &C::imm8_reg_to_imm8_gpr(ctx, &v4); |
18296 | 0 | let v6 = constructor_x64_shr(ctx, I64, arg1, v5); |
18297 | 0 | let v8 = constructor_imm(ctx, I64, 0x7777777777777777); |
18298 | 0 | let v9 = C::gpr_new(ctx, v8); |
18299 | 0 | let v10 = &C::gpr_to_gpr_mem_imm(ctx, v9); |
18300 | 0 | let v11 = constructor_x64_and(ctx, I64, v6, v10); |
18301 | 0 | let v12 = &C::gpr_to_gpr_mem_imm(ctx, v11); |
18302 | 0 | let v13 = constructor_x64_sub(ctx, I64, arg1, v12); |
18303 | 0 | let v14 = &C::imm8_reg_to_imm8_gpr(ctx, &v4); |
18304 | 0 | let v15 = constructor_x64_shr(ctx, I64, v11, v14); |
18305 | 0 | let v16 = &C::gpr_to_gpr_mem_imm(ctx, v9); |
18306 | 0 | let v17 = constructor_x64_and(ctx, I64, v15, v16); |
18307 | 0 | let v18 = &C::gpr_to_gpr_mem_imm(ctx, v17); |
18308 | 0 | let v19 = constructor_x64_sub(ctx, I64, v13, v18); |
18309 | 0 | let v20 = &C::imm8_reg_to_imm8_gpr(ctx, &v4); |
18310 | 0 | let v21 = constructor_x64_shr(ctx, I64, v17, v20); |
18311 | 0 | let v22 = &C::gpr_to_gpr_mem_imm(ctx, v9); |
18312 | 0 | let v23 = constructor_x64_and(ctx, I64, v21, v22); |
18313 | 0 | let v24 = &C::gpr_to_gpr_mem_imm(ctx, v23); |
18314 | 0 | let v25 = constructor_x64_sub(ctx, I64, v19, v24); |
18315 | 0 | let v27 = Imm8Reg::Imm8 { |
18316 | 0 | imm: 0x4, |
18317 | 0 | }; |
18318 | 0 | let v28 = &C::imm8_reg_to_imm8_gpr(ctx, &v27); |
18319 | 0 | let v29 = constructor_x64_shr(ctx, I64, v25, v28); |
18320 | 0 | let v30 = &C::gpr_to_gpr_mem_imm(ctx, v25); |
18321 | 0 | let v31 = constructor_x64_add(ctx, I64, v29, v30); |
18322 | 0 | let v33 = constructor_imm(ctx, I64, 0xF0F0F0F0F0F0F0F); |
18323 | 0 | let v34 = C::gpr_new(ctx, v33); |
18324 | 0 | let v35 = &C::gpr_to_gpr_mem_imm(ctx, v34); |
18325 | 0 | let v36 = constructor_x64_and(ctx, I64, v31, v35); |
18326 | 0 | let v38 = constructor_imm(ctx, I64, 0x101010101010101); |
18327 | 0 | let v39 = C::gpr_new(ctx, v38); |
18328 | 0 | let v40 = &C::gpr_to_gpr_mem_imm(ctx, v39); |
18329 | 0 | let v41 = constructor_x64_mul(ctx, I64, v36, v40); |
18330 | 0 | let v43 = Imm8Reg::Imm8 { |
18331 | 0 | imm: 0x38, |
18332 | 0 | }; |
18333 | 0 | let v44 = &C::imm8_reg_to_imm8_gpr(ctx, &v43); |
18334 | 0 | let v45 = constructor_x64_shr(ctx, I64, v41, v44); |
18335 | 0 | // Rule at src/isa/x64/lower.isle line 1747. |
18336 | 0 | return v45; |
18337 | | } |
18338 | 0 | _ => {} |
18339 | 0 | } |
18340 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "do_popcnt", "src/isa/x64/lower.isle line 1746") |
18341 | 0 | } |
18342 | | |
18343 | | // Generated as internal constructor for term do_bitrev8. |
18344 | 0 | pub fn constructor_do_bitrev8<C: Context>( |
18345 | 0 | ctx: &mut C, |
18346 | 0 | arg0: Type, |
18347 | 0 | arg1: Gpr, |
18348 | 0 | ) -> Gpr { |
18349 | 0 | let v2 = C::ty_mask(ctx, arg0); |
18350 | 0 | let v4 = C::u64_and(ctx, v2, 0x5555555555555555); |
18351 | 0 | let v5 = constructor_imm(ctx, arg0, v4); |
18352 | 0 | let v6 = C::gpr_new(ctx, v5); |
18353 | 0 | let v7 = &C::gpr_to_gpr_mem_imm(ctx, v6); |
18354 | 0 | let v8 = constructor_x64_and(ctx, arg0, arg1, v7); |
18355 | 0 | let v10 = Imm8Reg::Imm8 { |
18356 | 0 | imm: 0x1, |
18357 | 0 | }; |
18358 | 0 | let v11 = &C::imm8_reg_to_imm8_gpr(ctx, &v10); |
18359 | 0 | let v12 = constructor_x64_shr(ctx, arg0, arg1, v11); |
18360 | 0 | let v13 = &C::gpr_to_gpr_mem_imm(ctx, v6); |
18361 | 0 | let v14 = constructor_x64_and(ctx, arg0, v12, v13); |
18362 | 0 | let v15 = &C::imm8_reg_to_imm8_gpr(ctx, &v10); |
18363 | 0 | let v16 = constructor_x64_shl(ctx, arg0, v8, v15); |
18364 | 0 | let v17 = &C::gpr_to_gpr_mem_imm(ctx, v14); |
18365 | 0 | let v18 = constructor_x64_or(ctx, arg0, v16, v17); |
18366 | 0 | let v20 = C::u64_and(ctx, v2, 0x3333333333333333); |
18367 | 0 | let v21 = constructor_imm(ctx, arg0, v20); |
18368 | 0 | let v22 = C::gpr_new(ctx, v21); |
18369 | 0 | let v23 = &C::gpr_to_gpr_mem_imm(ctx, v22); |
18370 | 0 | let v24 = constructor_x64_and(ctx, arg0, v18, v23); |
18371 | 0 | let v26 = Imm8Reg::Imm8 { |
18372 | 0 | imm: 0x2, |
18373 | 0 | }; |
18374 | 0 | let v27 = &C::imm8_reg_to_imm8_gpr(ctx, &v26); |
18375 | 0 | let v28 = constructor_x64_shr(ctx, arg0, v18, v27); |
18376 | 0 | let v29 = &C::gpr_to_gpr_mem_imm(ctx, v22); |
18377 | 0 | let v30 = constructor_x64_and(ctx, arg0, v28, v29); |
18378 | 0 | let v31 = &C::imm8_reg_to_imm8_gpr(ctx, &v26); |
18379 | 0 | let v32 = constructor_x64_shl(ctx, arg0, v24, v31); |
18380 | 0 | let v33 = &C::gpr_to_gpr_mem_imm(ctx, v30); |
18381 | 0 | let v34 = constructor_x64_or(ctx, arg0, v32, v33); |
18382 | 0 | let v36 = C::u64_and(ctx, v2, 0xF0F0F0F0F0F0F0F); |
18383 | 0 | let v37 = constructor_imm(ctx, arg0, v36); |
18384 | 0 | let v38 = C::gpr_new(ctx, v37); |
18385 | 0 | let v39 = &C::gpr_to_gpr_mem_imm(ctx, v38); |
18386 | 0 | let v40 = constructor_x64_and(ctx, arg0, v34, v39); |
18387 | 0 | let v42 = Imm8Reg::Imm8 { |
18388 | 0 | imm: 0x4, |
18389 | 0 | }; |
18390 | 0 | let v43 = &C::imm8_reg_to_imm8_gpr(ctx, &v42); |
18391 | 0 | let v44 = constructor_x64_shr(ctx, arg0, v34, v43); |
18392 | 0 | let v45 = &C::gpr_to_gpr_mem_imm(ctx, v38); |
18393 | 0 | let v46 = constructor_x64_and(ctx, arg0, v44, v45); |
18394 | 0 | let v47 = &C::imm8_reg_to_imm8_gpr(ctx, &v42); |
18395 | 0 | let v48 = constructor_x64_shl(ctx, arg0, v40, v47); |
18396 | 0 | let v49 = &C::gpr_to_gpr_mem_imm(ctx, v46); |
18397 | 0 | let v50 = constructor_x64_or(ctx, arg0, v48, v49); |
18398 | 0 | // Rule at src/isa/x64/lower.isle line 1879. |
18399 | 0 | return v50; |
18400 | 0 | } |
18401 | | |
18402 | | // Generated as internal constructor for term do_bitrev16. |
18403 | 0 | pub fn constructor_do_bitrev16<C: Context>( |
18404 | 0 | ctx: &mut C, |
18405 | 0 | arg0: Type, |
18406 | 0 | arg1: Gpr, |
18407 | 0 | ) -> Gpr { |
18408 | 0 | let v2 = constructor_do_bitrev8(ctx, arg0, arg1); |
18409 | 0 | let v3 = C::ty_mask(ctx, arg0); |
18410 | 0 | let v5 = C::u64_and(ctx, v3, 0xFF00FF00FF00FF); |
18411 | 0 | let v6 = constructor_imm(ctx, arg0, v5); |
18412 | 0 | let v7 = C::gpr_new(ctx, v6); |
18413 | 0 | let v8 = &C::gpr_to_gpr_mem_imm(ctx, v7); |
18414 | 0 | let v9 = constructor_x64_and(ctx, arg0, v2, v8); |
18415 | 0 | let v11 = Imm8Reg::Imm8 { |
18416 | 0 | imm: 0x8, |
18417 | 0 | }; |
18418 | 0 | let v12 = &C::imm8_reg_to_imm8_gpr(ctx, &v11); |
18419 | 0 | let v13 = constructor_x64_shr(ctx, arg0, v2, v12); |
18420 | 0 | let v14 = &C::gpr_to_gpr_mem_imm(ctx, v7); |
18421 | 0 | let v15 = constructor_x64_and(ctx, arg0, v13, v14); |
18422 | 0 | let v16 = &C::imm8_reg_to_imm8_gpr(ctx, &v11); |
18423 | 0 | let v17 = constructor_x64_shl(ctx, arg0, v9, v16); |
18424 | 0 | let v18 = &C::gpr_to_gpr_mem_imm(ctx, v15); |
18425 | 0 | let v19 = constructor_x64_or(ctx, arg0, v17, v18); |
18426 | 0 | // Rule at src/isa/x64/lower.isle line 1902. |
18427 | 0 | return v19; |
18428 | 0 | } |
18429 | | |
18430 | | // Generated as internal constructor for term do_bitrev32. |
18431 | 0 | pub fn constructor_do_bitrev32<C: Context>( |
18432 | 0 | ctx: &mut C, |
18433 | 0 | arg0: Type, |
18434 | 0 | arg1: Gpr, |
18435 | 0 | ) -> Gpr { |
18436 | 0 | let v2 = constructor_do_bitrev16(ctx, arg0, arg1); |
18437 | 0 | let v3 = C::ty_mask(ctx, arg0); |
18438 | 0 | let v5 = C::u64_and(ctx, v3, 0xFFFF0000FFFF); |
18439 | 0 | let v6 = constructor_imm(ctx, arg0, v5); |
18440 | 0 | let v7 = C::gpr_new(ctx, v6); |
18441 | 0 | let v8 = &C::gpr_to_gpr_mem_imm(ctx, v7); |
18442 | 0 | let v9 = constructor_x64_and(ctx, arg0, v2, v8); |
18443 | 0 | let v11 = Imm8Reg::Imm8 { |
18444 | 0 | imm: 0x10, |
18445 | 0 | }; |
18446 | 0 | let v12 = &C::imm8_reg_to_imm8_gpr(ctx, &v11); |
18447 | 0 | let v13 = constructor_x64_shr(ctx, arg0, v2, v12); |
18448 | 0 | let v14 = &C::gpr_to_gpr_mem_imm(ctx, v7); |
18449 | 0 | let v15 = constructor_x64_and(ctx, arg0, v13, v14); |
18450 | 0 | let v16 = &C::imm8_reg_to_imm8_gpr(ctx, &v11); |
18451 | 0 | let v17 = constructor_x64_shl(ctx, arg0, v9, v16); |
18452 | 0 | let v18 = &C::gpr_to_gpr_mem_imm(ctx, v15); |
18453 | 0 | let v19 = constructor_x64_or(ctx, arg0, v17, v18); |
18454 | 0 | // Rule at src/isa/x64/lower.isle line 1914. |
18455 | 0 | return v19; |
18456 | 0 | } |
18457 | | |
18458 | | // Generated as internal constructor for term do_bitrev64. |
18459 | 0 | pub fn constructor_do_bitrev64<C: Context>( |
18460 | 0 | ctx: &mut C, |
18461 | 0 | arg0: Type, |
18462 | 0 | arg1: Gpr, |
18463 | 0 | ) -> Gpr { |
18464 | 0 | if arg0 == I64 { |
18465 | 0 | let v2 = constructor_do_bitrev32(ctx, arg0, arg1); |
18466 | 0 | let v4 = constructor_imm(ctx, arg0, 0xFFFFFFFF); |
18467 | 0 | let v5 = C::gpr_new(ctx, v4); |
18468 | 0 | let v6 = &C::gpr_to_gpr_mem_imm(ctx, v5); |
18469 | 0 | let v7 = constructor_x64_and(ctx, arg0, v2, v6); |
18470 | 0 | let v9 = Imm8Reg::Imm8 { |
18471 | 0 | imm: 0x20, |
18472 | 0 | }; |
18473 | 0 | let v10 = &C::imm8_reg_to_imm8_gpr(ctx, &v9); |
18474 | 0 | let v11 = constructor_x64_shr(ctx, arg0, v2, v10); |
18475 | 0 | let v12 = &C::imm8_reg_to_imm8_gpr(ctx, &v9); |
18476 | 0 | let v13 = constructor_x64_shl(ctx, arg0, v7, v12); |
18477 | 0 | let v14 = &C::gpr_to_gpr_mem_imm(ctx, v11); |
18478 | 0 | let v15 = constructor_x64_or(ctx, arg0, v13, v14); |
18479 | 0 | // Rule at src/isa/x64/lower.isle line 1926. |
18480 | 0 | return v15; |
18481 | 0 | } |
18482 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "do_bitrev64", "src/isa/x64/lower.isle line 1925") |
18483 | 0 | } |
18484 | | |
18485 | | // Generated as internal constructor for term fmadd. |
18486 | 0 | pub fn constructor_fmadd<C: Context>( |
18487 | 0 | ctx: &mut C, |
18488 | 0 | arg0: Type, |
18489 | 0 | arg1: Value, |
18490 | 0 | arg2: Value, |
18491 | 0 | arg3: Value, |
18492 | 0 | ) -> Xmm { |
18493 | 0 | let v24 = C::def_inst(ctx, arg2); |
18494 | 0 | if let Some(v25) = v24 { |
18495 | 0 | let v26 = &C::inst_data(ctx, v25); |
18496 | | if let &InstructionData::Unary { |
18497 | 0 | opcode: ref v27, |
18498 | 0 | arg: v28, |
18499 | 0 | } = v26 { |
18500 | 0 | if let &Opcode::Fneg = v27 { |
18501 | 0 | let v29 = constructor_fnmadd(ctx, arg0, arg1, v28, arg3); |
18502 | 0 | // Rule at src/isa/x64/lower.isle line 2381. |
18503 | 0 | return v29; |
18504 | 0 | } |
18505 | 0 | } |
18506 | 0 | } |
18507 | 0 | let v18 = C::def_inst(ctx, arg1); |
18508 | 0 | if let Some(v19) = v18 { |
18509 | 0 | let v20 = &C::inst_data(ctx, v19); |
18510 | | if let &InstructionData::Unary { |
18511 | 0 | opcode: ref v21, |
18512 | 0 | arg: v22, |
18513 | 0 | } = v20 { |
18514 | 0 | if let &Opcode::Fneg = v21 { |
18515 | 0 | let v23 = constructor_fnmadd(ctx, arg0, v22, arg2, arg3); |
18516 | 0 | // Rule at src/isa/x64/lower.isle line 2380. |
18517 | 0 | return v23; |
18518 | 0 | } |
18519 | 0 | } |
18520 | 0 | } |
18521 | 0 | let v14 = &C::sinkable_load(ctx, arg2); |
18522 | 0 | if let Some(v15) = v14 { |
18523 | 0 | let v4 = constructor_put_in_xmm(ctx, arg1); |
18524 | 0 | let v11 = constructor_put_in_xmm(ctx, arg3); |
18525 | 0 | let v16 = &constructor_sink_load_to_xmm_mem(ctx, v15); |
18526 | 0 | let v17 = constructor_x64_vfmadd132(ctx, arg0, v4, v11, v16); |
18527 | 0 | // Rule at src/isa/x64/lower.isle line 2376. |
18528 | 0 | return v17; |
18529 | 0 | } |
18530 | 0 | let v8 = &C::sinkable_load(ctx, arg1); |
18531 | 0 | if let Some(v9) = v8 { |
18532 | 0 | let v10 = constructor_put_in_xmm(ctx, arg2); |
18533 | 0 | let v11 = constructor_put_in_xmm(ctx, arg3); |
18534 | 0 | let v12 = &constructor_sink_load_to_xmm_mem(ctx, v9); |
18535 | 0 | let v13 = constructor_x64_vfmadd132(ctx, arg0, v10, v11, v12); |
18536 | 0 | // Rule at src/isa/x64/lower.isle line 2375. |
18537 | 0 | return v13; |
18538 | 0 | } |
18539 | 0 | let v4 = constructor_put_in_xmm(ctx, arg1); |
18540 | 0 | let v5 = constructor_put_in_xmm(ctx, arg2); |
18541 | 0 | let v6 = &C::put_in_xmm_mem(ctx, arg3); |
18542 | 0 | let v7 = constructor_x64_vfmadd213(ctx, arg0, v4, v5, v6); |
18543 | 0 | // Rule at src/isa/x64/lower.isle line 2370. |
18544 | 0 | return v7; |
18545 | 0 | } |
18546 | | |
18547 | | // Generated as internal constructor for term fnmadd. |
18548 | 0 | pub fn constructor_fnmadd<C: Context>( |
18549 | 0 | ctx: &mut C, |
18550 | 0 | arg0: Type, |
18551 | 0 | arg1: Value, |
18552 | 0 | arg2: Value, |
18553 | 0 | arg3: Value, |
18554 | 0 | ) -> Xmm { |
18555 | 0 | let v24 = C::def_inst(ctx, arg2); |
18556 | 0 | if let Some(v25) = v24 { |
18557 | 0 | let v26 = &C::inst_data(ctx, v25); |
18558 | | if let &InstructionData::Unary { |
18559 | 0 | opcode: ref v27, |
18560 | 0 | arg: v28, |
18561 | 0 | } = v26 { |
18562 | 0 | if let &Opcode::Fneg = v27 { |
18563 | 0 | let v29 = constructor_fmadd(ctx, arg0, arg1, v28, arg3); |
18564 | 0 | // Rule at src/isa/x64/lower.isle line 2389. |
18565 | 0 | return v29; |
18566 | 0 | } |
18567 | 0 | } |
18568 | 0 | } |
18569 | 0 | let v18 = C::def_inst(ctx, arg1); |
18570 | 0 | if let Some(v19) = v18 { |
18571 | 0 | let v20 = &C::inst_data(ctx, v19); |
18572 | | if let &InstructionData::Unary { |
18573 | 0 | opcode: ref v21, |
18574 | 0 | arg: v22, |
18575 | 0 | } = v20 { |
18576 | 0 | if let &Opcode::Fneg = v21 { |
18577 | 0 | let v23 = constructor_fmadd(ctx, arg0, v22, arg2, arg3); |
18578 | 0 | // Rule at src/isa/x64/lower.isle line 2388. |
18579 | 0 | return v23; |
18580 | 0 | } |
18581 | 0 | } |
18582 | 0 | } |
18583 | 0 | let v14 = &C::sinkable_load(ctx, arg2); |
18584 | 0 | if let Some(v15) = v14 { |
18585 | 0 | let v4 = constructor_put_in_xmm(ctx, arg1); |
18586 | 0 | let v11 = constructor_put_in_xmm(ctx, arg3); |
18587 | 0 | let v16 = &constructor_sink_load_to_xmm_mem(ctx, v15); |
18588 | 0 | let v17 = constructor_x64_vfnmadd132(ctx, arg0, v4, v11, v16); |
18589 | 0 | // Rule at src/isa/x64/lower.isle line 2385. |
18590 | 0 | return v17; |
18591 | 0 | } |
18592 | 0 | let v8 = &C::sinkable_load(ctx, arg1); |
18593 | 0 | if let Some(v9) = v8 { |
18594 | 0 | let v10 = constructor_put_in_xmm(ctx, arg2); |
18595 | 0 | let v11 = constructor_put_in_xmm(ctx, arg3); |
18596 | 0 | let v12 = &constructor_sink_load_to_xmm_mem(ctx, v9); |
18597 | 0 | let v13 = constructor_x64_vfnmadd132(ctx, arg0, v10, v11, v12); |
18598 | 0 | // Rule at src/isa/x64/lower.isle line 2384. |
18599 | 0 | return v13; |
18600 | 0 | } |
18601 | 0 | let v4 = constructor_put_in_xmm(ctx, arg1); |
18602 | 0 | let v5 = constructor_put_in_xmm(ctx, arg2); |
18603 | 0 | let v6 = &C::put_in_xmm_mem(ctx, arg3); |
18604 | 0 | let v7 = constructor_x64_vfnmadd213(ctx, arg0, v4, v5, v6); |
18605 | 0 | // Rule at src/isa/x64/lower.isle line 2383. |
18606 | 0 | return v7; |
18607 | 0 | } |
18608 | | |
18609 | | // Generated as internal constructor for term cmp_zero_i128. |
18610 | 0 | pub fn constructor_cmp_zero_i128<C: Context>( |
18611 | 0 | ctx: &mut C, |
18612 | 0 | arg0: &CC, |
18613 | 0 | arg1: ValueRegs, |
18614 | 0 | ) -> IcmpCondResult { |
18615 | 0 | let v1 = &C::cc_nz_or_z(ctx, arg0); |
18616 | 0 | if let Some(v2) = v1 { |
18617 | 0 | let v5 = constructor_value_regs_get_gpr(ctx, arg1, 0x0); |
18618 | 0 | let v7 = constructor_value_regs_get_gpr(ctx, arg1, 0x1); |
18619 | 0 | let v10 = RegMemImm::Imm { |
18620 | 0 | simm32: 0x0, |
18621 | 0 | }; |
18622 | 0 | let v11 = &C::gpr_mem_imm_new(ctx, &v10); |
18623 | 0 | let v12 = &constructor_x64_cmp(ctx, &OperandSize::Size64, v11, v5); |
18624 | 0 | let v14 = &constructor_x64_setcc(ctx, &CC::Z); |
18625 | 0 | let v15 = constructor_with_flags_reg(ctx, v12, v14); |
18626 | 0 | let v16 = C::gpr_new(ctx, v15); |
18627 | 0 | let v17 = &C::gpr_mem_imm_new(ctx, &v10); |
18628 | 0 | let v18 = &constructor_x64_cmp(ctx, &OperandSize::Size64, v17, v7); |
18629 | 0 | let v19 = &constructor_x64_setcc(ctx, &CC::Z); |
18630 | 0 | let v20 = constructor_with_flags_reg(ctx, v18, v19); |
18631 | 0 | let v21 = C::gpr_new(ctx, v20); |
18632 | 0 | let v23 = &C::gpr_to_gpr_mem_imm(ctx, v16); |
18633 | 0 | let v24 = &constructor_x64_test(ctx, &OperandSize::Size8, v23, v21); |
18634 | 0 | let v25 = &constructor_icmp_cond_result(ctx, v24, v2); |
18635 | 0 | // Rule at src/isa/x64/lower.isle line 2821. |
18636 | 0 | return v25.clone(); |
18637 | 0 | } |
18638 | 0 | unreachable!("no rule matched for term {} at {}; should it be partial?", "cmp_zero_i128", "src/isa/x64/lower.isle line 2820") |
18639 | 0 | } |
18640 | | |
18641 | | // Generated as internal constructor for term cmp_zero_int_bool_ref. |
18642 | 70.1k | pub fn constructor_cmp_zero_int_bool_ref<C: Context>( |
18643 | 70.1k | ctx: &mut C, |
18644 | 70.1k | arg0: Value, |
18645 | 70.1k | ) -> ProducesFlags { |
18646 | 70.1k | let v1 = C::value_type(ctx, arg0); |
18647 | 70.1k | let v2 = &C::raw_operand_size_of_type(ctx, v1); |
18648 | 70.1k | let v3 = constructor_put_in_gpr(ctx, arg0); |
18649 | 70.1k | let v4 = &C::gpr_to_gpr_mem_imm(ctx, v3); |
18650 | 70.1k | let v5 = &constructor_x64_test(ctx, v2, v4, v3); |
18651 | 70.1k | // Rule at src/isa/x64/lower.isle line 2832. |
18652 | 70.1k | return v5.clone(); |
18653 | 70.1k | } |
18654 | | |
18655 | | // Generated as internal constructor for term nonzero_sdiv_divisor. |
18656 | 121 | pub fn constructor_nonzero_sdiv_divisor<C: Context>( |
18657 | 121 | ctx: &mut C, |
18658 | 121 | arg0: Type, |
18659 | 121 | arg1: Value, |
18660 | 121 | ) -> Reg { |
18661 | 121 | let v2 = C::def_inst(ctx, arg1); |
18662 | 121 | if let Some(v3) = v2 { |
18663 | 121 | let v4 = &C::inst_data(ctx, v3); |
18664 | | if let &InstructionData::UnaryImm { |
18665 | 121 | opcode: ref v5, |
18666 | 121 | imm: v6, |
18667 | 121 | } = v4 { |
18668 | 121 | if let &Opcode::Iconst = v5 { |
18669 | 121 | let v7 = C::safe_divisor_from_imm64(ctx, arg0, v6); |
18670 | 121 | if let Some(v8) = v7 { |
18671 | 121 | let v9 = constructor_imm(ctx, arg0, v8); |
18672 | 121 | // Rule at src/isa/x64/lower.isle line 3425. |
18673 | 121 | return v9; |
18674 | 0 | } |
18675 | 0 | } |
18676 | 0 | } |
18677 | 0 | } |
18678 | 0 | let v10 = C::put_in_reg(ctx, arg1); |
18679 | 0 | let v11 = &C::raw_operand_size_of_type(ctx, arg0); |
18680 | 0 | let v12 = &constructor_reg_to_gpr_mem_imm(ctx, v10); |
18681 | 0 | let v13 = C::gpr_new(ctx, v10); |
18682 | 0 | let v14 = &constructor_x64_test(ctx, v11, v12, v13); |
18683 | 0 | let v17 = &constructor_trap_if(ctx, &CC::Z, &TrapCode::IntegerDivisionByZero); |
18684 | 0 | let v18 = &constructor_with_flags_side_effect(ctx, v14, v17); |
18685 | 0 | let v19 = constructor_side_effect(ctx, v18); |
18686 | 0 | // Rule at src/isa/x64/lower.isle line 3428. |
18687 | 0 | return v10; |
18688 | 121 | } |